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172 Commits

Author SHA1 Message Date
H. Peter Anvin
ff6e12da50 Reshuffle and move the bytecodes for segment register push/pop 
Reshuffle the bytecodes for segment register push/pop to make more
sense, and move them from \4 to \344, thus freeing up the single-digit
bytecodes \4..\7 for future use.  It doesn't really make sense to use
single-digit bytecodes for this very oddball use.

Signed-off-by: H. Peter Anvin <hpa@zytor.com>
 2008-10-08 21:17:32 -07:00
H. Peter Anvin
65feb5ae33 Add missing IMUL pattern: reg64,imm8 
Make "imul rax,byte 5" work as expected.

Signed-off-by: H. Peter Anvin <hpa@zytor.com>
 2008-10-07 11:26:41 -07:00
H. Peter Anvin
37c6d166d2 Add a few missing \15 -> \275 conversions 
Add a few \15 -> \275 conversions that had been missed earlier.
Still haven't done the work on IMUL.

Signed-off-by: H. Peter Anvin <hpa@zytor.com>
 2008-10-07 10:56:32 -07:00
H. Peter Anvin
55f58acdae Change \40 class opcodes to \254, except IMUL 
Change \40 class opcodes which need to be changed to \254.  IMUL will
need a separate audit; I'm not convinced we are really sure what all
the IMUL conditions should be.

Signed-off-by: H. Peter Anvin <hpa@zytor.com>
 2008-10-07 10:53:08 -07:00
H. Peter Anvin
588df78b0d New opcode for 32->64 bit sign-extended immediate with warning 
Add a new opcode for 32->64 bit sign-extended immediate, with warning
on the number not matching.

This unfortunately calls for an audit of all the \4[0123] opcodes, if
they should be replaced by \25[4567].  This only replaces one
instruction (MOV reg64,imm32); other instructions need to be
considered.

Signed-off-by: H. Peter Anvin <hpa@zytor.com>
 2008-10-07 10:05:10 -07:00
H. Peter Anvin
c1377e9a98 New opcodes to deal with 8-bit immediate sign extended to opsize 
New opcodes to deal with 8-bit immediates which are then sign-extended
to the operand size.  These allow us to warn appropriately.
Not sure I'm using these in all the proper places; need audit of all
uses of the \14..\17 opcodes.

Signed-off-by: H. Peter Anvin <hpa@zytor.com>
 2008-10-06 23:40:31 -07:00
H. Peter Anvin
e9d7f1a074 Better warnings for out-of-range values 
Issue better warnings for out-of-range values.  This is not yet
complete.

In particular, note we may have out-of-range for values that end up
being subject to optimization.  That is because the optimization takes
place on the *truncated* value, not the pre-truncated value.

Signed-off-by: H. Peter Anvin <hpa@zytor.com>
 2008-10-06 18:47:29 -07:00
H. Peter Anvin
ee6789ceb1 BR 2148476: Fix arguments for a bunch of the CVT* instructions 
Fix bugs exposed by test for BR 2148476.

Signed-off-by: H. Peter Anvin <hpa@zytor.com>
 2008-10-06 17:58:57 -07:00
H. Peter Anvin
6f87180c3f JMP reg64 does not require a REX.W prefix. 
We were redundantly emitting a REX.W prefix for JMP reg64.

Signed-off-by: H. Peter Anvin <hpa@zytor.com>
 2008-09-25 23:42:28 -07:00
H. Peter Anvin
163e5874d9 Accept implicit memory size for VMREAD/VMWRITE 2008-08-28 18:05:23 -07:00
H. Peter Anvin
5e7d6f1105 BR 2029472: Wrong operand size for VMREAD/VMWRITE in 64-bit mode 
Fix the operand size for VMREAD/VMWRITE in 64-bit mode
 2008-08-28 18:03:49 -07:00
H. Peter Anvin
dd1de39ece BR 2028995: Missing MOVNTI m64, r64 
Fix MOVNTI with a 64-bit argument.
 2008-08-28 17:54:55 -07:00
H. Peter Anvin
962e30519c BR 2029829: Accept VIA XCRYPT instructions with or without REP 
Accept the VIA XCRYPT instructions either with or without a REP
prefix, as documented.

Add the missing XCRYPTCTR instruction.
 2008-08-28 17:47:16 -07:00
H. Peter Anvin
7b4dc622c6 BR 2039212: Handle indirect far jumps in 64-bit mode 
Handle indirect far jumps in 64-bit mode.  Default to 64 bit unless
overridden, for consistency with other jumps.
 2008-08-28 17:35:25 -07:00
H. Peter Anvin
04f54809d2 Add 256-bit AVX stores per the latest AVX spec. 
Add 256-bit forms of VMOVNTPD, VMOVNTPS, and VMOVNT[DQ]Q.
 2008-08-27 18:47:05 -07:00
H. Peter Anvin
06425512ae Add AVX forms of the AES instructions (new in the latest AVX spec) 
The AES instructions, too, have gotten VEX forms.
 2008-08-27 18:42:26 -07:00
H. Peter Anvin
51e403152a BR 2067820: add the MOVSXD instruction 
The official mnemonic for 32-to-64-bit sign extension is MOVSXD for
some idiotic reason.  Add support for it while continue to recognize
MOVSX for this as an alias.

Signed-off-by: H. Peter Anvin <hpa@zytor.com>
 2008-08-24 18:12:20 -07:00
H. Peter Anvin
2a09b3bf11 BR 2030823: Problem with the 256-bit FMA instructions 
Fix the 256-bit FMA instructions per bug report.
 2008-08-13 16:25:08 -07:00
H. Peter Anvin
38c6b44909 BR 2043111: Typo in insns.dat: VCMPFT_OQPD VCMPFT_OQPS 
Fix typo
 2008-08-13 16:18:23 -07:00
H. Peter Anvin
ecf8c3e382 BR 2025977: Handle SLDT with a 64-bit register operand 
Handle SLDT with a 64-bit register operand.  Don't generate a REX.W
prefix in the assembler, since zero-extending is just fine, but do
support it in the disassembler.
 2008-07-30 17:28:05 -07:00
H. Peter Anvin
bb266eaa4b BR 2023036: MOV reg32,dreg and vice versa are NOLONG 
MOV reg32,dreg and MOV dreg,reg32 are NOLONG; in 64-bit mode we always
move to/from reg64.
 2008-07-20 14:59:18 -07:00
H. Peter Anvin
96a6954db4 BR 2017453: indirect jumps in 64-bit mode are implicitly 64 bits 
Indirect jumps in 64-bit mode implicitly have 64-bit operand size.
Fix this; the disassembly is still unnecessarily ugly, however.
 2008-07-13 15:21:01 -07:00
Charles Crayne
a8ef7ab51d Fix Bugs item (LTR in long mode) 
LTR is valid in long (64-bit) mode, but still uses
16-bit operand, so remove NOLONG restriction.
 2008-07-13 12:52:02 -07:00
H. Peter Anvin
f89d681805 AES instructions are WESTMERE, not NEHALEM 
Still need to make this crap saner...
 2008-06-27 11:41:59 -07:00
H. Peter Anvin
358c97d21f The XSAVE group are SSE-spefix-sensitive 
The XSAVE group are SSE-prefix-sensitive (null prefix), and therefore
take the \360 flag.
 2008-06-05 16:23:35 -07:00
H. Peter Anvin
92c4704ddb insns.dat: whitespace cleanup 2008-05-27 14:22:19 -07:00
H. Peter Anvin
fd507e7a79 Fix double 66 prefixes on INVEPT/INVVPID (BR 1956955) 
Fix double 66 prefixes on INVEPT/INVVPID in 16-bit mode, per BR
1956955.
 2008-05-27 14:20:21 -07:00
H. Peter Anvin
62449a6ce0 VCVTPD2PS, VCVTPD2DQ, VCVTTPD2DQ mem need explicit op size (BR 1974170) 
BR 1974170: VCVTPD2PS, VCVTPD2DQ, VCVTTPD2DQ with a memory operand are
ambiguous without a specific operand size, so force one to be added.

Split the instruction pattern due to our current clunky handling of
MMX/XMM/YMM registers together with sizes.  Fix in the future, please!
 2008-05-26 22:48:51 -07:00
H. Peter Anvin
4a49b6770f Fix parameters to VCVTPD2DQ (BR 1974159) 2008-05-26 22:42:02 -07:00
H. Peter Anvin
216fea010d Fix mnemnonics for SSE5 PCOMU instructions 2008-05-25 09:25:47 -07:00
H. Peter Anvin
8cb2ae916b Fix mnemonics for VTESTP[SD] (BR 1971570) 
Incorrectly entered as VPTEST* due to illogical placement in the manual.
 2008-05-24 22:15:56 -07:00
H. Peter Anvin
7aacbeb537 Fix the VPSHUF*W instructions (BR 1971567) 
The VPSHUF*W instructions had both wrong mnemonics and opcodes.
 2008-05-24 22:13:33 -07:00
H. Peter Anvin
05430f64b5 Fix typo in VPCMPESTRM instruction (BR 1971565) 
The VPCMPESTRM instruction was typoed.
 2008-05-24 22:11:44 -07:00
H. Peter Anvin
ee71120a63 Add VCVTSI2SS (BR 1971564) 
The VCVTSI2SS instruction was missing.
 2008-05-24 22:09:51 -07:00
H. Peter Anvin
f2c10aee70 Fix immediate for PCLMULHQ* instructions (BR 1971555) 
The immediate for the PCLMULHQ* instructions was wrong.
 2008-05-24 22:07:03 -07:00
H. Peter Anvin
89031ff5d2 Remove imm from specific versions of VCMPxx 
For the versions of VCMPxx which already embed their condition code,
we do not want an extra immediate argument.

Todo: fix bytecode compiler to complain more about these.
 2008-05-24 22:04:23 -07:00
H. Peter Anvin
d0da1c7202 Add VLDQQU as an alias for 256-bit VLDDQU (BR 1971539) 
Accept VLDQQU as an alias for VLDDQU when used with 256-bit values.
 2008-05-24 21:58:59 -07:00
H. Peter Anvin
6c8042c0eb VFMSUBADDP[SD], not VFMADDSUBS[SD] (BR 1971573) 
There are VFMSUBADDP instructions, but there are no VFMADDSUBS
instructions.
 2008-05-24 21:54:09 -07:00
H. Peter Anvin
dd84acedcc AVX FMA: Instruction table for the AVX FMA instructions 
This adds the AVX FMA instructions to the instruction table, which
should complete the AVX work.
 2008-05-23 17:46:08 -07:00
H. Peter Anvin
55ca614e62 AVX: Remaining AVX instructions (still need FMA) 
Implement the remaining set of AVX instructions
 2008-05-23 17:27:15 -07:00
H. Peter Anvin
2ee4c67e7d AVX instruction table through "P" 
AVX instruction table through the letter P in the manual
 2008-05-23 17:03:30 -07:00
H. Peter Anvin
7c71949931 AVX: instruction table up to PE 
Complete the instruction table up to and including PE (document
319433-002, start next on page 5-330).
 2008-05-21 23:21:57 -07:00
H. Peter Anvin
283ba9103e AVX: instruction table through M 
Implement the AVX instruction table through the letter M.
 2008-05-21 18:10:09 -07:00
H. Peter Anvin
982a7bd3dd Implement aliases for specific SSE5 compare operations 
Implement aliases for specific SSE5 compare operations, per BR 1930630.
 2008-05-21 15:02:30 -07:00
H. Peter Anvin
eaf3d491ad insns.dat: reimplement SSE5 compares using the bytecode compiler 
Use the bytecode compiler for the SSE5 compare instructions.  While we
are at it, give it correct flags.
 2008-05-21 14:45:46 -07:00
H. Peter Anvin
eccd1acca9 Add the PCLMUL instructions (BR 1933742) 
Add the PCLMUL group instructions, from the AVX spec but not actually
AVX instructions.
 2008-05-21 14:28:42 -07:00
H. Peter Anvin
cf6682fb01 Add INVEPT and INVVPID (BR 1956955) 2008-05-21 14:17:33 -07:00
H. Peter Anvin
bce9da223f Add the MOVBE instructions (BR 1956954) 
Add the MOVBE instructions (load/store and swap)
 2008-05-21 14:03:56 -07:00
H. Peter Anvin
18c3ce2517 insns typo fix: SSE5 FNM* instructions misspelled 
The SSE5 FNM* instructions were misspelled as FMN*

(Bug 1930322)
 2008-05-21 08:45:17 -07:00
H. Peter Anvin
2b524d5e62 Merge branch 'master' of git+ssh://repo.or.cz/srv/git/nasm 2008-05-21 08:42:55 -07:00