H. Peter Anvin
0db11e236b
Handle "LOCK as REX.R" for MOV CRx; fix warning for invalid 64-bit regs
...
- MOV gpr,CRx or MOV CRx,gpr can access high control registers with a LOCK
prefix; handle that in both the assembler and disassembler.
- Get a saner error message when trying to access high resources in
non-64-bit mode.
2007-04-17 20:23:11 +00:00
Keith Kanios
fd626d6770
MEM_OFFSET Instructions Fixed.
2007-04-16 18:16:46 +00:00
Keith Kanios
56e3528b4a
Fixed long mode MEM_OFFS issue.
2007-04-16 14:05:01 +00:00
H. Peter Anvin
ed45f4c6f2
More \321 -> \324 for 64-bit instructions
...
The assembler doesn't seem to care, but for the disassembler, it's
vitally important that we get our operand-size hints correctly. We
probably need to audit insns.dat for this kinds of errors.
2007-04-16 05:26:29 +00:00
H. Peter Anvin
7cf03aff4f
More 64-bit ndisasm fixes.
...
In particular, now we should handle A0-A3 instructions.
2007-04-16 02:39:56 +00:00
H. Peter Anvin
b061d595fb
Fixes for 64-bit ndisasm.
...
This fixes some of the most glaring bugs in ndisasm 64-bit mode. We're
still getting redundant prefixes for unknown reason, however.
2007-04-16 02:02:06 +00:00
H. Peter Anvin
e2eb92d055
CR8 is not special in any way as far as the assembler is concerned.
...
CR8 is not special in any way as far as the assembler is concerned. It's
listed as having a special form in the Intel documentation, but that is
only because there are no other CRs which require a REX prefix.
MOV to CR8 is special in the sense that it's a non-serializing
instruction, but that's irrelevant to the assembler.
Furthermore, it's totally unclear how TRs should be handled in long mode;
there are no CPUs which uses TRs which also have long mode, so the easiest
is to simply mark those instructions NOLONG.
Finally, add PRIV to some privileged instructions.
2007-04-15 23:09:23 +00:00
Keith Kanios
b7a89544d0
General push for x86-64 support, dubbed 0.99.00.
2007-04-12 02:40:54 +00:00
Eric Christopher
aa348dec7d
Add VMX instructions.
2006-03-02 18:35:09 +00:00
H. Peter Anvin
cd342f0f7e
STR also has SMSW/SLDT-like semantics for operand size
2003-09-02 21:38:48 +00:00
H. Peter Anvin
539f81d517
SMSW and SLDT are implicitly 16 bits when accessing memory, but can set
...
the upper part of a 16-bit register if used with a 32-bit register
argument.
2003-08-27 21:25:44 +00:00
H. Peter Anvin
eea289f908
Add Cyrix XSTORE
2003-03-12 04:57:51 +00:00
H. Peter Anvin
10101f26bc
Add support for the new instructions in Prescott
2003-02-24 23:22:45 +00:00
Frank Kotler
761c5cc5d3
bugfixes to insns.dat pmovhps, pmovlps, sysexit
2003-02-04 17:13:49 +00:00
H. Peter Anvin
08a3377059
Fix bug 615409 (UNPCKHPD xmmreg,mem not vice versa)
2002-11-08 20:18:51 +00:00
Debbie Wiles
0fde2f574e
Removed unnecessary address size flags from register only versions of instructions
2002-06-07 07:12:49 +00:00
H. Peter Anvin
232badbbbc
This is the "megapatch":
...
a) Automatically generate dependencies for all Makefiles;
b) Move register definitions to a separate .dat file;
c) Add support for "unimplemented but there in theory" registers.
2002-06-06 02:41:20 +00:00
H. Peter Anvin
3ab8de6a14
Add the JMPE instruction.
2002-05-28 01:25:06 +00:00
H. Peter Anvin
3ba467795a
Deal with another case of address/operand size confusion, BR 560873
2002-05-27 23:19:35 +00:00
Debbie Wiles
d71fe8ec11
*** empty log message ***
2002-05-10 23:07:02 +00:00
Debbie Wiles
1c7da40456
*** empty log message ***
2002-05-09 21:23:55 +00:00
H. Peter Anvin
10eb0c3e47
Processor level fixes from John Coffman
2002-05-09 20:55:50 +00:00
H. Peter Anvin
8ac364139a
NASM 0.98.30
2002-04-30 21:09:12 +00:00
H. Peter Anvin
9a633fa3b9
NASM 0.98.25alt
2002-04-30 21:08:11 +00:00
H. Peter Anvin
9f39464e5b
NASM 0.98.25
2002-04-30 21:07:51 +00:00
H. Peter Anvin
dce1e2f795
NASM 0.98.23
2002-04-30 21:06:37 +00:00
H. Peter Anvin
09f6acbb75
NASM 0.98.21
2002-04-30 21:05:55 +00:00
H. Peter Anvin
788e6c10e1
NASM 0.98.12
2002-04-30 21:02:01 +00:00
H. Peter Anvin
4cf1748e68
NASM 0.98.11
2002-04-30 21:01:38 +00:00
H. Peter Anvin
734b188090
NASM 0.98.09
2002-04-30 21:01:08 +00:00
H. Peter Anvin
1cd0e2d5bf
NASM 0.98.08
2002-04-30 21:00:33 +00:00
H. Peter Anvin
af535c16cf
NASM 0.98.03
2002-04-30 20:59:21 +00:00
H. Peter Anvin
41bf8002b2
NASM 0.98
2002-04-30 20:58:18 +00:00
H. Peter Anvin
ef7468f4ec
NASM 0.98p7
2002-04-30 20:57:59 +00:00
H. Peter Anvin
620515ab4e
NASM 0.98p6
2002-04-30 20:57:38 +00:00
H. Peter Anvin
f443eb3d0d
NASM 0.98p3.6
2002-04-30 20:57:02 +00:00
H. Peter Anvin
4836e3374e
NASM 0.98p3.5
2002-04-30 20:56:43 +00:00
H. Peter Anvin
b64535fd4e
NASM 0.98p3.3
2002-04-30 20:55:37 +00:00
H. Peter Anvin
ce14ce6fc4
NASM 0.98p3.2
2002-04-30 20:54:58 +00:00
H. Peter Anvin
900fa5b26b
NASM 0.98p3-hpa
2002-04-30 20:54:13 +00:00
H. Peter Anvin
eba20a73f2
NASM 0.98p3
2002-04-30 20:53:55 +00:00
H. Peter Anvin
76690a12ad
NASM 0.96
2002-04-30 20:52:49 +00:00
H. Peter Anvin
d7ed89eac9
NASM 0.94
2002-04-30 20:52:08 +00:00
H. Peter Anvin
ea8382740d
NASM 0.93
2002-04-30 20:51:53 +00:00
H. Peter Anvin
ea6e34db64
NASM 0.91
2002-04-30 20:51:32 +00:00
