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94a7645ec9
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295 Commits

Author SHA1 Message Date
Cyrill Gorcunov
94a7645ec9 insns.dat: Add hle flag for INC instruction 
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
 2012-02-25 23:51:45 +04:00
Cyrill Gorcunov
47fe219004 insns.dat: Add hle flag for DEC instruction 
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
 2012-02-25 23:51:44 +04:00
Cyrill Gorcunov
e520db7f49 insns.dat: Add hle flag for CMPXCHG16B instruction 
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
 2012-02-25 23:51:44 +04:00
Cyrill Gorcunov
aea6453c8b insns.dat: Add hle flag for CMPXCHG8B instruction 
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
 2012-02-25 23:51:44 +04:00
Cyrill Gorcunov
08a291d0da insns.dat: Add hle flag for CMPXCHG instruction 
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
 2012-02-25 23:51:44 +04:00
Cyrill Gorcunov
6763e28b68 insns.dat: Add hle flag for BTS instruction 
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
 2012-02-25 23:51:44 +04:00
Cyrill Gorcunov
e7a9ec3676 insns.dat: Add hle flag for BTR instruction 
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
 2012-02-25 23:51:44 +04:00
Cyrill Gorcunov
75150e2df4 insns.dat: Add hle flag for BTC instruction 
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
 2012-02-25 23:51:44 +04:00
Cyrill Gorcunov
e844844321 insns.dat: Add hle flag for AND instruction 
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
 2012-02-25 23:51:44 +04:00
Cyrill Gorcunov
e30aef38da insns.dat: Add hle flag for ADC instruction 
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
 2012-02-25 23:51:44 +04:00
Cyrill Gorcunov
dec6037fa7 insns.dat: Add hle flag for ADD instruction 
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
 2012-02-25 23:51:44 +04:00
H. Peter Anvin
755f5214b7 Remove all remaining explicit bytecodes from insns.dat 
Get rid of the last vestiges of the explicit byte codes in insns.dat.
The only files that now depend on actual byte code numbers are
insns.pl, assemble.c and disasm.c.

Signed-off-by: H. Peter Anvin <hpa@zytor.com>
 2012-02-25 11:41:34 -08:00
H. Peter Anvin
44454be952 insns: create a symbolic "wait" token for the \341 byte code 
Create a symbolic name "wait" for the \341 byte code, so we don't have
to open-code it.

Signed-off-by: H. Peter Anvin <hpa@zytor.com>
 2012-02-10 11:11:08 -08:00
H. Peter Anvin
b17da041cb insns: fix IMUL patterns to get rid of open-coded \100 bytecodes 
There already is a standard encoding for "use this operand in multiple
slots"; no need to open-code it.

Signed-off-by: H. Peter Anvin <hpa@zytor.com>
 2012-02-10 11:08:09 -08:00
H. Peter Anvin
e2b262beae insns: correct the TSX opcodes 
All except XTEST are RTM, not HLE; XBEGIN is like a JMP or CALL.

Signed-off-by: H. Peter Anvin <hpa@zytor.com>
 2012-02-09 16:24:32 -08:00
Cyrill Gorcunov
d0f773230e insns: Add AVX2 transactional synchronization extensions 
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
 2012-02-09 16:20:57 -08:00
H. Peter Anvin
9d93f4b396 insns: replace open-coded \322 opcode with odf (operand default) 
Create a mnemonic for the open-coded opcode \322.

Signed-off-by: H. Peter Anvin <hpa@zytor.com>
 2012-02-09 16:20:21 -08:00
H. Peter Anvin
a56b70436e BR 3463230: Add VMFUNC instruction 
Add VMFUNC instruction from the Intel SDM version 041.

Signed-off-by: H. Peter Anvin <hpa@zytor.com>
 2011-12-21 08:26:48 -08:00
Cyrill Gorcunov
4b6f98bdd6 insns: Fix up sizes for MOVSD and VMOVSS instructions 
Reported-by: Jasper Neumann <jasper.neumann@scpsoftware.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
 2011-12-17 12:09:02 +04:00
Cyrill Gorcunov
d279fbbd80 BR3392199: Revert "insns: Add MOVD as aliases to MOVQ for compatibility with AMD" 
This reverts commit 70712c0df6.

Conflicts:

	insns.dat

Our instructions matcher fuzzy logic fails to handle it at moment.

Reported-by: KO Myung-Hun <komh@chollian.net>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
 2011-11-20 17:16:43 +04:00
Cyrill Gorcunov
d96a329a78 insns.dat: Fix VPCMPEQQ template 
http://bugzilla.nasm.us/show_bug.cgi?id=3392197

Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
 2011-11-15 01:21:48 +04:00
Cyrill Gorcunov
013da29782 BR3392195: insns: Drop MMX flag from MOVD 
Typo in specification.

Reported-by: Jasper Neumann <sirrida@web.de>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
 2011-11-12 09:47:27 +04:00
Cyrill Gorcunov
eb786412f6 insns: Fix typos for vcmpeq aliases 
The patch came from herumi@nifty.com

Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
 2011-11-11 13:04:20 +04:00
Cyrill Gorcunov
70712c0df6 insns: Add MOVD as aliases to MOVQ for compatibility with AMD 
AMD has MOVD for both 32bit and 64bit GPRs so in a sake of
compatibility bring them into insns.dat.

Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
 2011-10-02 10:53:37 +04:00
Cyrill Gorcunov
9022212ba9 insns.dat: Fixup VGATHERx instructions 
As being spotted by nasm64developer the memory
operands size is incorrect. Fix it.

Reported-by: nasm64developer
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
 2011-08-31 01:34:43 +04:00
Cyrill Gorcunov
db3f71bc67 insns, avx2: A couple of upper-case to lower-case conversion 
Just to be solid in style

Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
 2011-08-23 00:35:32 +04:00
Cyrill Gorcunov
b16bb628ce insns, avx2: A typo in VPERMPD 
The second VPERMD should be VPERMPD actually.

Thanks to nasm64developer for gas test file provided
which allowed to reveal this issue.

Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
 2011-08-23 00:30:28 +04:00
Cyrill Gorcunov
4c78ab3474 BR3385573: Some AVX2 instructions fixups 
A few instruction templates for AVX2 set were wrong.

Reported-by: Agner Fog
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
 2011-08-22 01:38:40 +04:00
Cyrill Gorcunov
c7970eb4a3 insns: Change VPERMPQ to VPERMQ 
Was a typo

Reported-by: Agner Fog
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
 2011-08-03 22:16:29 +04:00
Anonymous
e837a7b4ea Implement insns.dat in human readable form 
I converted almost all instructions in insns.dat (version
 7a6f978698) to the more
 readable format that insns.pl has supported for years.

 I also made some changes to insns.pl. You can verify that the
 new insns.dat and insns.pl produce byte-identical output to
 the old insns.dat and insns.pl, so I think that this change
 is safe to check in, even though it is a large change to
 insns.dat.

The changes to insns.pl are:

 * fixed a bug: ib,u was not recognized
 * added support for a second immediate argument called "j" for
   instructions like ENTER imm,imm
 * added a "+r" syntax for \10..\13

[gorcunov: insns files remains the same, great job anonymous!]

Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
 2011-07-20 21:47:53 +04:00
Cyrill Gorcunov
f757614d48 insns: A final pile of AVX2 instructions 
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
 2011-07-20 01:16:11 +04:00
Cyrill Gorcunov
7a0c878ffb insns: A few additional AVX2 templates 
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
 2011-07-19 17:01:35 +04:00
Cyrill Gorcunov
7a6f978698 insns: One more small snippet of AVX2 
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
 2011-07-18 01:15:25 +04:00
Cyrill Gorcunov
55a12fddc7 insns: One more slab of AVX2 instructions 
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
 2011-07-18 00:57:35 +04:00
Cyrill Gorcunov
89a38dac36 insns: Add a slab of AVX2 instructions 
Not all are covered yet, but still a step
forward I think.

Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
 2011-07-17 23:20:00 +04:00
Cyrill Gorcunov
80c7efbad4 insns.dat: Move exsiting AVX2 insns to a separate section 
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
 2011-07-17 20:24:16 +04:00
H. Peter Anvin
9f0dcfc724 A few more AVX2 spec instructions 
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
 2011-07-08 16:08:34 -07:00
H. Peter Anvin
573aea590e insns.dat: Clean up and fix the BMI instruction patterns 
Clean up the formatting of the BMI instruction patterns, and fix:

a) X64,FUTURE is wrong - it needs to be LONG,FUTURE
b) Fix the BLSI, BLSMSK, BLSR instruction patterns
c) Use a bracket pattern for TZCNT

Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
 2011-07-07 15:29:14 -07:00
Jasper Neuman
5cc798c612 insns: Fix up RORX template 
Missed 64 bit case.

Signed-off-by: Jasper Neuman <jasper.neumann@web.de>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
 2011-07-07 11:02:11 +04:00
Jasper Neuman
c1610e6abe insns.dat: Add some BMI1 and BMI2 instructions 
Signed-off-by: Jasper Neuman <jasper.neumann@web.de>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
 2011-07-07 01:08:51 +04:00
Cyrill Gorcunov
8a61142504 insns: Mark AVX2 instructions as FUTURE 
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
 2011-06-29 23:35:53 +04:00
Cyrill Gorcunov
9880ea4572 insns: A few more AVX2 instructions 
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
 2011-06-26 10:45:10 +04:00
Cyrill Gorcunov
92569ece7b insns: Add VPERMD instruction 
We somehow missed it.

Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
 2011-06-26 02:07:22 +04:00
Cyrill Gorcunov
ed33be2519 insns: Allow MOVD xmmreg,rm32 to be used in 32bit mode 
Reported-by: Keith Kanios <keith@kanios.net>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
 2011-06-26 01:49:29 +04:00
Cyrill Gorcunov
80594e79ed insns: Mark VGATHERDPD as AVX2 instructions 
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
 2011-06-25 12:01:52 +04:00
H. Peter Anvin
95adeabff5 Implement the VGATHERP instruction 
As an initial test of the VSIB handling, implement the VGATHERP
instruction.

Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
 2011-06-22 18:20:28 -07:00
Cyrill Gorcunov
a09fe1ebfb Merge branch 'nasm-2.09.xx' 
Conflicts:
	doc/changes.src
	version

Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
 2011-03-12 22:35:42 +03:00
Cyrill Gorcunov
b61564400a BR3189064: Fixes for VEXTRACTF128, VMASKMOVPS 
These AVX instructions should use YMM register

Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
 2011-03-07 12:40:22 +03:00
Cyrill Gorcunov
4e45e61055 Merge branch 'nasm-2.09.xx' 2011-02-23 00:49:41 +03:00
Cyrill Gorcunov
79abe7a731 insns: VLDQQU is back 
As HPA explained
|
| w.r.t. the -QQ- instruction forms... when we did
| the initial AVX implementation we decided that
| using -DQ- (double quadword) for 256-bit instructions
| was a bit messy, so we decided to accept both -DQ-
| (being official) and -QQ-
|

So move VLDQQU back and place it before VLDDQU so disassembler
match it first.

Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
 2011-02-23 00:41:43 +03:00