mirror/nasm
2
0
Fork 0
mirror of https://github.com/netwide-assembler/nasm.git synced 2024-12-27 09:29:06 +08:00
Code Issues Packages Projects Releases Wiki Activity
1,315 Commits 60 Branches 348 Tags 23 MiB
932de6c252
Commit Graph

153 Commits

Author SHA1 Message Date
H. Peter Anvin
ecf8c3e382 BR 2025977: Handle SLDT with a 64-bit register operand 
Handle SLDT with a 64-bit register operand.  Don't generate a REX.W
prefix in the assembler, since zero-extending is just fine, but do
support it in the disassembler.
 2008-07-30 17:28:05 -07:00
H. Peter Anvin
bb266eaa4b BR 2023036: MOV reg32,dreg and vice versa are NOLONG 
MOV reg32,dreg and MOV dreg,reg32 are NOLONG; in 64-bit mode we always
move to/from reg64.
 2008-07-20 14:59:18 -07:00
H. Peter Anvin
96a6954db4 BR 2017453: indirect jumps in 64-bit mode are implicitly 64 bits 
Indirect jumps in 64-bit mode implicitly have 64-bit operand size.
Fix this; the disassembly is still unnecessarily ugly, however.
 2008-07-13 15:21:01 -07:00
Charles Crayne
a8ef7ab51d Fix Bugs item #2017455 (LTR in long mode) 
LTR is valid in long (64-bit) mode, but still uses
16-bit operand, so remove NOLONG restriction.
 2008-07-13 12:52:02 -07:00
H. Peter Anvin
f89d681805 AES instructions are WESTMERE, not NEHALEM 
Still need to make this crap saner...
 2008-06-27 11:41:59 -07:00
H. Peter Anvin
358c97d21f The XSAVE group are SSE-spefix-sensitive 
The XSAVE group are SSE-prefix-sensitive (null prefix), and therefore
take the \360 flag.
 2008-06-05 16:23:35 -07:00
H. Peter Anvin
92c4704ddb insns.dat: whitespace cleanup 2008-05-27 14:22:19 -07:00
H. Peter Anvin
fd507e7a79 Fix double 66 prefixes on INVEPT/INVVPID (BR 1956955) 
Fix double 66 prefixes on INVEPT/INVVPID in 16-bit mode, per BR
1956955.
 2008-05-27 14:20:21 -07:00
H. Peter Anvin
62449a6ce0 VCVTPD2PS, VCVTPD2DQ, VCVTTPD2DQ mem need explicit op size (BR 1974170) 
BR 1974170: VCVTPD2PS, VCVTPD2DQ, VCVTTPD2DQ with a memory operand are
ambiguous without a specific operand size, so force one to be added.

Split the instruction pattern due to our current clunky handling of
MMX/XMM/YMM registers together with sizes.  Fix in the future, please!
 2008-05-26 22:48:51 -07:00
H. Peter Anvin
4a49b6770f Fix parameters to VCVTPD2DQ (BR 1974159) 2008-05-26 22:42:02 -07:00
H. Peter Anvin
216fea010d Fix mnemnonics for SSE5 PCOMU instructions 2008-05-25 09:25:47 -07:00
H. Peter Anvin
8cb2ae916b Fix mnemonics for VTESTP[SD] (BR 1971570) 
Incorrectly entered as VPTEST* due to illogical placement in the manual.
 2008-05-24 22:15:56 -07:00
H. Peter Anvin
7aacbeb537 Fix the VPSHUF*W instructions (BR 1971567) 
The VPSHUF*W instructions had both wrong mnemonics and opcodes.
 2008-05-24 22:13:33 -07:00
H. Peter Anvin
05430f64b5 Fix typo in VPCMPESTRM instruction (BR 1971565) 
The VPCMPESTRM instruction was typoed.
 2008-05-24 22:11:44 -07:00
H. Peter Anvin
ee71120a63 Add VCVTSI2SS (BR 1971564) 
The VCVTSI2SS instruction was missing.
 2008-05-24 22:09:51 -07:00
H. Peter Anvin
f2c10aee70 Fix immediate for PCLMULHQ* instructions (BR 1971555) 
The immediate for the PCLMULHQ* instructions was wrong.
 2008-05-24 22:07:03 -07:00
H. Peter Anvin
89031ff5d2 Remove imm from specific versions of VCMPxx 
For the versions of VCMPxx which already embed their condition code,
we do not want an extra immediate argument.

Todo: fix bytecode compiler to complain more about these.
 2008-05-24 22:04:23 -07:00
H. Peter Anvin
d0da1c7202 Add VLDQQU as an alias for 256-bit VLDDQU (BR 1971539) 
Accept VLDQQU as an alias for VLDDQU when used with 256-bit values.
 2008-05-24 21:58:59 -07:00
H. Peter Anvin
6c8042c0eb VFMSUBADDP[SD], not VFMADDSUBS[SD] (BR 1971573) 
There are VFMSUBADDP instructions, but there are no VFMADDSUBS
instructions.
 2008-05-24 21:54:09 -07:00
H. Peter Anvin
dd84acedcc AVX FMA: Instruction table for the AVX FMA instructions 
This adds the AVX FMA instructions to the instruction table, which
should complete the AVX work.
 2008-05-23 17:46:08 -07:00
H. Peter Anvin
55ca614e62 AVX: Remaining AVX instructions (still need FMA) 
Implement the remaining set of AVX instructions
 2008-05-23 17:27:15 -07:00
H. Peter Anvin
2ee4c67e7d AVX instruction table through "P" 
AVX instruction table through the letter P in the manual
 2008-05-23 17:03:30 -07:00
H. Peter Anvin
7c71949931 AVX: instruction table up to PE 
Complete the instruction table up to and including PE (document
319433-002, start next on page 5-330).
 2008-05-21 23:21:57 -07:00
H. Peter Anvin
283ba9103e AVX: instruction table through M 
Implement the AVX instruction table through the letter M.
 2008-05-21 18:10:09 -07:00
H. Peter Anvin
982a7bd3dd Implement aliases for specific SSE5 compare operations 
Implement aliases for specific SSE5 compare operations, per BR 1930630.
 2008-05-21 15:02:30 -07:00
H. Peter Anvin
eaf3d491ad insns.dat: reimplement SSE5 compares using the bytecode compiler 
Use the bytecode compiler for the SSE5 compare instructions.  While we
are at it, give it correct flags.
 2008-05-21 14:45:46 -07:00
H. Peter Anvin
eccd1acca9 Add the PCLMUL instructions (BR 1933742) 
Add the PCLMUL group instructions, from the AVX spec but not actually
AVX instructions.
 2008-05-21 14:28:42 -07:00
H. Peter Anvin
cf6682fb01 Add INVEPT and INVVPID (BR 1956955) 2008-05-21 14:17:33 -07:00
H. Peter Anvin
bce9da223f Add the MOVBE instructions (BR 1956954) 
Add the MOVBE instructions (load/store and swap)
 2008-05-21 14:03:56 -07:00
H. Peter Anvin
18c3ce2517 insns typo fix: SSE5 FNM* instructions misspelled 
The SSE5 FNM* instructions were misspelled as FMN*

(Bug 1930322)
 2008-05-21 08:45:17 -07:00
H. Peter Anvin
2b524d5e62 Merge branch 'master' of git+ssh://repo.or.cz/srv/git/nasm 2008-05-21 08:42:55 -07:00
H. Peter Anvin
be5133cb13 UDx instructions are 186+, not 286+ 
The UDx instructions are valid as far back as the #UD trap, which is
the 186, not the 286.
 2008-05-21 08:41:58 -07:00
H. Peter Anvin
c882715a8e AVX instructions up to VMINSS 2008-05-20 23:28:46 -07:00
H. Peter Anvin
330cbd1c90 A few more AVX instructions (up to VLDMXCSR) 
More AVX instructions, up to VLDMXCSR
 2008-05-20 23:16:27 -07:00
H. Peter Anvin
2d31ec106a Officially specify - as the symbol for an implicit operand 
Use - to denote that an operand is implicit (not encoded).  This
*better* be a fixed operand!
 2008-05-20 18:21:11 -07:00
H. Peter Anvin
9681ef4144 AVX: implement all the convert instructions... 
Make our way through the AVX instructions: conversions.
This is all I have time for now... hopefully this can service as a
generous source of examples.
 2008-05-20 18:14:30 -07:00
H. Peter Anvin
4ae88e1a83 Accept the gas mnemonics "ud2a" and "ud2b"; fix ud0 
Accept the gas mnemonics "ud2a" and "ud2b" for the instructions we
call ud2 and ud1 respectively, and Intel call ud2 and undocumented :)

Also, 0F FF is ud0 regardless of prefixes, at least as far as we know.
 2008-05-20 17:14:17 -07:00
H. Peter Anvin
f99359c03a Finish the VCMP series... 2008-05-20 16:59:17 -07:00
H. Peter Anvin
e6d0eb4d68 More AVX instructions 
Add additional AVX instructions to the list.
 2008-05-20 16:48:34 -07:00
H. Peter Anvin
73252a92ae PTEST is SSE4.1; although AMD says it's SSE5. 
Fix this when we have proper support for feature sets, or forget about
the concept entirely.
 2008-05-20 13:07:09 -07:00
H. Peter Anvin
dfb918047b Add DY, YWORD, and the SY instruction flag 
Add the DY instruction, YWORD keyword, and an SY marker for
instruction sizes.  Add a few more AVX sample instructions.
 2008-05-20 11:43:53 -07:00
H. Peter Anvin
d82dd4f1a3 insns.dat: no subheader for "must be last" 2008-05-20 11:05:59 -07:00
H. Peter Anvin
1e5203872d insns.dat: make even wider to make space for AVX 
The AVX instructions take more space, so add a few tab stops across
the entire file.
 2008-05-20 11:04:26 -07:00
H. Peter Anvin
8597e6900c insns.dat: use compiler-generated bytecodes for AVX 
Use compiler-generated bytecodes for the AVX instruction demos.  This
should make it a lot easier for other people (HINT, HINT) to add the
instruction table.
 2008-05-20 11:01:28 -07:00
H. Peter Anvin
2812ff5181 Use the \360..\363 annotations for SSE prefixes 2008-05-20 10:21:57 -07:00
H. Peter Anvin
aaa088fbf3 Remove special hacks to avoid zero bytecodes 
We can now have zero bytecodes with impunity, so remove any special
hacks we had to avoid zeroes in the bytecode.
 2008-05-12 11:13:41 -07:00
H. Peter Anvin
e303936391 Fix encoding of VPERMIL2PS instructions 2008-05-06 20:06:14 -07:00
H. Peter Anvin
42a8caecb5 Sandy Bridge, not Sandy Banks; add Westmere 2008-05-06 19:54:28 -07:00
H. Peter Anvin
d85d250fa2 First cut at AVX machinery. 
First cut at AVX machinery support.  The only instruction implemented
is VPERMIL2PS, and it's probably buggy.  I'm checking this in with the
hope that other people can start helping out with (a) testing this,
and (b) adding instructions.

NDISASM support is not there yet.
 2008-05-04 17:53:31 -07:00
H. Peter Anvin
32cd4c2a62 Correctly identify SBYTE in the optimizer 
Correctly identify SBYTE in the optimizer, *HOWEVER*, this change will
cause nuisance warnings to be issued; that will have to be fixed.
 2008-04-04 13:34:53 -07:00