Add the MOVBE CPUID flag, add helper patterns for 16-bit BSWAP
emulation. Unfortunately using ROL/ROR for registers other than the
ones for which XCHG can work clobbers the flags.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
More work on cleaning up instruction patterns, fixing matchig corner
cases, and tidying up the organization of insns.dat.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
More matching and macrofication work.
Improve some error and warning messages.
Update some travis tests for better messages and added optimizations.
Fix duplicated warning messages for the same out-of-range value
problem.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Tag pseudo-instructions explicitly and don't set any CPU level flag
for those.
Change insnsa.c to have (length, pointer) rather than using an ever
increasing in size sentinel at the end of each table. This also means
that empty tables (Dx, INCBIN) can be omitted entirely.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Add more instruction macros and fix problems. Adjust some matching
problems.
Remove all FUTURE tags from the instruction list, and add a bunch of
new CPUID tags. Hopefully a small step toward actually getting CPU
feature selection working properly in the future.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
"nw" now means: 64-bit operand size is the default, o32 is not
permitted in 64-bit mode.
"osz" means: instruction size determined by prefixes, otherwise the
mode default.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Don't break a string on a quoted comma, for obvious reasons. Allow an
op argument to be quoted in general.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Add more improvements to the macro features. Now it is possible to
generate the -X versions of the shift instructions as part of the
macroization, which is highly desirable in order to allow them to be
generated using {nf} syntax.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Work more on the macro facility. Add the ability to kill an
instruction pattern based on expansion (if the token KILL appears.)
Add APX patterns to the arithmetic macro and macroize the shift and
rotate patterns.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Make the macro facility in preinsns.pl more general, and relying less
on evaluating Perl constructs. This *might* be practical with some
more work, to move to a data file, but wait until we have a better
idea of the needs.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
The former addflags.pl now does more general preprocessing, so rename
it from addflags.pl to preinsns.pl.
To generate the instruction list in the documentation, use the
post-preprocessed insns.xda file.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
This is a WIP checkpoint; not all tests pass yet.
More matching changes, and hopefully something much closer to what
really is desired now. The number of required patterns is now much
smaller.
However, a lot of *changes* are needed to the patterns.
Since some patterns are repeated all over the place, clean up the
x86/addflags.pl script and make it able to generate macro-based
common patterns; first use being the patterns for the "basic 8"
arithmetic patterns.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Work through a number of changes toward making matching a lot saner,
both to reduce the number of patterns to generate for APX but also to
make a number of code patterns simpler.
This replaces a fair number of byte codes.
Improve a number of error messages, especially related to overflows.
Move process_insn() from nasm.c to assemble.c, as it really is the
primary entry point to the assembler module.
Reorder some prefixes. In particular, F2/F3 override 66 when used as a
mandatory prefix, so it makes more sense for them to be closer to the
opcode.
Move a lot more information into struct insn. It is better to have it
in one place; memory consumption is not an issue because struct insn
is transient information.
Get rid of "optimization levels" and replace it with a mask of
flags. That was already halfway done; complete the job.
Replace seg:offset in struct out_data with a struct location. It would
be better to extend this to more places, too.
The ARx and SMx flags are now explicit bitmasks, instead of having a
couple of hard-coded ranges.
Add __func__ to assert or panic messages.
Because of prefix and message changes, a number of travis tests had to
be audited and updated.
Fix a number of instruction patterns which had .128 when they ought to
be .lig. This is no longer a minor issue with the disassembler: for
AVX10, the pattern vector length determines how SAE/RC are encoded,
and there is no valid 128-bit encoding. However, with .lig the 512-bit
encoding can be used.
Separate "o64nw" into two pieces: opsize 64 and "nw" = "REX.w not necessary". The
latter can be included in non-64-bit patterns. "o64" still set REX.W
since that is still the common thing.
New "osz" bytecode: emit an OSP *or* REX.W depending on the current
mode and operand size. Useful for special cases like "nop" where "o64
nop" probably wants to be encoded as "48 90".
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Don't do an out-of-range check for the operands, even
temporarily. Setting the operand pointer to NULL will help catch
errors when accessing non-operands, too.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Add MOVSX[D] -> CBW/CWDE/CDQE optimization patterns when the suitable
form of the AX register are referenced.
Add MOVZX reg64,rm32 pattern which converts to a 32-bit MOV.
Add MOVZXD reg64,rm32 alias pattern for consistency.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
.dat versus .dax is annoying for tab completion, change the extension
for the preprocessed insns.dat to .xda.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
For the instructions ending in -x because they don't modify the flags,
also accept {nf}. Add 2-operand relaxed versions like for most other
instructions, too.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Make sure to get the right type for the disassembly tables. This is
now a fixed-depth tree, so there is no reason to use union types or
anything along those lines.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Change the generation of tables for disassembly to be map-based. This
also makes the code a bit more regular.
This is the first step at catching up with APX support in the
disassembler.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
These are mostly structured. Leave this as an explicit processing
step, at least until the correctness of these flags have been fully
verified; perhaps after that as well.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Merge a bunch of common code in the handling of modr/m
generation. Make the handing of compressed disp8 simpler and more
transparent by exporting a the shift factor for the compressed
immediate in ea_data. For the case of no compression, the shift factor
is simply 0; there is no need to distinguish "compressed" from
"uncompressed".
The tidied up version of the disp8 code is simple enough that it makes
more sense to inline it.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
The {nf} and {zu} prefixes (or suffixes) can be used on a number of
instructions without actually change the encodings (either they don't
touch the flags at all, or they write a 32- or 64-bit register
already.)
Make this a bit more flexible, by adding an FL instruction flag for
the instructions which actually touch the flags, and a ZU instruction
flag for the instructions which zero the upper half.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
For the instruction space that are explicitly excluded by REX2, add
NOAPX tags. This was done with an automated script.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Implement the JMPABS instruction, which can also be specified as JMP
ABS for consistency. Since ABS is already a keyword, this does not
pollute the namespace.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
