The "high 16" register class macros were actually incorrect, as they
simply aliased the corresponding whole set class. In oder to keep
someone from getting confused and making mistakes, remove them.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Since the multi-line macro preprocessor is modified to expand
grouped parameter with braces. The escape character is not needed
any more.
The testcase converter script is also modified not to generate '\'.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Multi-line macro uses curly braces for enclosing a parameter
containing comma(s). Passing curly braces as a part of a parameter
which is already enclosed with braces confuses the macro expander.
The number of braces in a group parameter is counted and any brace
in the outmost enclosing braces is treated as a part of parameter.
e.g.) mmacro {1,2,3}, {4,{5,6}}
mmacro gets 2 parameters of '1,2,3' and '4,{5,6}'
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
This reverts commit a800aed7b7.
As recommended by the community, braces inside a group parameter
of multi-line macro should be parsed without a need of a leading
escape character such as "\{ab,c\}".
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
As recommended by the community, a comma-separated decorators ({k1,z})
and nested braces ({{k1},{z}}) are dropped out. So only standard syntax
is supported from now.
This rework made source code neat and easy to maintain. Most of the codes
for handling corner cases are removed.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
For checking the availability of {evex} prefix, AVX512 iflag
has been used. But this is a flag for an instruction set
not for an encoding scheme. And there are some AVX512 instructions
encoded with VEX prefix.
So a new instruction flag (IF_EVEX) is added for the instructions
which are actually encoded with EVEX prefix.
This flag is automatically added by insns.pl, so no need to add manually
in insns.dat.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Since only EVEX supports all 32 vector registers encoding for now,
VEX/REX encoded instructions should not take high-16 registers as operands.
This filtering had been done using instruction flag so far, but
using the opflags makes more sense.
[XYZ]MMREG operands used for non-EVEX instructions are automatically
converted to [XYZ]MM_L16 in insns.pl
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Added the list of features added since 2.10 release.
Nasmdoc is also updated with those new features.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Only generate a signed relocation if the displacement size is less
than the address size. This matters when involving address size
overrides.
It is technically impossible to do this one perfectly, because it is
never really knowable if the displacement offset is used as a base or
an index.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Emit signed relocations where we know they are necessary. This is not
at all exhaustive; in particular we are missing this for a number of
8- and 16-bit cases, and probably others.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
In order for iflag_cmp() to return an ordering that makes sense, we
need to scan from the most significant word downward. That way the
bits with the higher index consistently are the more significant.
This fixes the disassembler vendor selection algorithm. While we are
doing that, make that dependency more explicit in the comments.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Double underscores are reserved for the implementation, i.e. the C
compiler and its libraries. NASM is an application and should not use
this namespace.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Avoid using C99 constructs when not necessary. Don't hardcode the
number of words when we can autodiscover them.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Multi-dependencies don't work as expected, especially not across Make
versions, this is why we don't use them and read the instructions list
multiple times.
iflag.h has a lot of static content, so factor out the static content.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
In commit 9bb987d8e0
we had to drop some flags due to flags type used
in nasm code.
Since now flags internal structure is reworked, we
can restore them back.
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
It been found that 64 bits for instruction flags is too small,
so instead we start using indirect addressing scheme to keep
instruction flags in bitvectors instead.
Using one bitvector per instruction template entry is wastefull
(especially if vector grow in future, at moment it's 128 bit length),
so we use indirect addressing, which is generated as follow
- read instruction flags from insns.dat
- flag sequence sorted and joined into one key string
- this key string become a hash index
- all hash entries are compacted into one array
- every instruction template uses array offset instead
of flags bitfield
Just for info, at moment we have 195 unique flags combination,
but since instruction template will use index as unsigned
integer, we can use a way more wider combination of flags
in future.
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
We've 'test' target in toplevel Makefile, lets be
complete and allow to generate "golden" tests from
toplevel as well.
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Reverted the redundant branch instruction patterns for bnd prefix.
And when a relaxed jmp instruction becomes a short (Jb) form,
bnd prefix is not needed because it does not initialize bnd registers.
So in that case, bnd prefix is silently dropped.
BND JMP foo -> drops bnd prefix
BND JMP short foo -> shows an explicit error
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Consolidated two separate but similar functions in nasm and ndisasm
into a commonly linked source code.
To encode and decode the compressed displacement (disp8*N) for EVEX,
N value should be derived using various conditions.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
When tuple type is indicated in the bytecode, disp8 is
treated as a compressed disp and gets calculated back to disp8*N.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Disassembler can translate EVEX prefix, count up to 32 vector registers
and recognize new ZMM / opmask registers.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
The broadcasting decorator {1to##} must describe exactly how many times
the memory element is repeated in order to clearly match the correct
instruction format.
For example,
vaddpd zmm30,zmm29,QWORD [rdx+0x3f8]{1to8} ; good
vaddpd zmm30,zmm29,QWORD [rdx+0x3f8]{1to16} ; fail qword * 16 = 1024b
vaddps zmm30,zmm29,DWORD [rcx]{1to16} ; good
vaddps zmm30,zmm29,DWORD [rcx]{1to8} ; fail dword * 8 = 256b
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Broadcasting operand size is different from the original
operand size because 32b or 64b element is repeated to form a vector.
So when matching a broadcasting operand, opsize should be treated
differently.
The broadcasting element size is specified in the decorator information.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Giving a correct printf format specifier supresses the warning message.
And a local pointer variable is initialized with NULL.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
As BND prefix validity check conflicts with jcc8 prefix,
IF_BND is added for the instruction templates which can have
bnd prefix for preserving the content of bound register.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
GAS uses *1 multiplier for explicitly marking an index register in mib operand.
e.g.) [rdx * 1 + 3] is equivalent to [3, rdx] in NASM's split EA format
So only for mib operands, this is encoded same as gas does.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
