AMD has MOVD for both 32bit and 64bit GPRs so in a sake of
compatibility bring them into insns.dat.
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
As being spotted by nasm64developer the memory
operands size is incorrect. Fix it.
Reported-by: nasm64developer
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
The second VPERMD should be VPERMPD actually.
Thanks to nasm64developer for gas test file provided
which allowed to reveal this issue.
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
I converted almost all instructions in insns.dat (version
7a6f978698) to the more
readable format that insns.pl has supported for years.
I also made some changes to insns.pl. You can verify that the
new insns.dat and insns.pl produce byte-identical output to
the old insns.dat and insns.pl, so I think that this change
is safe to check in, even though it is a large change to
insns.dat.
The changes to insns.pl are:
* fixed a bug: ib,u was not recognized
* added support for a second immediate argument called "j" for
instructions like ENTER imm,imm
* added a "+r" syntax for \10..\13
[gorcunov: insns files remains the same, great job anonymous!]
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Clean up the formatting of the BMI instruction patterns, and fix:
a) X64,FUTURE is wrong - it needs to be LONG,FUTURE
b) Fix the BLSI, BLSMSK, BLSR instruction patterns
c) Use a bracket pattern for TZCNT
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
As HPA explained
|
| w.r.t. the -QQ- instruction forms... when we did
| the initial AVX implementation we decided that
| using -DQ- (double quadword) for 256-bit instructions
| was a bit messy, so we decided to accept both -DQ-
| (being official) and -QQ-
|
So move VLDQQU back and place it before VLDDQU so disassembler
match it first.
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
This form of VPEXTRW is that named 'B' form so
operands encoding should be fixed.
Reported-by: Jasper Neumann
Patch-by: Jasper Neumann
CC: "H. Peter Anvin" <hpa@zytor.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
In fact it was written as
MOVAPS xmmreg,xmmreg \360\2\x0F\x28\110 KATMAI,SSE
MOVAPS xmmreg,xmmreg \360\2\x0F\x29\101 KATMAI,SSE
in first place
MOVUPS xmmreg,xmmreg \360\2\x0F\x10\110 KATMAI,SSE
MOVUPS xmmreg,xmmreg \360\2\x0F\x11\101 KATMAI,SSE
and for example x28 stands for xmmrm128,xmmreg and
x1 for xmmrm128,xmmreg.
TODO: Inspect and fix WILLAMETTE instructions.
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Handle immediate-size optimization for "mov r64,imm" -- reduce it to
"mov r32,imm32" or "mov r64,imm32" as appropriate.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Allow implicit operands for VBLENDVP, just as for other instructions,
since the semi-legacy forms now are removed.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Version 7 of the AVX spec specifically forbids (#UD) using the
66 0F 38 14/15 forms of the BLENDV instructions with a VEX prefix;
those encodings are strictly legacy SSE 4.1.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Updates from the AVX version 7 specification: mostly tightening of the
rules for VEX.L and VEX.W, but remove the VPERMIL2 instructions.
Also encode all the full-length forms of the VCMP instructions and
prefer those for the disassembly.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Add FXSAVE64 and FXRSTOR64; drop the np prefix on 0F AE instructions:
none of the rest of the 0F AE instructions have them, and there are no
conflicts.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
FUTURE is a CPU level flag, and cannot be combined with X64 (which is
shorthand for X86_64,LONG). Also, make sure we add LONG annotations
to everything that is 64-bit mode only.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Add the RD*SBASE, WR*SBASE and RDRAND instructions from version 7 of
the AVX specification, Intel document 319433-007.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
