The "high 16" register class macros were actually incorrect, as they
simply aliased the corresponding whole set class. In oder to keep
someone from getting confused and making mistakes, remove them.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Since only EVEX supports all 32 vector registers encoding for now,
VEX/REX encoded instructions should not take high-16 registers as operands.
This filtering had been done using instruction flag so far, but
using the opflags makes more sense.
[XYZ]MMREG operands used for non-EVEX instructions are automatically
converted to [XYZ]MM_L16 in insns.pl
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Added MPX instructions and corresponding parser and encoder.
ICC style mib - base + disp and index are separate - is supported.
E.g. bndstx [ebx+3], bnd2, edx -> ebx+3 : base+disp, edx : index
As a supplement to NASM style mib - split EA - parser,
omitted base+disp is now treated as 0 displacement.
E.g. bndstx [,edx], bnd2 -> bndstx [0,edx], bnd2
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Fixed or purged some old comments and added a comment for a previous patch.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
AVX-512 introduced new syntax using braces for decorators.
Opmask, broadcat, rounding control use this new syntax.
http://software.intel.com/sites/default/files/319433-015.pdf
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
This patch is getting rid of the following bytecodes
'pushseg','popseg','pushseg2','popseg2' and simplifies
overall code.
[gorcunov@: a few style fixes]
Signed-off-by: Ben Rudiak-Gould <benrudiak@gmail.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Add the SSSE3, SSE4.1 and SSE4.2 instruction sets. Change \332 to be
a literal 0xF2 prefix, by analog with \333 for 0xF3 prefix (the
previous \332 flag changed to \335). This is necessary to get the REX
prefix in the right place for instructions that use it.
We are going to have to go in and change existing instruction patterns
which use these, as well.
Implement "REL" and "ABS" modifiers for offsets in 64-bit mode. This
replaces "rip+XXX" type addressing. The infrastructure to set the default
mode is there, but there is nothing to throw the switch just yet.
Get rid of magic open-coded register numbers. We now keep track of
a total of three different kinds of register numbers: the register
enumeration (regs.h), the x86 register value, and the register flags.
That has all the information we need.
Additionally, do massive revamping of the EA generation code and the
REX generation logic.
64-bit support required some major changes to regs.dat; clean some of
it up (re-introduce patterns, where appropriate) and allow a single
register to belong to multiple disassembly classes; also keep track
of the x86 register number again.
a) Automatically generate dependencies for all Makefiles;
b) Move register definitions to a separate .dat file;
c) Add support for "unimplemented but there in theory" registers.
