Both C and C++ have "bool", "true" and "false" in lower case; C
requires <stdbool.h> for this, in C++ it is an inherent type built
into the compiler. Use those instead of the old macros; emulate with
a simple typedef enum if unavailable.
Concentrate compiler dependencies to compiler.h; make sure compiler.h
is included first in every .c file (since some prototypes may depend
on the presence of feature request macros.)
Actually use the conditional inclusion of various functions (totally
broken in previous releases.)
Remove bogus "treat labels different from immediates" code, which
would result in generating of a relative mod/rm but without adjusting
the address accordingly.
Update addressing mode test.
Auto-generate 0x67 prefixes without the need for \30x codes; the
prefix is automatically added when there is a memory operand with
address size differing from the current address size (and impossible
combinations checked for.)
Implement oword, reso, do, as well as the SO flag to instructions. No
instructions are actually flagged with SO yet, but this allows us to
specify 128-bit sizes in instruction patterns.
This checkin completes what is required to actually generate SSE5
instructions. No support in the disassembler yet.
This checkin covers:
- Support for actually generating DREX prefixes.
- Support for matching operand "operand X must match Y"
Add the SSSE3, SSE4.1 and SSE4.2 instruction sets. Change \332 to be
a literal 0xF2 prefix, by analog with \333 for 0xF3 prefix (the
previous \332 flag changed to \335). This is necessary to get the REX
prefix in the right place for instructions that use it.
We are going to have to go in and change existing instruction patterns
which use these, as well.
We have a lot of enumerations; by declaring fields as such, we make it
easier when debugging, since the debugger can display the enumerations
in cleartext. However, make sure exceptional values (like -1) are
included in the enumeration, since the compiler otherwise may not
include it in the valid range of the enumeration.
Implement "REL" and "ABS" modifiers for offsets in 64-bit mode. This
replaces "rip+XXX" type addressing. The infrastructure to set the default
mode is there, but there is nothing to throw the switch just yet.
\313 indicates a fixed 64-bit address size. It was incorrectly
documented and incorrectly implemented in the assembler, and was
unimplemented in the disassembler.
The recent switch from register numbers (with -1 meaning "none") to
register flags (with 0 meaning "none") broke the generation of 67
prefixes, especially in 64-bit mode.
Remove tests that are bogus (they trigger for legitimate instructions.)
The failure cases are okay anyway since they will be trapped by the
REX generation logic.
Remove a bogus check for 64-bit operands. If appropriate, we will
detect this during REX generation and will bail then. However, there
are other instructions (floating point, MMX, ...) which are legitimately
64 bits in non-64-bit mode.
Get rid of magic open-coded register numbers. We now keep track of
a total of three different kinds of register numbers: the register
enumeration (regs.h), the x86 register value, and the register flags.
That has all the information we need.
Additionally, do massive revamping of the EA generation code and the
REX generation logic.
- MOV gpr,CRx or MOV CRx,gpr can access high control registers with a LOCK
prefix; handle that in both the assembler and disassembler.
- Get a saner error message when trying to access high resources in
non-64-bit mode.
