Allow the form:
mov <rm>,byte 1
... to generate the explicit byte form. An unfortunate side effect is
that disassembly is ugly; this could be fixed by making a special byte
code that acts the same for the assembler but disassembles specially.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Remove the SB flag from the rm,imm forms of the shift/rotate
instructions; presumably the intent was to mark the immediate as a
byte immediate, but it instead caused the memory operand to be
accepted without a size, but generate the incorrect code as a result.
Note: it would be good to modify the UNITY filter so that the explicit
form:
shl eax,byte 1
... forces the imm form rather than the ,1 form.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
In this path the opflags bits are completely reworked
in a sake of simplier extension. Inparticular for Knights
Corener instructions we will need new registers and new
sizes.
What's done
- all bits are grouped in sequences, and start using OP_
macros, thus if one need to extend some field -- just
tune up @shift and @bits where needed
- the #define we use in code are OR'ed in symbols, this
should be a way more convenient to deal with instead of
pure hex numbers.
The tests are passed but more eyes needed to review this
rather big and intrusive patch. The reason why it's done
in one single path -- for revertability in one command.
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
This patch introduces two macros
- OP_GENMASK, to generate masks in opflags
- OP_GENBIT, to generate bit at specified position
we will use them with extended 64 bits opflags.
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Quote filenames for Make when generated for filenames internally.
Only skip quoting when using the -MT option (rather than -MQ).
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Soon we will need to encode 512 bits values
thus there is no space left in our opflags_t
which is 32 bitfield.
Extend it to 64 bits width.
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
The 256-bit form of the VORPD instruction was deleted in checkin
89a38dac363c45d5309001a710f8cf44e7833f81, apparently by mistake.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
This should make it easier to read and moreover
now we're able to preprocess pasting as
%define N 1e%++%+ 5
dd N, 1e+5
Note that N should be expanded as series of pasting
to 1e+5 term, but before this patch we were ending
up in 1e+%+ 5 which is wrong.
In other words the fixed version output is
dd 1e+5, 1e+5
while broken one was
dd 1e+%+ 5, 1e+5
This patch also fixes nil dereferences in case if
there is no left or right token around pasting term.
http://bugzilla.nasm.us/show_bug.cgi?id=3392207
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
The 82h opcodes are undocumented aliases for the 80h opcodes, except
in 64-bit mode. We don't generate them, but let the disassembler
handle them correctly.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
The moffset opcodes A2 and A3 do not support HLE. Unfortunately
checkin
fb3f4e6d HLE: Change NOHLE to be an instruction flag
... inadvertently lost the NOHLE flag for opcode A2.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Add norexw to the 32-bit versions of instructions with only 32- and
64-bit forms (66 ignored as a size override.)
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
New instructions (ADCX, ADOX, RDSEED) from the 013 AVX spec
(Intel® Architecture Instruction Set Extensions Programming
Reference).
Note: ADCX in 64-bit mode disassembles incorrectly with a 64-bit
argument. This still needs to be fixed before a 2.10.02 release.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Add general support in the function parser for "integer functions"
(actually implemented as special unary operators, then wrapped in
macros) and implement a family of integer logarithms. The only
difference is the behavior on a non-power-of-two argument:
ilog2[e] -- throw an error
ilog2w -- throw a warning
ilog2f -- round down to power of 2
ilog2c -- round up to power of 2
This is useful for back-converting from masks to bit values.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
[backport 290eac75699fb768fdea4588772cf08b5db2788c]
2.09 series was the last one we support context-thru search
(and we were issuing a warning about that) so drop all-context
from get_ctx() routine.
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Try to implement the handling of MOVD as attempted in checkin:
70712c0df6c437c50452c4997aa2e3de5a0e0299
and reverted in:
d279fbbd80aab6f79584249629a4aea90b851458
due to BR3392199. This time make sure to use the SX flag to only
match when a size is explicitly given, and also don't duplicate the 0F
6F/7F opcodes, which are documented as MOVQ by AMD as well as Intel.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
The NASM 2.09 preprocessor allows some illogical constructs, but which
unfortunately has been found in real code in the field. We need
a compatibility solution or a pragma before we can avoid that.
However, we need the other features in NASM 2.10 to come out, so
revert the preprocessor changes for now.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
