With broadcasting, EVEX.L'L should be matched even when EVEX.b is set.
Only in a case of embedded rounding, EVEX.L'L is ignored in matching
function since it becomes EVEX.RC.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
emit_rex is supposed to write REX prefix into output stream
if needed, but we happen to drop it off on a first write
which breaks REX required instructions if TIMES directive
is used.
For example the code like
| times 4 movq xmm11, xmm11
compiles into
| 0000000000000000 <.text>:
| 0: f3 45 0f 7e db movq %xmm11,%xmm11
| 5: f3 0f 7e db movq %xmm3,%xmm3
| 9: f3 0f 7e db movq %xmm3,%xmm3
| d: f3 0f 7e db movq %xmm3,%xmm3
instead of proper
| 0000000000000000 <.text>:
| 0: f3 45 0f 7e db movq %xmm11,%xmm11
| 5: f3 45 0f 7e db movq %xmm11,%xmm11
| a: f3 45 0f 7e db movq %xmm11,%xmm11
| f: f3 45 0f 7e db movq %xmm11,%xmm11
http://bugzilla.nasm.us/show_bug.cgi?id=3392278
Reported-by: Javier <elpochodelagente@gmail.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Add the CLFLUSHOPT instruction from the Intel Instruction Set
Architecture Extensions document version 319433-018 (Feb 2014).
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Add the XSAVEC, XSAVES, and XRSTORS instructions from the Intel SDM
release 253665-050US (Feb 2014).
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
If someone specifies "section align" without =value, error out.
Reported-by: Ilya Albrekht <ilya.albrekht@gmail.com>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
BR 3392275 complains about xmm0 having to be explicitly included in
the assembly syntax when it is implicit in the encoding. In the
interest of "be liberal in what you accept", accept either form in the
input.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Elf align section attribute requires syntax "align=value",
but in case if '=' is missed we pass nil pointer into
atoi function which cause libc to crash.
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
[nosplit eax] has been encoded as [eax*1+0] since 0.98.34.
But this seems like unexpected behavior.
So only when a register is multiplied, that will be treated
as an index. ([nosplit eax*1] -> [eax*1+0])
Document is updated accordingly.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
[nosplit eax+eax] was encoded [eax*2] previously but
this seems against the user's intention.
So in this case, nosplit is ignored now and [eax+eax] will be
generated.
Document is also updated accordingly.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
In mib operands, users' intention should be preserved.
e.g.) [eax + eax*1] and [eax*2] must be distinguished and encoded differently.
So a new EA flag EAF_MIB for mib operands is added.
And a new EA hint EAH_SUMMED for the case of [eax+eax*4] being parsed
as [eax*5] is also added.
NOSPLIT specifier does not have an effect in mib, so [nosplit eax + eax*1]
will be encoded as [eax, eax] rather than [eax*2] as in a regular EA.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
asciidoc/xmlto are not tools we require every users to have, so each
tarball should contain them. That means the release script needs to
know about them.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
It's sad but not all compilers support c99 features, so drop
off IFLAG_INIT helper.
Reported-by: H. Peter Anvin <hpa@zytor.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Added bnd warning and nobnd prefix. DEFAULT directive section
has got more description about BND-related settings.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
bnd and nobnd prifixes can be used for each instruction line to
direct whether bnd registers should be preserved or not.
And those are also added as options for DEFAULT directive.
Once bnd is set with default, DEFAULT BND, all bnd-prefix
available instructions are prefixed with bnd. To override it,
nobnd prefix can be used.
In the other way, DEFAULT NOBND can disable DEFAULT BND and
have nasm encode in the normal way.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
When bnd prefix is dropped as jmp is encoded as jmp short,
nasm shows a warning message, which can be suppressed with a new
command line option, -w-bnd.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
In ndisasm, the priority follows the order of instructions in insns.dat.
Other iflags could affect this mechanism when a proper instruction form
had a higher iflag bit set.
The preferred mask bits are now limited to vendor flags (Cyrix and AMD)
and other flags do not affect disassembler any more.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Allow specifying {vex3} or {vex2} (the latter is currently always
redundant, unless we end up with instructions at some point can be
specified with legacy prefixes or VEX) to select a specific encoding
of VEX-encoded instructions.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
The "high 16" register class macros were actually incorrect, as they
simply aliased the corresponding whole set class. In oder to keep
someone from getting confused and making mistakes, remove them.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Since the multi-line macro preprocessor is modified to expand
grouped parameter with braces. The escape character is not needed
any more.
The testcase converter script is also modified not to generate '\'.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Multi-line macro uses curly braces for enclosing a parameter
containing comma(s). Passing curly braces as a part of a parameter
which is already enclosed with braces confuses the macro expander.
The number of braces in a group parameter is counted and any brace
in the outmost enclosing braces is treated as a part of parameter.
e.g.) mmacro {1,2,3}, {4,{5,6}}
mmacro gets 2 parameters of '1,2,3' and '4,{5,6}'
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
This reverts commit a800aed7b7.
As recommended by the community, braces inside a group parameter
of multi-line macro should be parsed without a need of a leading
escape character such as "\{ab,c\}".
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
As recommended by the community, a comma-separated decorators ({k1,z})
and nested braces ({{k1},{z}}) are dropped out. So only standard syntax
is supported from now.
This rework made source code neat and easy to maintain. Most of the codes
for handling corner cases are removed.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
For checking the availability of {evex} prefix, AVX512 iflag
has been used. But this is a flag for an instruction set
not for an encoding scheme. And there are some AVX512 instructions
encoded with VEX prefix.
So a new instruction flag (IF_EVEX) is added for the instructions
which are actually encoded with EVEX prefix.
This flag is automatically added by insns.pl, so no need to add manually
in insns.dat.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Since only EVEX supports all 32 vector registers encoding for now,
VEX/REX encoded instructions should not take high-16 registers as operands.
This filtering had been done using instruction flag so far, but
using the opflags makes more sense.
[XYZ]MMREG operands used for non-EVEX instructions are automatically
converted to [XYZ]MM_L16 in insns.pl
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Added the list of features added since 2.10 release.
Nasmdoc is also updated with those new features.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Only generate a signed relocation if the displacement size is less
than the address size. This matters when involving address size
overrides.
It is technically impossible to do this one perfectly, because it is
never really knowable if the displacement offset is used as a base or
an index.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
