Commit Graph

1164 Commits

Author SHA1 Message Date
H. Peter Anvin
ee71120a63 Add VCVTSI2SS (BR 1971564)
The VCVTSI2SS instruction was missing.
2008-05-24 22:09:51 -07:00
H. Peter Anvin
f2c10aee70 Fix immediate for PCLMULHQ* instructions (BR 1971555)
The immediate for the PCLMULHQ* instructions was wrong.
2008-05-24 22:07:03 -07:00
H. Peter Anvin
89031ff5d2 Remove imm from specific versions of VCMPxx
For the versions of VCMPxx which already embed their condition code,
we do not want an extra immediate argument.

Todo: fix bytecode compiler to complain more about these.
2008-05-24 22:04:23 -07:00
H. Peter Anvin
d0da1c7202 Add VLDQQU as an alias for 256-bit VLDDQU (BR 1971539)
Accept VLDQQU as an alias for VLDDQU when used with 256-bit values.
2008-05-24 21:58:59 -07:00
H. Peter Anvin
6c8042c0eb VFMSUBADDP[SD], not VFMADDSUBS[SD] (BR 1971573)
There are VFMSUBADDP instructions, but there are no VFMADDSUBS
instructions.
2008-05-24 21:54:09 -07:00
H. Peter Anvin
e3ad2ecdfe Add note about SEH support
Still need documentation from someone who actually knows anything
about how this works.
2008-05-23 21:51:21 -07:00
Andy Polyakov
94cd4dd113 Win64: IMAGEREL references (SEH support for Win64)
Guess what, SEH again, but in Win64 context, which is completely
different matter from Win32. At lowest level this one boils down to
putting so called imagerel references, or in practical terms
relocations of type ADDR32NB, 0x0003, into .pdata and .xdata
segments. Two possibilities. 1. implement say 'wrt ..imagerel' or 'wrt
..imagebase'. 2. silently enforce ADDR32NB relocations in .pdata and
.xdata segments.
2008-05-23 19:45:39 -07:00
H. Peter Anvin
45b7431a0c Make SAFESEH syntax error ERR_NONFATAL
Incorrect use of SAFESEH is more suited for ERR_NONFATAL than ERR_FATAL
2008-05-23 18:38:51 -07:00
Andy Polyakov
4401cc79a2 Support for Win32 safeseh (BR 195417)
This is basically not a bug report, but a feature request.

It's desired to be able to link .obj modules compiled with 'nasm -f
win32' with Microsoft 'link /safeseh'. As well as to register symbols
(commonly subroutine's entry points or even external symbols) as "safe
handlers." In order to achieve this, several points are required.

First of all, object module has to have absolute symbol named @feat.00
with value of 1. This can actually be achived by adding 'absolute 1'
and '@feat.00:' to source code, but it's desirable that it's
autogenerated for win32 modules.

Handler registration is essentially symbol's *index* in current
module's symbol table in .sxdata, segment with 0x200 segment flags, an
"info" segment. It's also essential that symbol has type 0x20 (see
below). All this is depicted in following framgents of 'objdump -xD'
output:

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 .sxdata       00000004  00000000  00000000  0000003c  2**2
                  CONTENTS, READONLY, DEBUGGING

SYMBOL TABLE:
...
[  5](sec -1)(fl 0x00)(ty   0)(scl   3) (nx 0) 0x00000001 @feat.00
[  6](sec  0)(fl 0x00)(ty  20)(scl   2) (nx 0) 0x00000000 _handler
...
<.sxdata>
0: 06 00 00 00

Note [6] and (ty 20) in _handle line in SYMBOL TABLE. "06 00 00 00" in
.sxdata is little-endian 6, _handler's index. This is what makes up
"registration." It's impossible to achieve this with current nasm
facilities and it's probably appropriate to introduce a directive for
it, 'safeseh _handler' is probably most natural choice.
2008-05-23 18:37:52 -07:00
H. Peter Anvin
e6a5cb536a doc: another reference to DY 2008-05-23 18:24:03 -07:00
H. Peter Anvin
1b4b42599f CHANGES since 2.02, so far... 2008-05-23 18:03:26 -07:00
H. Peter Anvin
a69749581d Document DY, RESY and YWORD 2008-05-23 17:58:01 -07:00
H. Peter Anvin
dd84acedcc AVX FMA: Instruction table for the AVX FMA instructions
This adds the AVX FMA instructions to the instruction table, which
should complete the AVX work.
2008-05-23 17:46:08 -07:00
H. Peter Anvin
55ca614e62 AVX: Remaining AVX instructions (still need FMA)
Implement the remaining set of AVX instructions
2008-05-23 17:27:15 -07:00
H. Peter Anvin
69d648800e insns.pl: better error messages, handle no-operand instructions better
Better error messages, and allow "void" instructions to omit the
operand colon.
2008-05-23 17:25:54 -07:00
H. Peter Anvin
2ee4c67e7d AVX instruction table through "P"
AVX instruction table through the letter P in the manual
2008-05-23 17:03:30 -07:00
H. Peter Anvin
ea2832c7f3 fmtinsns.pl: handle compiler fields; do some case mangling
Handle compiler-generated fields, and at least try to do some case
mangling.
2008-05-23 16:59:59 -07:00
H. Peter Anvin
072771e4a5 Use hash tables even for context-sensitive macros
Normally, contexts aren't used with a large number of macros, but in
case someone does, do use hash tables for those as well.  This
simplifies the code somewhat, since *all* handling of macros is now
done via hash tables.

Future note: consider if it wouldn't be better to allow struct
hash_table to be allocated by the caller, instead of being allocated
by the hash table routine.
2008-05-22 13:17:51 -07:00
H. Peter Anvin
bd420c7095 Add tokens vex.ww and vex.wx; vex.wx is the default
Add vex.ww (for VEX.W follows REX.W) and vex.wx (for VEX.W is a don't
care); vex.wx is the default since that seems to match existing usage
better.
2008-05-22 11:24:35 -07:00
H. Peter Anvin
7c71949931 AVX: instruction table up to PE
Complete the instruction table up to and including PE (document
319433-002, start next on page 5-330).
2008-05-21 23:21:57 -07:00
H. Peter Anvin
283ba9103e AVX: instruction table through M
Implement the AVX instruction table through the letter M.
2008-05-21 18:10:09 -07:00
H. Peter Anvin
2637aca805 insns.pl: error if we have a 'v' operand and no vex.nds/ndd
Although redundant, the presence of a 'v' operand should match the
existence of a nds or ndd flag on vex; this should help catch typos.
2008-05-21 18:09:17 -07:00
H. Peter Anvin
a69ce1d19d insnsn.c: cleaner to *not* separate out conditional instructions
The disassembler code gets cleaner if we do *not* separate out the
conditional instructions; instead, rely on the fact that the
conditionals are always at the end and use FIRST_COND_OPCODE as a
barrier.
2008-05-21 15:09:31 -07:00
H. Peter Anvin
895f56b611 Add legacy blendvpd to avx.asm, as a disassembler test. 2008-05-21 15:03:26 -07:00
H. Peter Anvin
982a7bd3dd Implement aliases for specific SSE5 compare operations
Implement aliases for specific SSE5 compare operations, per BR 1930630.
2008-05-21 15:02:30 -07:00
H. Peter Anvin
eaf3d491ad insns.dat: reimplement SSE5 compares using the bytecode compiler
Use the bytecode compiler for the SSE5 compare instructions.  While we
are at it, give it correct flags.
2008-05-21 14:45:46 -07:00
H. Peter Anvin
f89b305c32 insns.pl: match AMD documentation for DREX syntax
Adjust the compiler to give a syntax for DREX instructions that
matches the AMD documentation.
2008-05-21 14:44:42 -07:00
H. Peter Anvin
eccd1acca9 Add the PCLMUL instructions (BR 1933742)
Add the PCLMUL group instructions, from the AVX spec but not actually
AVX instructions.
2008-05-21 14:28:42 -07:00
H. Peter Anvin
cf6682fb01 Add INVEPT and INVVPID (BR 1956955) 2008-05-21 14:17:33 -07:00
H. Peter Anvin
9d5d239a9d Use "o64nw" instead of "o64i" for o64 without REX.W
Use the somewhat more mnemonic "o64nw" for 64-bit operand size sans
REX.W.
2008-05-21 14:16:49 -07:00
H. Peter Anvin
bce9da223f Add the MOVBE instructions (BR 1956954)
Add the MOVBE instructions (load/store and swap)
2008-05-21 14:03:56 -07:00
H. Peter Anvin
36b47fdfdc insns.pl: readabilty improvements for isnsnd.c
Make insnsd.c a bit more consistent in style.
2008-05-21 11:18:12 -07:00
H. Peter Anvin
2fb033af18 Disassembler: select table based on VEX prefixes
We can use the new VEX prefixes to select into a large table of new
opcode spaces.  Since the table is (currently) sparse, add logic so we
don't end up producing tons of empty tables for no good reason.

This is also necessary since VEX is likely to reuse opcode bytes that
would appear as prefixes at some point, which would cause conflicts
with the regular tables.
2008-05-21 11:05:39 -07:00
H. Peter Anvin
eb9e093840 Fix skipping 0270 code when searching for disasm prefixes
The 0270 code was incorrectly entered as 270 (decimal), which meant
that instructions with vex but no .nds got misfiled in the improper
opcode tables.
2008-05-21 10:34:33 -07:00
H. Peter Anvin
39d6ac6f79 Fix display for fixed xmm0/ymm0, SSE redundant prefixes
All singleton registers need to be displayable from register flags
alone!

When using the new 0360..0363 codes, make sure we appropriate avoid
displaying the legacy use of the prefixes.
2008-05-21 10:33:19 -07:00
Philipp Thomas
76ec8e73db Fix buffer overflow in preproc.c (BR 1942146)
Fix buffer overflow in preproc.c due to an incorrect test.  In the
code:

        for (r = p, s = ourcopy; *r; r++) {
	    if (r >= p+MAX_KEYWORD)
	    	return tokval->t_type = TOKEN_ID; /* Not a keyword */
            *s++ = tolower(*r);
	    }
        *s = '\0';

... the test really needs to be >= since for the pass where there are
equal:

a) a nonzero byte means we have > MAX_KEYWORD characters, and
b) s = ourcopy+MAX_KEYWORD; but if the test doesn't trigger,
   we can write one more character *plus* the null byte, overflowing
   ourcopy.
2008-05-21 08:53:21 -07:00
H. Peter Anvin
18c3ce2517 insns typo fix: SSE5 FNM* instructions misspelled
The SSE5 FNM* instructions were misspelled as FMN*

(Bug 1930322)
2008-05-21 08:45:17 -07:00
H. Peter Anvin
2b524d5e62 Merge branch 'master' of git+ssh://repo.or.cz/srv/git/nasm 2008-05-21 08:42:55 -07:00
H. Peter Anvin
be5133cb13 UDx instructions are 186+, not 286+
The UDx instructions are valid as far back as the #UD trap, which is
the 186, not the 286.
2008-05-21 08:41:58 -07:00
Victor van den Elzen
1fc045591b Add automation to avx test. 2008-05-21 13:33:26 +02:00
Victor van den Elzen
82fa68acec Configure tests to be performed automatically 2008-05-21 12:42:46 +02:00
Victor van den Elzen
533385ace5 Add automated testing script 2008-05-21 12:42:45 +02:00
H. Peter Anvin
6b3b7bcd33 VEX prefixes apply to VEX instructions only... 2008-05-20 23:36:36 -07:00
H. Peter Anvin
c882715a8e AVX instructions up to VMINSS 2008-05-20 23:28:46 -07:00
H. Peter Anvin
330cbd1c90 A few more AVX instructions (up to VLDMXCSR)
More AVX instructions, up to VLDMXCSR
2008-05-20 23:16:27 -07:00
H. Peter Anvin
52dc353868 Handle is4 bytes without meaningful information in the bottom bits
Support is4 bytes without meaningful information in the bottom bits.
This is equivalent to /is4=0 for the assembler, but makes the bottom
bits don't care for the disassembler.
2008-05-20 19:29:04 -07:00
H. Peter Anvin
21513e822f inslist.pl: deal with the new encoding format
Make it possible for inslist.pl to understand the new encoding format;
fix a few minor buglets.
2008-05-20 18:33:40 -07:00
H. Peter Anvin
2d31ec106a Officially specify - as the symbol for an implicit operand
Use - to denote that an operand is implicit (not encoded).  This
*better* be a fixed operand!
2008-05-20 18:21:11 -07:00
H. Peter Anvin
9681ef4144 AVX: implement all the convert instructions...
Make our way through the AVX instructions: conversions.
This is all I have time for now... hopefully this can service as a
generous source of examples.
2008-05-20 18:14:30 -07:00
H. Peter Anvin
4ae88e1a83 Accept the gas mnemonics "ud2a" and "ud2b"; fix ud0
Accept the gas mnemonics "ud2a" and "ud2b" for the instructions we
call ud2 and ud1 respectively, and Intel call ud2 and undocumented :)

Also, 0F FF is ud0 regardless of prefixes, at least as far as we know.
2008-05-20 17:14:17 -07:00