Add a "nohi" code flag for the \325 byte code, which sets the REX_NH
flag. That is, REX_P not required to support high registers, high
registers are not supported and spl/bpl/sil/dil enabled even in
non-64-bit mode.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Allow a * to be put on an operand, indicating that it is optional and
should be replaced with the immediately preceding operand if it is
omitted. This allows official and relaxed forms of nondestructive
instructions to be written on one line.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
We already have such kind of aliases for L field
(via l0 and l1). Via p0,p1,p2 it's become easier
to follow AMD docs while encoding VEX/XOP commands.
Signed-off-by: Cyrill Gorcunov <gorcunov@openvz.org>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Use lower case for VEX and XOP ("vex", "xop") to avoid visual
confusion (and in the future potential real confusion) with upper-case
hexadecimal numbers.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Handle AMD's XOP prefixes; they use basically the same encoding as VEX
prefixes, so treat them simply as a variant of VEX.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
The bytecode format assumes max 4 operands pretty strictly, but we
already have one instruction with 5 operands, and it's likely to get
more. Support them via extension prefixes (similar to REX prefixes).
For bytecodes which use argument bytes we encode the number directly,
however.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Reshuffle the bytecodes for segment register push/pop to make more
sense, and move them from \4 to \344, thus freeing up the single-digit
bytecodes \4..\7 for future use. It doesn't really make sense to use
single-digit bytecodes for this very oddball use.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
We are starting to have to worry about running short on available
bytecodes, especially where we encode the operand number in the byte
code. Thus, compile a table of bytecode usage and include as a
comment in insnsb.c.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Add a new opcode for 32->64 bit sign-extended immediate, with warning
on the number not matching.
This unfortunately calls for an audit of all the \4[0123] opcodes, if
they should be replaced by \25[4567]. This only replaces one
instruction (MOV reg64,imm32); other instructions need to be
considered.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
New opcodes to deal with 8-bit immediates which are then sign-extended
to the operand size. These allow us to warn appropriately.
Not sure I'm using these in all the proper places; need audit of all
uses of the \14..\17 opcodes.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Some pseudo-instructions (RESB and EQU) seem to make it into the
instruction table. This also generates an instruction table for
zero-length instructions, which of course can never actually be
accessed. Quiet a compiler warning by simply not emitting this
useless table. Ideally we shouldn't emit the pseudo-instructions
either, but that is a bigger change, and it's hardly a lot of memory
involved.
The disassembler code gets cleaner if we do *not* separate out the
conditional instructions; instead, rely on the fact that the
conditionals are always at the end and use FIRST_COND_OPCODE as a
barrier.
We can use the new VEX prefixes to select into a large table of new
opcode spaces. Since the table is (currently) sparse, add logic so we
don't end up producing tons of empty tables for no good reason.
This is also necessary since VEX is likely to reuse opcode bytes that
would appear as prefixes at some point, which would cause conflicts
with the regular tables.
Support is4 bytes without meaningful information in the bottom bits.
This is equivalent to /is4=0 for the assembler, but makes the bottom
bits don't care for the disassembler.
We had a completely unnecessary loop to test for conditional opcodes.
Since we always put the conditional opcodes at the end, we might as
well just remember where that list starts and compare against it.
Sometimes assembly syntax wants to permit a single operand to serve
multiple functions; allow this.
The disassembler could really use to be smarter about those.
Properly done, all SSE instructions which has the 66/F2/F3 opcode
multiplex need two prefixes: one to control the use of OSP and one to
control the use of REP. However, it's a four-way select: np/66/F2/F3;
so introduce shorthand bytecodes for that purpose.
"make alldeps" doesn't really like it when included files end in *.c.
Instead of renaming insnsb.c to insnsb.h, make it an actual
compilation unit, since there really isn't any reason for it not to
be.
Generate a byte array instead of using C compiler strings for the byte
codes. This has a few advantages:
- No need to special-case zero due to broken C compilers.
- Only insns.pl only ever reads the string, so we can invent our own
syntax.
- Compaction.
- We can give it the proper, unsigned type.
Initial NDISASM support for AVX instructions and VEX prefixes. It
doesn't mean it's correct, but it seems to match my current
understanding. It can disassemble *some*, but not *all*, of the AVX
test cases (which are known to be at least partially incorrect...)
First cut at AVX machinery support. The only instruction implemented
is VPERMIL2PS, and it's probably buggy. I'm checking this in with the
hope that other people can start helping out with (a) testing this,
and (b) adding instructions.
NDISASM support is not there yet.
