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https://github.com/netwide-assembler/nasm.git
synced 2025-04-06 18:30:21 +08:00
Reshuffle and move the bytecodes for segment register push/pop
Reshuffle the bytecodes for segment register push/pop to make more sense, and move them from \4 to \344, thus freeing up the single-digit bytecodes \4..\7 for future use. It doesn't really make sense to use single-digit bytecodes for this very oddball use. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
This commit is contained in:
H. Peter Anvin
parent
a5c31197f5
commit
ff6e12da50
102
assemble.c
102
assemble.c
@ -8,10 +8,6 @@
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* the actual codes (C syntax, i.e. octal):
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* \0 - terminates the code. (Unless it's a literal of course.)
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* \1, \2, \3 - that many literal bytes follow in the code stream
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* \4, \6 - the POP/PUSH (respectively) codes for CS, DS, ES, SS
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* (POP is never used for CS) depending on operand 0
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* \5, \7 - the second byte of POP/PUSH codes for FS, GS, depending
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* on operand 0
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* \10..\13 - a literal byte follows in the code stream, to be added
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* to the register value of operand 0..3
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* \14..\17 - a signed byte immediate operand, from operand 0..3
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@ -101,6 +97,10 @@
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* \336-\337 are still listed as prefixes in the disassembler.
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* \340 - reserve <operand 0> bytes of uninitialized storage.
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* Operand 0 had better be a segmentless constant.
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* \344,\345 - the PUSH/POP (respectively) codes for CS, DS, ES, SS
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* (POP is never used for CS) depending on operand 0
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* \346,\347 - the second byte of PUSH/POP codes for FS, GS, depending
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* on operand 0
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* \360 - no SSE prefix (== \364\331)
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* \361 - 66 SSE prefix (== \366\331)
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* \362 - F2 SSE prefix (== \364\332)
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@ -800,12 +800,6 @@ static int64_t calcsize(int32_t segment, int64_t offset, int bits,
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case 03:
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codes += c, length += c;
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break;
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case 04:
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case 05:
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case 06:
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case 07:
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length++;
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break;
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case 010:
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case 011:
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case 012:
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@ -1049,6 +1043,12 @@ static int64_t calcsize(int32_t segment, int64_t offset, int bits,
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else
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length += ins->oprs[0].offset;
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break;
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case 0344:
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case 0345:
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case 0346:
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case 0347:
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length++;
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break;
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case 0360:
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break;
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case 0361:
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@ -1202,46 +1202,6 @@ static void gencode(int32_t segment, int64_t offset, int bits,
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offset += c;
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break;
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case 04:
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case 06:
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switch (ins->oprs[0].basereg) {
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case R_CS:
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bytes[0] = 0x0E + (c == 0x04 ? 1 : 0);
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break;
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case R_DS:
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bytes[0] = 0x1E + (c == 0x04 ? 1 : 0);
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break;
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case R_ES:
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bytes[0] = 0x06 + (c == 0x04 ? 1 : 0);
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break;
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case R_SS:
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bytes[0] = 0x16 + (c == 0x04 ? 1 : 0);
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break;
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default:
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errfunc(ERR_PANIC,
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"bizarre 8086 segment register received");
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}
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out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
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offset++;
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break;
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case 05:
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case 07:
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switch (ins->oprs[0].basereg) {
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case R_FS:
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bytes[0] = 0xA0 + (c == 0x05 ? 1 : 0);
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break;
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case R_GS:
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bytes[0] = 0xA8 + (c == 0x05 ? 1 : 0);
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break;
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default:
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errfunc(ERR_PANIC,
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"bizarre 386 segment register received");
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}
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out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
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offset++;
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break;
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case 010:
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case 011:
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case 012:
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@ -1781,6 +1741,48 @@ static void gencode(int32_t segment, int64_t offset, int bits,
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}
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break;
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case 0344:
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case 0345:
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bytes[0] = c & 1;
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switch (ins->oprs[0].basereg) {
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case R_CS:
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bytes[0] += 0x0E;
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break;
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case R_DS:
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bytes[0] += 0x1E;
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break;
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case R_ES:
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bytes[0] += 0x06;
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break;
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case R_SS:
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bytes[0] += 0x16;
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break;
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default:
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errfunc(ERR_PANIC,
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"bizarre 8086 segment register received");
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}
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out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
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offset++;
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break;
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case 0346:
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case 0347:
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bytes[0] = c & 1;
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switch (ins->oprs[0].basereg) {
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case R_FS:
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bytes[0] += 0xA0;
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break;
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case R_GS:
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bytes[0] += 0xA8;
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break;
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default:
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errfunc(ERR_PANIC,
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"bizarre 386 segment register received");
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}
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out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
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offset++;
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break;
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case 0360:
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break;
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122
disasm.c
122
disasm.c
@ -407,67 +407,6 @@ static int matches(const struct itemplate *t, uint8_t *data,
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return false;
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break;
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case 04:
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switch (*data++) {
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case 0x07:
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ins->oprs[0].basereg = 0;
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break;
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case 0x17:
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ins->oprs[0].basereg = 2;
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break;
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case 0x1F:
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ins->oprs[0].basereg = 3;
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break;
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default:
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return false;
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}
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break;
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case 05:
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switch (*data++) {
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case 0xA1:
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ins->oprs[0].basereg = 4;
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break;
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case 0xA9:
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ins->oprs[0].basereg = 5;
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break;
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default:
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return false;
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}
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break;
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case 06:
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switch (*data++) {
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case 0x06:
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ins->oprs[0].basereg = 0;
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break;
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case 0x0E:
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ins->oprs[0].basereg = 1;
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break;
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case 0x16:
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ins->oprs[0].basereg = 2;
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break;
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case 0x1E:
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ins->oprs[0].basereg = 3;
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break;
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default:
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return false;
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}
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break;
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case 07:
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switch (*data++) {
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case 0xA0:
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ins->oprs[0].basereg = 4;
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break;
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case 0xA8:
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ins->oprs[0].basereg = 5;
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break;
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default:
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return false;
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}
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break;
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case4(010):
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{
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int t = *r++, d = *data++;
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@ -891,6 +830,67 @@ static int matches(const struct itemplate *t, uint8_t *data,
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case 0340:
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return false;
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case 0344:
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switch (*data++) {
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case 0x06:
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ins->oprs[0].basereg = 0;
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break;
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case 0x0E:
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ins->oprs[0].basereg = 1;
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break;
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case 0x16:
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ins->oprs[0].basereg = 2;
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break;
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case 0x1E:
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ins->oprs[0].basereg = 3;
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break;
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default:
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return false;
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}
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break;
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case 0345:
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switch (*data++) {
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case 0x07:
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ins->oprs[0].basereg = 0;
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break;
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case 0x17:
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ins->oprs[0].basereg = 2;
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break;
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case 0x1F:
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ins->oprs[0].basereg = 3;
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break;
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default:
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return false;
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}
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break;
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case 0346:
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switch (*data++) {
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case 0xA0:
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ins->oprs[0].basereg = 4;
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break;
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case 0xA8:
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ins->oprs[0].basereg = 5;
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break;
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default:
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return false;
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}
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break;
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case 0347:
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switch (*data++) {
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case 0xA1:
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ins->oprs[0].basereg = 4;
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break;
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case 0xA9:
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ins->oprs[0].basereg = 5;
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break;
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default:
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return false;
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}
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break;
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case 0360:
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if (prefix->osp || prefix->rep)
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return false;
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10
insns.dat
10
insns.dat
@ -923,8 +923,8 @@ POP rm16 \320\1\x8F\200 8086
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POP rm32 \321\1\x8F\200 386,NOLONG
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POP rm64 \323\1\x8F\200 X64
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POP reg_cs \1\x0F 8086,UNDOC,ND
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POP reg_dess \4 8086,NOLONG
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POP reg_fsgs \1\x0F\5 386
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POP reg_dess \345 8086,NOLONG
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POP reg_fsgs \1\x0F\347 386
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POPA void \322\1\x61 186,NOLONG
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POPAD void \321\1\x61 386,NOLONG
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POPAW void \320\1\x61 186,NOLONG
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@ -971,9 +971,9 @@ PUSH reg64 \323\10\x50 X64
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PUSH rm16 \320\1\xFF\206 8086
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PUSH rm32 \321\1\xFF\206 386,NOLONG
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PUSH rm64 \323\1\xFF\206 X64
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PUSH reg_cs \6 8086,NOLONG
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PUSH reg_dess \6 8086,NOLONG
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PUSH reg_fsgs \1\x0F\7 386
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PUSH reg_cs \344 8086,NOLONG
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PUSH reg_dess \344 8086,NOLONG
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PUSH reg_fsgs \1\x0F\346 386
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PUSH imm8 \1\x6A\274 186
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PUSH imm16 \320\144\x68\140 186,AR0,SZ
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PUSH imm32 \321\154\x68\150 386,NOLONG,AR0,SZ
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16
insns.pl
16
insns.pl
@ -504,14 +504,6 @@ sub startseq($) {
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}
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unshift(@codes, $c0);
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} elsif ($c0 == 04) {
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return addprefix($prefix, 0x07, 0x17, 0x1F);
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} elsif ($c0 == 05) {
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return addprefix($prefix, 0xA1, 0xA9);
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} elsif ($c0 == 06) {
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return addprefix($prefix, 0x06, 0x0E, 0x16, 0x1E);
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} elsif ($c0 == 07) {
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return addprefix($prefix, 0xA0, 0xA8);
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} elsif ($c0 >= 010 && $c0 <= 013) {
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return addprefix($prefix, $c1..($c1+7));
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} elsif (($c0 & ~013) == 0144) {
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@ -520,6 +512,14 @@ sub startseq($) {
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return addprefix($prefix, $c1..($c1+15));
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} elsif ($c0 == 0 || $c0 == 0340) {
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return $prefix;
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} elsif ($c0 == 0344) {
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return addprefix($prefix, 0x06, 0x0E, 0x16, 0x1E);
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} elsif ($c0 == 0345) {
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return addprefix($prefix, 0x07, 0x17, 0x1F);
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} elsif ($c0 == 0346) {
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return addprefix($prefix, 0xA0, 0xA8);
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} elsif ($c0 == 0347) {
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return addprefix($prefix, 0xA1, 0xA9);
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} elsif (($c0 & ~3) == 0260 || $c0 == 0270) {
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my $m,$wlp,$vxp;
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$m = shift(@codes);
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