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https://github.com/netwide-assembler/nasm.git
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Remove support for DREX encoding
The DREX encoding never hit production silicon, and has been replaced by VEX/XOP encoding, so remove support for it. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
This commit is contained in:
H. Peter Anvin
parent
573aea590e
commit
fc561203fd
67
assemble.c
67
assemble.c
@ -66,13 +66,6 @@
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* \150..\153 - an immediate dword or signed byte for operand 0..3
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* \154..\157 - or 2 (s-field) into opcode byte if operand 0..3
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* is a signed byte rather than a dword. Opcode byte follows.
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* \160..\163 - this instruction uses DREX rather than REX, with the
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* OC0 field set to 0, and the dest field taken from
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* operand 0..3.
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* \164..\167 - this instruction uses DREX rather than REX, with the
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* OC0 field set to 1, and the dest field taken from
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* operand 0..3.
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* \171 - placement of DREX suffix in the absence of an EA
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* \172\ab - the register number from operand a in bits 7..4, with
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* the 4-bit immediate from operand b in bits 3..0.
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* \173\xab - the register number from operand a in bits 7..4, with
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@ -908,21 +901,6 @@ static int64_t calcsize(int32_t segment, int64_t offset, int bits,
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length++;
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break;
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case4(0160):
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length++;
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ins->rex |= REX_D;
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ins->drexdst = regval(opx);
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break;
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case4(0164):
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length++;
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ins->rex |= REX_D|REX_OC;
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ins->drexdst = regval(opx);
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break;
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case 0171:
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break;
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case 0172:
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case 0173:
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case 0174:
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@ -940,14 +918,14 @@ static int64_t calcsize(int32_t segment, int64_t offset, int bits,
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case4(0260):
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ins->rex |= REX_V;
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ins->drexdst = regval(opx);
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ins->vexreg = regval(opx);
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ins->vex_cm = *codes++;
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ins->vex_wlp = *codes++;
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break;
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case 0270:
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ins->rex |= REX_V;
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ins->drexdst = 0;
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ins->vexreg = 0;
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ins->vex_cm = *codes++;
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ins->vex_wlp = *codes++;
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break;
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@ -1178,7 +1156,7 @@ static int64_t calcsize(int32_t segment, int64_t offset, int bits,
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break;
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}
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if (bits != 64 && ((ins->rex & bad32) || ins->drexdst > 7)) {
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if (bits != 64 && ((ins->rex & bad32) || ins->vexreg > 7)) {
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errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
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return -1;
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}
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@ -1186,17 +1164,6 @@ static int64_t calcsize(int32_t segment, int64_t offset, int bits,
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length += 3;
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else
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length += 2;
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} else if (ins->rex & REX_D) {
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if (ins->rex & REX_H) {
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errfunc(ERR_NONFATAL, "cannot use high register in drex instruction");
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return -1;
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}
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if (bits != 64 && ((ins->rex & (REX_R|REX_W|REX_X|REX_B)) ||
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ins->drexdst > 7)) {
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errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
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return -1;
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}
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length++;
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} else if (ins->rex & REX_REAL) {
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if (ins->rex & REX_H) {
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errfunc(ERR_NONFATAL, "cannot use high register in rex instruction");
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@ -1219,7 +1186,7 @@ static int64_t calcsize(int32_t segment, int64_t offset, int bits,
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}
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#define EMIT_REX() \
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if (!(ins->rex & (REX_D|REX_V)) && (ins->rex & REX_REAL) && (bits == 64)) { \
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if (!(ins->rex & REX_V) && (ins->rex & REX_REAL) && (bits == 64)) { \
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ins->rex = (ins->rex & REX_REAL)|REX_P; \
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out(offset, segment, &ins->rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG); \
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ins->rex = 0; \
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@ -1499,20 +1466,6 @@ static void gencode(int32_t segment, int64_t offset, int bits,
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offset++;
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break;
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case4(0160):
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case4(0164):
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break;
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case 0171:
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bytes[0] =
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(ins->drexdst << 4) |
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(ins->rex & REX_OC ? 0x08 : 0) |
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(ins->rex & (REX_R|REX_X|REX_B));
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ins->rex = 0;
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out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
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offset++;
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break;
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case 0172:
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c = *codes++;
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opx = &ins->oprs[c >> 3];
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@ -1588,13 +1541,13 @@ static void gencode(int32_t segment, int64_t offset, int bits,
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bytes[0] = (ins->vex_cm >> 6) ? 0x8f : 0xc4;
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bytes[1] = (ins->vex_cm & 31) | ((~ins->rex & 7) << 5);
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bytes[2] = ((ins->rex & REX_W) << (7-3)) |
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((~ins->drexdst & 15)<< 3) | (ins->vex_wlp & 07);
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((~ins->vexreg & 15)<< 3) | (ins->vex_wlp & 07);
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out(offset, segment, &bytes, OUT_RAWDATA, 3, NO_SEG, NO_SEG);
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offset += 3;
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} else {
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bytes[0] = 0xc5;
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bytes[1] = ((~ins->rex & REX_R) << (7-2)) |
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((~ins->drexdst & 15) << 3) | (ins->vex_wlp & 07);
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((~ins->vexreg & 15) << 3) | (ins->vex_wlp & 07);
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out(offset, segment, &bytes, OUT_RAWDATA, 2, NO_SEG, NO_SEG);
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offset += 2;
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}
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@ -1858,14 +1811,6 @@ static void gencode(int32_t segment, int64_t offset, int bits,
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if (ea_data.sib_present)
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*p++ = ea_data.sib;
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/* DREX suffixes come between the SIB and the displacement */
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if (ins->rex & REX_D) {
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*p++ = (ins->drexdst << 4) |
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(ins->rex & REX_OC ? 0x08 : 0) |
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(ins->rex & (REX_R|REX_X|REX_B));
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ins->rex = 0;
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}
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s = p - bytes;
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out(offset, segment, bytes, OUT_RAWDATA, s, NO_SEG, NO_SEG);
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45
disasm.c
45
disasm.c
@ -196,24 +196,6 @@ static enum reg_enum whichreg(opflags_t regflags, int regval, int rex)
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return 0;
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}
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/*
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* Process a DREX suffix
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*/
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static uint8_t *do_drex(uint8_t *data, insn *ins)
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{
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uint8_t drex = *data++;
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operand *dst = &ins->oprs[ins->drexdst];
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if ((drex & 8) != ((ins->rex & REX_OC) ? 8 : 0))
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return NULL; /* OC0 mismatch */
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ins->rex = (ins->rex & ~7) | (drex & 7);
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dst->segment = SEG_RMREG;
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dst->basereg = drex >> 4;
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return data;
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}
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/*
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* Process an effective address (ModRM) specification.
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*/
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@ -231,11 +213,6 @@ static uint8_t *do_ea(uint8_t *data, int modrm, int asize,
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if (mod != 3 && asize != 16 && rm == 4)
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sib = *data++;
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if (ins->rex & REX_D) {
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data = do_drex(data, ins);
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if (!data)
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return NULL;
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}
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rex = ins->rex;
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if (mod == 3) { /* pure register version */
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@ -621,22 +598,6 @@ static int matches(const struct itemplate *t, uint8_t *data,
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}
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break;
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case4(0160):
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ins->rex |= REX_D;
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ins->drexdst = op1;
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break;
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case4(0164):
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ins->rex |= REX_D|REX_OC;
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ins->drexdst = op1;
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break;
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case 0171:
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data = do_drex(data, ins);
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if (!data)
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return false;
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break;
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case 0172:
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{
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uint8_t ximm = *data++;
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@ -705,7 +666,7 @@ static int matches(const struct itemplate *t, uint8_t *data,
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int vexwlp = *r++;
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ins->rex |= REX_V;
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if ((prefix->rex & (REX_V|REX_D|REX_P)) != REX_V)
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if ((prefix->rex & (REX_V|REX_P)) != REX_V)
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return false;
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if ((vexm & 0x1f) != prefix->vex_m)
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@ -945,8 +906,8 @@ static int matches(const struct itemplate *t, uint8_t *data,
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if (!vex_ok && (ins->rex & REX_V))
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return false;
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/* REX cannot be combined with DREX or VEX */
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if ((ins->rex & (REX_D|REX_V)) && (prefix->rex & REX_P))
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/* REX cannot be combined with VEX */
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if ((ins->rex & REX_V) && (prefix->rex & REX_P))
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return false;
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/*
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14
insns.pl
14
insns.pl
@ -649,7 +649,6 @@ sub startseq($$) {
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# r = register field in the modr/m
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# m = modr/m
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# v = VEX "v" field
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# d = DREX "dst" field
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# i = immediate
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# s = register field of is4/imz2 field
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# - = implicit (unencoded) operand
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@ -811,19 +810,6 @@ sub byte_code_compile($$) {
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push(@codes, defined($oppos{'v'}) ? 0260+($oppos{'v'} & 3) : 0270,
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($c << 6)+$m, ($w << 4)+($l << 2)+$p);
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$prefix_ok = 0;
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} elsif ($op =~ /^\/drex([01])$/) {
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my $oc0 = $1;
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if (!defined($oppos{'d'})) {
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die "$fname: $line: DREX without a 'd' operand\n";
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}
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# Note the use of *unshift* here, as opposed to *push*.
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# This is because NASM want this byte code at the start of
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# the instruction sequence, but the AMD documentation puts
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# this at (roughly) the position of the drex byte itself.
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# This allows us to match the AMD documentation and still
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# do the right thing.
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unshift(@codes, 0160+($oppos{'d'} & 3)+($oc0 ? 4 : 0));
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unshift(@codes, 05) if ($oppos{'d'} & 4);
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} elsif ($op =~ /^(ib\,s|ib|ibx|ib\,w|iw|iwd|id|idx|iwdq|rel|rel8|rel16|rel32|iq|seg|ibw|ibd|ibd,s)$/) {
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if (!defined($oppos{'i'})) {
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die "$fname: $line: $op without 'i' operand\n";
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8
nasm.h
8
nasm.h
@ -439,10 +439,8 @@ enum ccode { /* condition code names */
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#define REX_L 0x20 /* Use LOCK prefix instead of REX.R */
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#define REX_P 0x40 /* REX prefix present/required */
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#define REX_H 0x80 /* High register present, REX forbidden */
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#define REX_D 0x0100 /* Instruction uses DREX instead of REX */
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#define REX_OC 0x0200 /* DREX suffix has the OC0 bit set */
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#define REX_V 0x0400 /* Instruction uses VEX/XOP instead of REX */
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#define REX_NH 0x0800 /* Instruction which doesn't use high regs */
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#define REX_V 0x0100 /* Instruction uses VEX/XOP instead of REX */
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#define REX_NH 0x0200 /* Instruction which doesn't use high regs */
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/*
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* REX_V "classes" (prefixes which behave like VEX)
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@ -558,7 +556,7 @@ typedef struct insn { /* an instruction itself */
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int32_t times; /* repeat count (TIMES prefix) */
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bool forw_ref; /* is there a forward reference? */
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int rex; /* Special REX Prefix */
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int drexdst; /* Destination register for DREX/VEX suffix */
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int vexreg; /* Register encoded in VEX prefix */
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int vex_cm; /* Class and M field for VEX prefix */
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int vex_wlp; /* W, P and L information for VEX prefix */
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} insn;
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