mirror of
https://github.com/netwide-assembler/nasm.git
synced 2025-01-30 16:41:05 +08:00
opflags: more int32_t -> opflags_t conversions
Hopefully this should catch all of them... but please keep an eye out for any other uses of int32_t for the operand flags. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
This commit is contained in:
H. Peter Anvin
parent
970b1012ee
commit
f8563f7a98
31
assemble.c
31
assemble.c
@ -199,11 +199,11 @@ static enum match_result find_match(const struct itemplate **tempp,
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insn *instruction,
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int32_t segment, int64_t offset, int bits);
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static enum match_result matches(const struct itemplate *, insn *, int bits);
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static int32_t regflag(const operand *);
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static opflags_t regflag(const operand *);
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static int32_t regval(const operand *);
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static int rexflags(int, int32_t, int);
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static int rexflags(int, opflags_t, int);
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static int op_rexflags(const operand *, int);
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static ea *process_ea(operand *, ea *, int, int, int, int32_t);
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static ea *process_ea(operand *, ea *, int, int, int, opflags_t);
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static void add_asp(insn *, int);
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static int has_prefix(insn * ins, enum prefix_pos pos, enum prefixes prefix)
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@ -1137,7 +1137,7 @@ static int64_t calcsize(int32_t segment, int64_t offset, int bits,
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{
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ea ea_data;
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int rfield;
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int32_t rflags;
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opflags_t rflags;
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struct operand *opy = &ins->oprs[op2];
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ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
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@ -1851,7 +1851,7 @@ static void gencode(int32_t segment, int64_t offset, int bits,
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{
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ea ea_data;
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int rfield;
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int32_t rflags;
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opflags_t rflags;
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uint8_t *p;
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int32_t s;
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enum out_type type;
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@ -1940,7 +1940,7 @@ static void gencode(int32_t segment, int64_t offset, int bits,
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}
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}
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static int32_t regflag(const operand * o)
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static opflags_t regflag(const operand * o)
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{
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if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
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errfunc(ERR_PANIC, "invalid operand passed to regflag()");
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@ -1958,7 +1958,7 @@ static int32_t regval(const operand * o)
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static int op_rexflags(const operand * o, int mask)
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{
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int32_t flags;
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opflags_t flags;
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int val;
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if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
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@ -1971,7 +1971,7 @@ static int op_rexflags(const operand * o, int mask)
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return rexflags(val, flags, mask);
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}
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static int rexflags(int val, int32_t flags, int mask)
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static int rexflags(int val, opflags_t flags, int mask)
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{
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int rex = 0;
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@ -2225,7 +2225,7 @@ static enum match_result matches(const struct itemplate *itemp,
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}
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static ea *process_ea(operand * input, ea * output, int bits,
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int addrbits, int rfield, int32_t rflags)
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int addrbits, int rfield, opflags_t rflags)
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{
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bool forw_ref = !!(input->opflags & OPFLAG_UNKNOWN);
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@ -2236,7 +2236,7 @@ static ea *process_ea(operand * input, ea * output, int bits,
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if (is_class(REGISTER, input->type)) { /* register direct */
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int i;
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int32_t f;
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opflags_t f;
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if (input->basereg < EXPR_REG_START /* Verify as Register */
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|| input->basereg >= REG_ENUM_LIMIT)
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@ -2276,9 +2276,8 @@ static ea *process_ea(operand * input, ea * output, int bits,
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int i = input->indexreg, b = input->basereg, s = input->scale;
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int32_t o = input->offset, seg = input->segment;
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int hb = input->hintbase, ht = input->hinttype;
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int t;
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int it, bt;
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int32_t ix, bx; /* register flags */
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int t, it, bt; /* register numbers */
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opflags_t x, ix, bx; /* register flags */
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if (s == 0)
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i = -1; /* make this easy, at least */
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@ -2336,7 +2335,7 @@ static ea *process_ea(operand * input, ea * output, int bits,
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|| (hb == i && ht == EAH_MAKEBASE))) {
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/* swap if hints say so */
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t = bt, bt = it, it = t;
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t = bx, bx = ix, ix = t;
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x = bx, bx = ix, ix = x;
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}
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if (bt == it) /* convert EAX+2*EAX to 3*EAX */
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bt = -1, bx = 0, s++;
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@ -2355,7 +2354,7 @@ static ea *process_ea(operand * input, ea * output, int bits,
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if (s == 1 && it == REG_NUM_ESP) {
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/* swap ESP into base if scale is 1 */
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t = it, it = bt, bt = t;
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t = ix, ix = bx, bx = t;
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x = ix, ix = bx, bx = x;
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}
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if (it == REG_NUM_ESP
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|| (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
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@ -2559,7 +2558,7 @@ static void add_asp(insn *ins, int addrbits)
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for (j = 0; j < ins->operands; j++) {
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if (!(MEMORY & ~ins->oprs[j].type)) {
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int32_t i, b;
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opflags_t i, b;
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/* Verify as Register */
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if (ins->oprs[j].indexreg < EXPR_REG_START
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2
disasm.c
2
disasm.c
@ -110,7 +110,7 @@ static uint64_t getu64(uint8_t *data)
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#define gets64(x) ((int64_t)getu64(x))
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/* Important: regval must already have been adjusted for rex extensions */
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static enum reg_enum whichreg(int32_t regflags, int regval, int rex)
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static enum reg_enum whichreg(opflags_t regflags, int regval, int rex)
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{
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if (!(regflags & (REGISTER|REGMEM)))
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return 0; /* Registers not permissible?! */
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197
nasm.h
197
nasm.h
@ -46,6 +46,7 @@
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#include "preproc.h"
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#include "insnsi.h" /* For enum opcode */
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#include "directives.h" /* For enum directive */
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#include "opflags.h"
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#define NO_SEG -1L /* null segment value */
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#define SEG_ABS 0x40000000L /* mask for far-absolute segments */
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@ -416,202 +417,6 @@ enum {
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* -----------------------------------------------------------
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*/
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/*
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* Here we define the operand types. These are implemented as bit
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* masks, since some are subsets of others; e.g. AX in a MOV
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* instruction is a special operand type, whereas AX in other
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* contexts is just another 16-bit register. (Also, consider CL in
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* shift instructions, DX in OUT, etc.)
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*
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* The basic concept here is that
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* (class & ~operand) == 0
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*
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* if and only if "operand" belongs to class type "class".
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*
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* The bits are assigned as follows:
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*
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* Bits 0-7, 23, 29: sizes
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* 0: 8 bits (BYTE)
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* 1: 16 bits (WORD)
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* 2: 32 bits (DWORD)
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* 3: 64 bits (QWORD)
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* 4: 80 bits (TWORD)
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* 5: FAR
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* 6: NEAR
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* 7: SHORT
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* 23: 256 bits (YWORD)
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* 29: 128 bits (OWORD)
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*
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* Bits 8-11 modifiers
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* 8: TO
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* 9: COLON
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* 10: STRICT
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* 11: (reserved)
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*
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* Bits 12-15: type of operand
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* 12: REGISTER
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* 13: IMMEDIATE
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* 14: MEMORY (always has REGMEM attribute as well)
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* 15: REGMEM (valid EA operand)
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*
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* Bits 16-19, 28: subclasses
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* With REG_CDT:
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* 16: REG_CREG (CRx)
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* 17: REG_DREG (DRx)
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* 18: REG_TREG (TRx)
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* With REG_GPR:
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* 16: REG_ACCUM (AL, AX, EAX, RAX)
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* 17: REG_COUNT (CL, CX, ECX, RCX)
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* 18: REG_DATA (DL, DX, EDX, RDX)
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* 19: REG_HIGH (AH, CH, DH, BH)
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* 28: REG_NOTACC (not REG_ACCUM)
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*
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* With REG_SREG:
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* 16: REG_CS
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* 17: REG_DESS (DS, ES, SS)
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* 18: REG_FSGS
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* 19: REG_SEG67
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*
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* With FPUREG:
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* 16: FPU0
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*
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* With XMMREG:
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* 16: XMM0
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*
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* With YMMREG:
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* 16: YMM0
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*
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* With MEMORY:
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* 16: MEM_OFFS (this is a simple offset)
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* 17: IP_REL (IP-relative offset)
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*
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* With IMMEDIATE:
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* 16: UNITY (1)
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* 17: BYTENESS16 (-128..127)
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* 18: BYTENESS32 (-128..127)
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* 19: BYTENESS64 (-128..127)
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*
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* Bits 20-22, 24-27: register classes
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* 20: REG_CDT (CRx, DRx, TRx)
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* 21: RM_GPR (REG_GPR) (integer register)
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* 22: REG_SREG
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* 24: FPUREG
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* 25: RM_MMX (MMXREG)
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* 26: RM_XMM (XMMREG)
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* 27: RM_YMM (YMMREG)
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*
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* Bit 31 is currently unallocated.
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*
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* 30: SAME_AS
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* Special flag only used in instruction patterns; means this operand
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* has to be identical to another operand. Currently only supported
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* for registers.
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*/
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typedef uint32_t opflags_t;
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/* Size, and other attributes, of the operand */
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#define BITS8 0x00000001U
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#define BITS16 0x00000002U
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#define BITS32 0x00000004U
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#define BITS64 0x00000008U /* x64 and FPU only */
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#define BITS80 0x00000010U /* FPU only */
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#define BITS128 0x20000000U
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#define BITS256 0x00800000U
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#define FAR 0x00000020U /* grotty: this means 16:16 or */
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/* 16:32, like in CALL/JMP */
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#define NEAR 0x00000040U
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#define SHORT 0x00000080U /* and this means what it says :) */
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#define SIZE_MASK 0x208000FFU /* all the size attributes */
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/* Modifiers */
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#define MODIFIER_MASK 0x00000f00U
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#define TO 0x00000100U /* reverse effect in FADD, FSUB &c */
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#define COLON 0x00000200U /* operand is followed by a colon */
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#define STRICT 0x00000400U /* do not optimize this operand */
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/* Type of operand: memory reference, register, etc. */
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#define OPTYPE_MASK 0x0000f000U
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#define REGISTER 0x00001000U /* register number in 'basereg' */
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#define IMMEDIATE 0x00002000U
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#define MEMORY 0x0000c000U
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#define REGMEM 0x00008000U /* for r/m, ie EA, operands */
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#define is_class(class, op) (!((opflags_t)(class) & ~(opflags_t)(op)))
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/* Register classes */
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#define REG_EA 0x00009000U /* 'normal' reg, qualifies as EA */
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#define RM_GPR 0x00208000U /* integer operand */
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#define REG_GPR 0x00209000U /* integer register */
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#define REG8 0x00209001U /* 8-bit GPR */
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#define REG16 0x00209002U /* 16-bit GPR */
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#define REG32 0x00209004U /* 32-bit GPR */
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#define REG64 0x00209008U /* 64-bit GPR */
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#define FPUREG 0x01001000U /* floating point stack registers */
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#define FPU0 0x01011000U /* FPU stack register zero */
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#define RM_MMX 0x02008000U /* MMX operand */
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#define MMXREG 0x02009000U /* MMX register */
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#define RM_XMM 0x04008000U /* XMM (SSE) operand */
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#define XMMREG 0x04009000U /* XMM (SSE) register */
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#define XMM0 0x04019000U /* XMM register zero */
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#define RM_YMM 0x08008000U /* YMM (AVX) operand */
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#define YMMREG 0x08009000U /* YMM (AVX) register */
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#define YMM0 0x08019000U /* YMM register zero */
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#define REG_CDT 0x00101004U /* CRn, DRn and TRn */
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#define REG_CREG 0x00111004U /* CRn */
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#define REG_DREG 0x00121004U /* DRn */
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#define REG_TREG 0x00141004U /* TRn */
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#define REG_SREG 0x00401002U /* any segment register */
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#define REG_CS 0x00411002U /* CS */
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#define REG_DESS 0x00421002U /* DS, ES, SS */
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#define REG_FSGS 0x00441002U /* FS, GS */
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#define REG_SEG67 0x00481002U /* Unimplemented segment registers */
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#define REG_RIP 0x00801008U /* RIP relative addressing */
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#define REG_EIP 0x00801004U /* EIP relative addressing */
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/* Special GPRs */
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#define REG_SMASK 0x100f0000U /* a mask for the following */
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#define REG_ACCUM 0x00219000U /* accumulator: AL, AX, EAX, RAX */
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#define REG_AL 0x00219001U
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#define REG_AX 0x00219002U
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#define REG_EAX 0x00219004U
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#define REG_RAX 0x00219008U
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#define REG_COUNT 0x10229000U /* counter: CL, CX, ECX, RCX */
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#define REG_CL 0x10229001U
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#define REG_CX 0x10229002U
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#define REG_ECX 0x10229004U
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#define REG_RCX 0x10229008U
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#define REG_DL 0x10249001U /* data: DL, DX, EDX, RDX */
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#define REG_DX 0x10249002U
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#define REG_EDX 0x10249004U
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#define REG_RDX 0x10249008U
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#define REG_HIGH 0x10289001U /* high regs: AH, CH, DH, BH */
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#define REG_NOTACC 0x10000000U /* non-accumulator register */
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#define REG8NA 0x10209001U /* 8-bit non-acc GPR */
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#define REG16NA 0x10209002U /* 16-bit non-acc GPR */
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#define REG32NA 0x10209004U /* 32-bit non-acc GPR */
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#define REG64NA 0x10209008U /* 64-bit non-acc GPR */
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/* special types of EAs */
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#define MEM_OFFS 0x0001c000U /* simple [address] offset - absolute! */
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#define IP_REL 0x0002c000U /* IP-relative offset */
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/* memory which matches any type of r/m operand */
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#define MEMORY_ANY (MEMORY|RM_GPR|RM_MMX|RM_XMM|RM_YMM)
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/* special type of immediate operand */
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#define UNITY 0x00012000U /* for shift/rotate instructions */
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#define SBYTE16 0x00022000U /* for op r16,immediate instrs. */
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#define SBYTE32 0x00042000U /* for op r32,immediate instrs. */
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#define SBYTE64 0x00082000U /* for op r64,immediate instrs. */
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#define BYTENESS 0x000e0000U /* for testing for byteness */
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/* special flags */
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#define SAME_AS 0x40000000U
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/* Register names automatically generated from regs.dat */
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#include "regs.h"
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239
opflags.h
Normal file
239
opflags.h
Normal file
@ -0,0 +1,239 @@
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/* ----------------------------------------------------------------------- *
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*
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* Copyright 1996-2009 The NASM Authors - All Rights Reserved
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* See the file AUTHORS included with the NASM distribution for
|
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* the specific copyright holders.
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following
|
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* conditions are met:
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*
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* * Redistributions of source code must retain the above copyright
|
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* notice, this list of conditions and the following disclaimer.
|
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* * Redistributions in binary form must reproduce the above
|
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* copyright notice, this list of conditions and the following
|
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* disclaimer in the documentation and/or other materials provided
|
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* with the distribution.
|
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
|
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* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
|
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* ----------------------------------------------------------------------- */
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/*
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* opflags.h - operand flags
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*/
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#ifndef NASM_OPFLAGS_H
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#define NASM_OPFLAGS_H
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#include "compiler.h"
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/*
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* Here we define the operand types. These are implemented as bit
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* masks, since some are subsets of others; e.g. AX in a MOV
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* instruction is a special operand type, whereas AX in other
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* contexts is just another 16-bit register. (Also, consider CL in
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* shift instructions, DX in OUT, etc.)
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*
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* The basic concept here is that
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* (class & ~operand) == 0
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*
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* if and only if "operand" belongs to class type "class".
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*
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* The bits are assigned as follows:
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*
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* Bits 0-7, 23, 29: sizes
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* 0: 8 bits (BYTE)
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||||
* 1: 16 bits (WORD)
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* 2: 32 bits (DWORD)
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* 3: 64 bits (QWORD)
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* 4: 80 bits (TWORD)
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* 5: FAR
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* 6: NEAR
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* 7: SHORT
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* 23: 256 bits (YWORD)
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* 29: 128 bits (OWORD)
|
||||
*
|
||||
* Bits 8-11 modifiers
|
||||
* 8: TO
|
||||
* 9: COLON
|
||||
* 10: STRICT
|
||||
* 11: (reserved)
|
||||
*
|
||||
* Bits 12-15: type of operand
|
||||
* 12: REGISTER
|
||||
* 13: IMMEDIATE
|
||||
* 14: MEMORY (always has REGMEM attribute as well)
|
||||
* 15: REGMEM (valid EA operand)
|
||||
*
|
||||
* Bits 16-19, 28: subclasses
|
||||
* With REG_CDT:
|
||||
* 16: REG_CREG (CRx)
|
||||
* 17: REG_DREG (DRx)
|
||||
* 18: REG_TREG (TRx)
|
||||
|
||||
* With REG_GPR:
|
||||
* 16: REG_ACCUM (AL, AX, EAX, RAX)
|
||||
* 17: REG_COUNT (CL, CX, ECX, RCX)
|
||||
* 18: REG_DATA (DL, DX, EDX, RDX)
|
||||
* 19: REG_HIGH (AH, CH, DH, BH)
|
||||
* 28: REG_NOTACC (not REG_ACCUM)
|
||||
*
|
||||
* With REG_SREG:
|
||||
* 16: REG_CS
|
||||
* 17: REG_DESS (DS, ES, SS)
|
||||
* 18: REG_FSGS
|
||||
* 19: REG_SEG67
|
||||
*
|
||||
* With FPUREG:
|
||||
* 16: FPU0
|
||||
*
|
||||
* With XMMREG:
|
||||
* 16: XMM0
|
||||
*
|
||||
* With YMMREG:
|
||||
* 16: YMM0
|
||||
*
|
||||
* With MEMORY:
|
||||
* 16: MEM_OFFS (this is a simple offset)
|
||||
* 17: IP_REL (IP-relative offset)
|
||||
*
|
||||
* With IMMEDIATE:
|
||||
* 16: UNITY (1)
|
||||
* 17: BYTENESS16 (-128..127)
|
||||
* 18: BYTENESS32 (-128..127)
|
||||
* 19: BYTENESS64 (-128..127)
|
||||
*
|
||||
* Bits 20-22, 24-27: register classes
|
||||
* 20: REG_CDT (CRx, DRx, TRx)
|
||||
* 21: RM_GPR (REG_GPR) (integer register)
|
||||
* 22: REG_SREG
|
||||
* 24: FPUREG
|
||||
* 25: RM_MMX (MMXREG)
|
||||
* 26: RM_XMM (XMMREG)
|
||||
* 27: RM_YMM (YMMREG)
|
||||
*
|
||||
* Bit 31 is currently unallocated.
|
||||
*
|
||||
* 30: SAME_AS
|
||||
* Special flag only used in instruction patterns; means this operand
|
||||
* has to be identical to another operand. Currently only supported
|
||||
* for registers.
|
||||
*/
|
||||
|
||||
typedef uint32_t opflags_t;
|
||||
|
||||
/* Size, and other attributes, of the operand */
|
||||
#define BITS8 0x00000001U
|
||||
#define BITS16 0x00000002U
|
||||
#define BITS32 0x00000004U
|
||||
#define BITS64 0x00000008U /* x64 and FPU only */
|
||||
#define BITS80 0x00000010U /* FPU only */
|
||||
#define BITS128 0x20000000U
|
||||
#define BITS256 0x00800000U
|
||||
#define FAR 0x00000020U /* grotty: this means 16:16 or */
|
||||
/* 16:32, like in CALL/JMP */
|
||||
#define NEAR 0x00000040U
|
||||
#define SHORT 0x00000080U /* and this means what it says :) */
|
||||
|
||||
#define SIZE_MASK 0x208000FFU /* all the size attributes */
|
||||
|
||||
/* Modifiers */
|
||||
#define MODIFIER_MASK 0x00000f00U
|
||||
#define TO 0x00000100U /* reverse effect in FADD, FSUB &c */
|
||||
#define COLON 0x00000200U /* operand is followed by a colon */
|
||||
#define STRICT 0x00000400U /* do not optimize this operand */
|
||||
|
||||
/* Type of operand: memory reference, register, etc. */
|
||||
#define OPTYPE_MASK 0x0000f000U
|
||||
#define REGISTER 0x00001000U /* register number in 'basereg' */
|
||||
#define IMMEDIATE 0x00002000U
|
||||
#define MEMORY 0x0000c000U
|
||||
#define REGMEM 0x00008000U /* for r/m, ie EA, operands */
|
||||
|
||||
#define is_class(class, op) (!((opflags_t)(class) & ~(opflags_t)(op)))
|
||||
|
||||
/* Register classes */
|
||||
#define REG_EA 0x00009000U /* 'normal' reg, qualifies as EA */
|
||||
#define RM_GPR 0x00208000U /* integer operand */
|
||||
#define REG_GPR 0x00209000U /* integer register */
|
||||
#define REG8 0x00209001U /* 8-bit GPR */
|
||||
#define REG16 0x00209002U /* 16-bit GPR */
|
||||
#define REG32 0x00209004U /* 32-bit GPR */
|
||||
#define REG64 0x00209008U /* 64-bit GPR */
|
||||
#define FPUREG 0x01001000U /* floating point stack registers */
|
||||
#define FPU0 0x01011000U /* FPU stack register zero */
|
||||
#define RM_MMX 0x02008000U /* MMX operand */
|
||||
#define MMXREG 0x02009000U /* MMX register */
|
||||
#define RM_XMM 0x04008000U /* XMM (SSE) operand */
|
||||
#define XMMREG 0x04009000U /* XMM (SSE) register */
|
||||
#define XMM0 0x04019000U /* XMM register zero */
|
||||
#define RM_YMM 0x08008000U /* YMM (AVX) operand */
|
||||
#define YMMREG 0x08009000U /* YMM (AVX) register */
|
||||
#define YMM0 0x08019000U /* YMM register zero */
|
||||
#define REG_CDT 0x00101004U /* CRn, DRn and TRn */
|
||||
#define REG_CREG 0x00111004U /* CRn */
|
||||
#define REG_DREG 0x00121004U /* DRn */
|
||||
#define REG_TREG 0x00141004U /* TRn */
|
||||
#define REG_SREG 0x00401002U /* any segment register */
|
||||
#define REG_CS 0x00411002U /* CS */
|
||||
#define REG_DESS 0x00421002U /* DS, ES, SS */
|
||||
#define REG_FSGS 0x00441002U /* FS, GS */
|
||||
#define REG_SEG67 0x00481002U /* Unimplemented segment registers */
|
||||
|
||||
#define REG_RIP 0x00801008U /* RIP relative addressing */
|
||||
#define REG_EIP 0x00801004U /* EIP relative addressing */
|
||||
|
||||
/* Special GPRs */
|
||||
#define REG_SMASK 0x100f0000U /* a mask for the following */
|
||||
#define REG_ACCUM 0x00219000U /* accumulator: AL, AX, EAX, RAX */
|
||||
#define REG_AL 0x00219001U
|
||||
#define REG_AX 0x00219002U
|
||||
#define REG_EAX 0x00219004U
|
||||
#define REG_RAX 0x00219008U
|
||||
#define REG_COUNT 0x10229000U /* counter: CL, CX, ECX, RCX */
|
||||
#define REG_CL 0x10229001U
|
||||
#define REG_CX 0x10229002U
|
||||
#define REG_ECX 0x10229004U
|
||||
#define REG_RCX 0x10229008U
|
||||
#define REG_DL 0x10249001U /* data: DL, DX, EDX, RDX */
|
||||
#define REG_DX 0x10249002U
|
||||
#define REG_EDX 0x10249004U
|
||||
#define REG_RDX 0x10249008U
|
||||
#define REG_HIGH 0x10289001U /* high regs: AH, CH, DH, BH */
|
||||
#define REG_NOTACC 0x10000000U /* non-accumulator register */
|
||||
#define REG8NA 0x10209001U /* 8-bit non-acc GPR */
|
||||
#define REG16NA 0x10209002U /* 16-bit non-acc GPR */
|
||||
#define REG32NA 0x10209004U /* 32-bit non-acc GPR */
|
||||
#define REG64NA 0x10209008U /* 64-bit non-acc GPR */
|
||||
|
||||
/* special types of EAs */
|
||||
#define MEM_OFFS 0x0001c000U /* simple [address] offset - absolute! */
|
||||
#define IP_REL 0x0002c000U /* IP-relative offset */
|
||||
|
||||
/* memory which matches any type of r/m operand */
|
||||
#define MEMORY_ANY (MEMORY|RM_GPR|RM_MMX|RM_XMM|RM_YMM)
|
||||
|
||||
/* special type of immediate operand */
|
||||
#define UNITY 0x00012000U /* for shift/rotate instructions */
|
||||
#define SBYTE16 0x00022000U /* for op r16,immediate instrs. */
|
||||
#define SBYTE32 0x00042000U /* for op r32,immediate instrs. */
|
||||
#define SBYTE64 0x00082000U /* for op r64,immediate instrs. */
|
||||
#define BYTENESS 0x000e0000U /* for testing for byteness */
|
||||
|
||||
/* special flags */
|
||||
#define SAME_AS 0x40000000U
|
||||
|
||||
#endif /* NASM_OPFLAGS_H */
|
||||
2
regs.pl
2
regs.pl
@ -151,7 +151,7 @@ if ( $fmt eq 'h' ) {
|
||||
print "/* automatically generated from $file - do not edit */\n\n";
|
||||
print "#include \"tables.h\"\n";
|
||||
print "#include \"nasm.h\"\n\n";
|
||||
print "const int32_t nasm_reg_flags[] = {\n";
|
||||
print "const opflags_t nasm_reg_flags[] = {\n";
|
||||
printf " 0,\n"; # Dummy entry for 0
|
||||
foreach $reg ( sort(keys(%regs)) ) {
|
||||
# Print the class of the register
|
||||
|
||||
9
tables.h
9
tables.h
@ -37,12 +37,13 @@
|
||||
* Declarations for auto-generated tables
|
||||
*/
|
||||
|
||||
#ifndef TABLES_H
|
||||
#define TABLES_H
|
||||
#ifndef NASM_TABLES_H
|
||||
#define NASM_TABLES_H
|
||||
|
||||
#include "compiler.h"
|
||||
#include <inttypes.h>
|
||||
#include "insnsi.h" /* For enum opcode */
|
||||
#include "opflags.h" /* For opflags_t */
|
||||
|
||||
/* --- From standard.mac via macros.pl: --- */
|
||||
|
||||
@ -61,8 +62,8 @@ extern const char * const nasm_insn_names[];
|
||||
/* regs.c */
|
||||
extern const char * const nasm_reg_names[];
|
||||
/* regflags.c */
|
||||
extern const int32_t nasm_reg_flags[];
|
||||
extern const opflags_t nasm_reg_flags[];
|
||||
/* regvals.c */
|
||||
extern const int nasm_regvals[];
|
||||
|
||||
#endif /* TABLES_H */
|
||||
#endif /* NASM_TABLES_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user