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insns: make the MMX version of PINSRW match the SSE/AVX ones
Make the MMX version of PINSRW match the SSE and AVX ones, and add it to the tests. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
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@ -1504,9 +1504,9 @@ PAVGW mmxreg,mmxrm \360\323\2\x0F\xE3\110 KATMAI,MMX,SQ
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PEXTRW reg32,mmxreg,imm \360\2\x0F\xC5\110\26 KATMAI,MMX,SB,AR2
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; PINSRW is documented as using a reg32, but it's really using only 16 bit
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; -- accept either, but be truthful in disassembly
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PINSRW mmxreg,reg16,imm \360\2\x0F\xC4\110\26 KATMAI,MMX
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PINSRW mmxreg,reg32,imm \360\2\x0F\xC4\110\26 KATMAI,MMX,ND
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PINSRW mmxreg,mem,imm \360\2\x0F\xC4\110\26 KATMAI,MMX,SW,AR1
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PINSRW mmxreg,mem,imm \360\2\x0F\xC4\110\26 KATMAI,MMX,SB,AR2
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PINSRW mmxreg,rm16,imm \360\2\x0F\xC4\110\26 KATMAI,MMX,SB,AR2
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PINSRW mmxreg,reg32,imm \360\2\x0F\xC4\110\26 KATMAI,MMX,SB,AR2
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PMAXSW mmxreg,mmxrm \360\323\2\x0F\xEE\110 KATMAI,MMX,SQ
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PMAXUB mmxreg,mmxrm \360\323\2\x0F\xDE\110 KATMAI,MMX,SQ
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PMINSW mmxreg,mmxrm \360\323\2\x0F\xEA\110 KATMAI,MMX,SQ
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@ -1,5 +1,10 @@
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bits 16
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pinsrw mm0,eax,0
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pinsrw mm1,si,0
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pinsrw mm2,[bx],0
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pinsrw mm3,word [bx],0
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pinsrb xmm0,eax,0
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pinsrb xmm1,sil,0
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; pinsrb xmm1,bh,0
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@ -1,5 +1,10 @@
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bits 32
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pinsrw mm0,eax,0
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pinsrw mm1,si,0
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pinsrw mm2,[ecx],0
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pinsrw mm3,word [ecx],0
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pinsrb xmm0,eax,0
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pinsrb xmm1,sil,0
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; pinsrb xmm1,bh,0
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@ -1,24 +1,29 @@
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bits 64
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pinsrw mm0,eax,0
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pinsrw mm1,si,0
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pinsrw mm2,[rcx],0
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pinsrw mm3,word [rcx],0
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pinsrb xmm0,eax,0
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pinsrb xmm1,sil,0 ; BROKEN
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; pinsrb xmm1,bh,0 ; BROKEN
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pinsrb xmm1,sil,0
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; pinsrb xmm1,bh,0
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pinsrb xmm2,[rcx],0
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pinsrb xmm3,byte [rcx],0 ; BROKEN
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pinsrb xmm3,byte [rcx],0
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pinsrw xmm0,eax,0
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pinsrw xmm1,si,0
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pinsrw xmm2,[rcx],0
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pinsrw xmm3,word [rcx],0 ; BROKEN
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pinsrw xmm3,word [rcx],0
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pinsrd xmm0,eax,0
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pinsrd xmm1,esi,0
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pinsrd xmm2,[rcx],0 ; BROKEN
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pinsrd xmm2,[rcx],0
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pinsrd xmm3,dword [rcx],0
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pinsrq xmm0,rax,0
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pinsrq xmm1,rsi,0
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pinsrq xmm2,[rcx],0 ; BROKEN
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pinsrq xmm2,[rcx],0
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pinsrq xmm3,qword [rcx],0
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vpinsrb xmm0,eax,0
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