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https://github.com/netwide-assembler/nasm.git
synced 2024-11-21 03:14:19 +08:00
insns.pl: audit for impossible Sx patterns; fix a few
Break the instruction processing if there are impossible combinations of Sx flags and operand sizes. If the intent is to always require explicit sizes, use the SX flag. The INSERTPS instruction pattern was explicitly wrong, the rest of these are nuisance fixes. TODO: fix the disassembler to be able to exclude patterns where these bits don't matter. Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
This commit is contained in:
H. Peter Anvin (Intel)
parent
5b89628e44
commit
e56c2dc5b7
36
test/immsize.asm
Normal file
36
test/immsize.asm
Normal file
@ -0,0 +1,36 @@
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bits 64
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%macro b 1
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%1 ax,16
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%1 eax,16
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%1 rax,16
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%1 word [rdi],16
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%1 dword [rdi],16
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%1 qword [rdi],16
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%1 ax,byte 16
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%1 eax,byte 16
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%1 rax,byte 16
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%1 word [rdi],byte 16
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%1 dword [rdi],byte 16
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%1 qword [rdi],byte 16
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%endmacro
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b bt
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b btc
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b btr
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b bts
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imul ax,[rdi],16
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imul ax,word [rdi],16
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imul ax,[rdi],byte 16
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imul ax,word [rdi],byte 16
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imul eax,[rdi],16
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imul eax,dword [rdi],16
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imul eax,[rdi],byte 16
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imul eax,dword [rdi],byte 16
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imul rax,[rdi],16
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imul rax,qword [rdi],16
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imul rax,[rdi],byte 16
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imul rax,qword [rdi],byte 16
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10
test/insertps.asm
Normal file
10
test/insertps.asm
Normal file
@ -0,0 +1,10 @@
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bits 64
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insertps xmm0,xmm1,16
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insertps xmm0,dword xmm1,16
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insertps xmm0,xmm1,byte 16
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insertps xmm0,dword xmm1,byte 16
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insertps xmm0,[rax],16
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insertps xmm0,dword [rax],16
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insertps xmm0,[rax],byte 16
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insertps xmm0,dword [rax],byte 16
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15
test/movhpd.asm
Normal file
15
test/movhpd.asm
Normal file
@ -0,0 +1,15 @@
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bits 64
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movhpd xmm0,[rdi+2]
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movhpd xmm0,qword [rdi+2]
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movhpd [rsi+3],xmm1
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movhpd qword [rsi+3],xmm1
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vmovhpd xmm2,xmm1,[rax+4]
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vmovhpd xmm2,xmm1,qword [rax+4]
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vmovhpd xmm3,[rax+4]
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vmovhpd xmm3,qword [rax+4]
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vmovhpd [rcx+5],xmm4
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vmovhpd qword [rcx+5],xmm4
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14
test/ssesize.asm
Normal file
14
test/ssesize.asm
Normal file
@ -0,0 +1,14 @@
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_start:
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movd ecx,xmm0
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movd [foo],xmm0
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movd dword [foo],xmm0
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movdqa xmm1,xmm0
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movdqa [foo],xmm0
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movdqa oword [foo],xmm0
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cmppd xmm2,xmm3,8
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cmppd xmm2,xmm3,byte 8
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section .bss
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foo: reso 1
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@ -218,36 +218,36 @@ BT mem,reg32 [mr: o32 0f a3 /r] 386,SM
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BT reg32,reg32 [mr: o32 0f a3 /r] 386
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BT mem,reg64 [mr: o64 0f a3 /r] X86_64,LONG,SM
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BT reg64,reg64 [mr: o64 0f a3 /r] X86_64,LONG
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BT rm16,imm [mi: o16 0f ba /4 ib,u] 386,SB
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BT rm32,imm [mi: o32 0f ba /4 ib,u] 386,SB
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BT rm64,imm [mi: o64 0f ba /4 ib,u] X86_64,LONG,SB
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BT rm16,imm8 [mi: o16 0f ba /4 ib,u] 386
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BT rm32,imm8 [mi: o32 0f ba /4 ib,u] 386
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BT rm64,imm8 [mi: o64 0f ba /4 ib,u] X86_64,LONG
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BTC mem,reg16 [mr: hle o16 0f bb /r] 386,SM,LOCK
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BTC reg16,reg16 [mr: o16 0f bb /r] 386
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BTC mem,reg32 [mr: hle o32 0f bb /r] 386,SM,LOCK
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BTC reg32,reg32 [mr: o32 0f bb /r] 386
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BTC mem,reg64 [mr: hle o64 0f bb /r] X86_64,LONG,SM,LOCK
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BTC reg64,reg64 [mr: o64 0f bb /r] X86_64,LONG
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BTC rm16,imm [mi: hle o16 0f ba /7 ib,u] 386,SB,LOCK
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BTC rm32,imm [mi: hle o32 0f ba /7 ib,u] 386,SB,LOCK
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BTC rm64,imm [mi: hle o64 0f ba /7 ib,u] X86_64,LONG,SB,LOCK
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BTC rm16,imm8 [mi: hle o16 0f ba /7 ib,u] 386,LOCK
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BTC rm32,imm8 [mi: hle o32 0f ba /7 ib,u] 386,LOCK
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BTC rm64,imm8 [mi: hle o64 0f ba /7 ib,u] X86_64,LONG,LOCK
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BTR mem,reg16 [mr: hle o16 0f b3 /r] 386,SM,LOCK
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BTR reg16,reg16 [mr: o16 0f b3 /r] 386
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BTR mem,reg32 [mr: hle o32 0f b3 /r] 386,SM,LOCK
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BTR reg32,reg32 [mr: o32 0f b3 /r] 386
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BTR mem,reg64 [mr: hle o64 0f b3 /r] X86_64,LONG,SM,LOCK
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BTR reg64,reg64 [mr: o64 0f b3 /r] X86_64,LONG
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BTR rm16,imm [mi: hle o16 0f ba /6 ib,u] 386,SB,LOCK
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BTR rm32,imm [mi: hle o32 0f ba /6 ib,u] 386,SB,LOCK
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BTR rm64,imm [mi: hle o64 0f ba /6 ib,u] X86_64,LONG,SB,LOCK
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BTR rm16,imm8 [mi: hle o16 0f ba /6 ib,u] 386,LOCK
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BTR rm32,imm8 [mi: hle o32 0f ba /6 ib,u] 386,LOCK
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BTR rm64,imm8 [mi: hle o64 0f ba /6 ib,u] X86_64,LONG,LOCK
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BTS mem,reg16 [mr: hle o16 0f ab /r] 386,SM,LOCK
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BTS reg16,reg16 [mr: o16 0f ab /r] 386
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BTS mem,reg32 [mr: hle o32 0f ab /r] 386,SM,LOCK
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BTS reg32,reg32 [mr: o32 0f ab /r] 386
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BTS mem,reg64 [mr: hle o64 0f ab /r] X86_64,LONG,SM,LOCK
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BTS reg64,reg64 [mr: o64 0f ab /r] X86_64,LONG
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BTS rm16,imm [mi: hle o16 0f ba /5 ib,u] 386,SB,LOCK
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BTS rm32,imm [mi: hle o32 0f ba /5 ib,u] 386,SB,LOCK
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BTS rm64,imm [mi: hle o64 0f ba /5 ib,u] X86_64,LONG,SB,LOCK
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BTS rm16,imm8 [mi: hle o16 0f ba /5 ib,u] 386,LOCK
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BTS rm32,imm8 [mi: hle o32 0f ba /5 ib,u] 386,LOCK
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BTS rm64,imm8 [mi: hle o64 0f ba /5 ib,u] X86_64,LONG,LOCK
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CALL imm [i: odf e8 rel] 8086,BND
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CALL imm|near [i: odf e8 rel] 8086,ND,BND
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CALL imm|far [i: odf 9a iwd seg] 8086,ND,NOLONG
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@ -607,7 +607,7 @@ IMUL reg32,mem [rm: o32 0f af /r] 386,SM
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IMUL reg32,reg32 [rm: o32 0f af /r] 386
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IMUL reg64,mem [rm: o64 0f af /r] X86_64,LONG,SM
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IMUL reg64,reg64 [rm: o64 0f af /r] X86_64,LONG
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IMUL reg16,mem,imm8 [rmi: o16 6b /r ib,s] 186,SM
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IMUL reg16,mem,imm8 [rmi: o16 6b /r ib,s] 186,SM2
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IMUL reg16,mem,sbyteword [rmi: o16 6b /r ib,s] 186,SM,ND
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IMUL reg16,mem,imm16 [rmi: o16 69 /r iw] 186,SM
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IMUL reg16,mem,imm [rmi: o16 69 /r iw] 186,SM,ND
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@ -615,7 +615,7 @@ IMUL reg16,reg16,imm8 [rmi: o16 6b /r ib,s] 186
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IMUL reg16,reg16,sbyteword [rmi: o16 6b /r ib,s] 186,SM,ND
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IMUL reg16,reg16,imm16 [rmi: o16 69 /r iw] 186
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IMUL reg16,reg16,imm [rmi: o16 69 /r iw] 186,SM,ND
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IMUL reg32,mem,imm8 [rmi: o32 6b /r ib,s] 386,SM
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IMUL reg32,mem,imm8 [rmi: o32 6b /r ib,s] 386,SM2
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IMUL reg32,mem,sbytedword [rmi: o32 6b /r ib,s] 386,SM,ND
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IMUL reg32,mem,imm32 [rmi: o32 69 /r id] 386,SM
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IMUL reg32,mem,imm [rmi: o32 69 /r id] 386,SM,ND
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@ -623,9 +623,9 @@ IMUL reg32,reg32,imm8 [rmi: o32 6b /r ib,s] 386
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IMUL reg32,reg32,sbytedword [rmi: o32 6b /r ib,s] 386,SM,ND
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IMUL reg32,reg32,imm32 [rmi: o32 69 /r id] 386
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IMUL reg32,reg32,imm [rmi: o32 69 /r id] 386,SM,ND
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IMUL reg64,mem,imm8 [rmi: o64 6b /r ib,s] X86_64,LONG,SM
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IMUL reg64,mem,imm8 [rmi: o64 6b /r ib,s] X86_64,LONG,SM2
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IMUL reg64,mem,sbytedword [rmi: o64 6b /r ib,s] X86_64,LONG,SM,ND
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IMUL reg64,mem,imm32 [rmi: o64 69 /r id] X86_64,LONG,SM
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IMUL reg64,mem,imm32 [rmi: o64 69 /r id] X86_64,LONG,SM2
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IMUL reg64,mem,imm [rmi: o64 69 /r id,s] X86_64,LONG,SM,ND
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IMUL reg64,reg64,imm8 [rmi: o64 6b /r ib,s] X86_64,LONG
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IMUL reg64,reg64,sbytedword [rmi: o64 6b /r ib,s] X86_64,LONG,SM,ND
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@ -1959,7 +1959,7 @@ DPPD xmmreg,xmmrm128,imm8 [rmi: 66 0f 3a 41 /r ib,u] SSE41
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DPPS xmmreg,xmmrm128,imm8 [rmi: 66 0f 3a 40 /r ib,u] SSE41
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EXTRACTPS rm32,xmmreg,imm8 [mri: 66 0f 3a 17 /r ib,u] SSE41
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EXTRACTPS reg64,xmmreg,imm8 [mri: o64 66 0f 3a 17 /r ib,u] SSE41,X86_64,LONG
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INSERTPS xmmreg,xmmrm32,imm8 [rmi: 66 0f 3a 21 /r ib,u] SSE41,SD
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INSERTPS xmmreg,xmmrm32,imm8 [rmi: 66 0f 3a 21 /r ib,u] SSE41
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MOVNTDQA xmmreg,mem128 [rm: 66 0f 38 2a /r] SSE41
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MPSADBW xmmreg,xmmrm128,imm8 [rmi: 66 0f 3a 42 /r ib,u] SSE41
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PACKUSDW xmmreg,xmmrm128 [rm: 66 0f 38 2b /r] SSE41
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53
x86/insns.pl
53
x86/insns.pl
@ -1,7 +1,7 @@
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#!/usr/bin/perl
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## --------------------------------------------------------------------------
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##
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## Copyright 1996-2017 The NASM Authors - All Rights Reserved
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## Copyright 1996-2020 The NASM Authors - All Rights Reserved
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## See the file AUTHORS included with the NASM distribution for
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## the specific copyright holders.
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##
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@ -444,7 +444,7 @@ sub format_insn($$$$$) {
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my $nd = 0;
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my ($num, $flagsindex);
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my @bytecode;
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my ($op, @ops, $opp, @opx, @oppx, @decos, @opevex);
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my ($op, @ops, @opsize, $opp, @opx, @oppx, @decos, @opevex);
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return (undef, undef) if $operands eq "ignore";
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@ -452,9 +452,11 @@ sub format_insn($$$$$) {
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$operands =~ s/\*//g;
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$operands =~ s/:/|colon,/g;
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@ops = ();
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@opsize = ();
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@decos = ();
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if ($operands ne 'void') {
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foreach $op (split(/,/, $operands)) {
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my $opsz = 0;
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@opx = ();
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@opevex = ();
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foreach $opp (split(/\|/, $op)) {
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@ -465,6 +467,7 @@ sub format_insn($$$$$) {
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if ($opp =~ s/(?<!\d)(8|16|32|64|80|128|256|512)$//) {
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push(@oppx, "bits$1");
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$opsz = $1 + 0;
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}
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$opp =~ s/^mem$/memory/;
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$opp =~ s/^memory_offs$/mem_offs/;
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@ -481,6 +484,7 @@ sub format_insn($$$$$) {
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}
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$op = join('|', @opx);
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push(@ops, $op);
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push(@opsize, $opsz);
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push(@decos, (@opevex ? join('|', @opevex) : '0'));
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}
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}
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@ -488,6 +492,7 @@ sub format_insn($$$$$) {
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$num = scalar(@ops);
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while (scalar(@ops) < $MAX_OPERANDS) {
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push(@ops, '0');
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push(@opsize, 0);
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push(@decos, '0');
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}
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$operands = join(',', @ops);
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@ -499,11 +504,14 @@ sub format_insn($$$$$) {
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}
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$decorators =~ tr/a-z/A-Z/;
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# Remember if we have an ARx flag
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my $arx = undef;
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# expand and uniqify the flags
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my %flags;
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foreach my $flag (split(',', $flags)) {
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next if ($flag eq '');
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if ($flag eq 'ND') {
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$nd = 1;
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} else {
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@ -514,6 +522,10 @@ sub format_insn($$$$$) {
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# These flags imply OBSOLETE
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$flags{'OBSOLETE'}++;
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}
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if ($flag =~ /^AR([0-9]+)$/) {
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$arx = $1+0;
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}
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}
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if ($codes =~ /evex\./) {
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@ -522,8 +534,41 @@ sub format_insn($$$$$) {
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$flags{'VEX'}++;
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}
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# Look for SM flags clearly inconsistent with operand bitsizes
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if ($flags{'SM'} || $flags{'SM2'}) {
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my $ssize = 0;
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my $e = $flags{'SM2'} ? 2 : $MAX_OPERANDS;
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for (my $i = 0; $i < $e; $i++) {
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next if (!$opsize[$i]);
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if (!$ssize) {
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$ssize = $opsize[$i];
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} elsif ($opsize[$i] != $ssize) {
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die "$fname:$line: inconsistent SM flag for argument $i\n";
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}
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}
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}
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# Look for Sx flags that can never match operand bitsizes. If the
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# intent is to never match (require explicit sizes), use the SX flag.
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# This doesn't apply to registers that pre-define specific sizes;
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# this should really be derived from include/opflags.h...
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my %sflags = ( 'SB' => 8, 'SW' => 16, 'SD' => 32, 'SQ' => 64,
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'SO' => 128, 'SY' => 256, 'SZ' => 512 );
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my $s = defined($arx) ? $arx : 0;
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my $e = defined($arx) ? $arx : $MAX_OPERANDS - 1;
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foreach my $sf (keys(%sflags)) {
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next if (!$flags{$sf});
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for (my $i = $s; $i <= $e; $i++) {
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if ($opsize[$i] && $ops[$i] !~ /\breg_(gpr|[cdts]reg)\b/) {
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die "$fname:$line: inconsistent $sf flag for argument $i ($ops[$i])\n"
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if ($opsize[$i] != $sflags{$sf});
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}
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}
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}
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$flagsindex = insns_flag_index(keys %flags);
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die "$fname:$line: error in flags $flags" unless (defined($flagsindex));
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die "$fname:$line: error in flags $flags\n" unless (defined($flagsindex));
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@bytecode = (decodify($codes, $relax), 0);
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push(@bytecode_list, [@bytecode]);
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