mirror of
https://github.com/netwide-assembler/nasm.git
synced 2025-03-19 18:00:23 +08:00
Add DY, YWORD, and the SY instruction flag
Add the DY instruction, YWORD keyword, and an SY marker for instruction sizes. Add a few more AVX sample instructions.
This commit is contained in:
H. Peter Anvin
parent
70a13f5a37
commit
dfb918047b
27
assemble.c
27
assemble.c
@ -119,6 +119,9 @@
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#include "regflags.c"
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#include "regvals.c"
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/* Initialized to zero by the C standard */
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static const uint8_t const_zero_buf[256];
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typedef struct {
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int sib_present; /* is a SIB byte necessary? */
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int bytes; /* # of bytes of offset needed */
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@ -168,6 +171,8 @@ static const char *size_name(int size)
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return "tword";
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case 16:
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return "oword";
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case 32:
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return "yword";
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default:
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return "???";
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}
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@ -294,6 +299,9 @@ int64_t assemble(int32_t segment, int64_t offset, int bits, uint32_t cp,
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case I_DO:
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wsize = 16;
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break;
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case I_DY:
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wsize = 32;
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break;
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default:
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break;
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}
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@ -318,7 +326,7 @@ int64_t assemble(int32_t segment, int64_t offset, int bits, uint32_t cp,
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OUT_RAWDATA, 1, NO_SEG, NO_SEG);
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}
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} else if (wsize > 8) {
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errfunc(ERR_NONFATAL, "integer supplied to a DT or DO"
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errfunc(ERR_NONFATAL, "integer supplied to a DT, DO or DY"
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" instruction");
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} else
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out(offset, segment, &e->offset,
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@ -333,8 +341,7 @@ int64_t assemble(int32_t segment, int64_t offset, int bits, uint32_t cp,
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if (align) {
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align = wsize - align;
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out(offset, segment,
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"\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0",
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out(offset, segment, const_zero_buf,
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OUT_RAWDATA, align, NO_SEG, NO_SEG);
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}
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offset += e->stringlen + align;
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@ -630,7 +637,8 @@ int64_t insn_size(int32_t segment, int64_t offset, int bits, uint32_t cp,
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if (instruction->opcode == I_DB || instruction->opcode == I_DW ||
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instruction->opcode == I_DD || instruction->opcode == I_DQ ||
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instruction->opcode == I_DT || instruction->opcode == I_DO) {
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instruction->opcode == I_DT || instruction->opcode == I_DO ||
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instruction->opcode == I_DY) {
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extop *e;
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int32_t isize, osize, wsize = 0; /* placate gcc */
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@ -654,6 +662,9 @@ int64_t insn_size(int32_t segment, int64_t offset, int bits, uint32_t cp,
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case I_DO:
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wsize = 16;
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break;
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case I_DY:
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wsize = 32;
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break;
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default:
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break;
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}
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@ -1483,7 +1494,7 @@ static void gencode(int32_t segment, int64_t offset, int bits,
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if (opx->segment == NO_SEG)
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errfunc(ERR_NONFATAL, "value referenced by FAR is not"
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" relocatable");
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data = 0L;
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data = 0;
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out(offset, segment, &data, OUT_ADDRESS, 2,
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outfmt->segbase(1 + opx->segment),
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opx->wrt);
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@ -1957,6 +1968,9 @@ static int matches(const struct itemplate *itemp, insn * instruction, int bits)
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case IF_SO:
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size[i] = BITS128;
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break;
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case IF_SY:
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size[i] = BITS256;
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break;
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case IF_SZ:
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switch (bits) {
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case 16:
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@ -1991,6 +2005,9 @@ static int matches(const struct itemplate *itemp, insn * instruction, int bits)
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case IF_SO:
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asize = BITS128;
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break;
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case IF_SY:
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asize = BITS256;
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break;
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case IF_SZ:
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switch (bits) {
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case 16:
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3
disasm.c
3
disasm.c
@ -1331,6 +1331,9 @@ int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize,
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if (t & BITS128)
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slen +=
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snprintf(output + slen, outbufsize - slen, "oword ");
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if (t & BITS256)
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slen +=
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snprintf(output + slen, outbufsize - slen, "yword ");
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if (t & FAR)
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slen += snprintf(output + slen, outbufsize - slen, "far ");
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if (t & NEAR)
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42
insns.dat
42
insns.dat
@ -25,12 +25,14 @@ DD ignore ignore ignore
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DQ ignore ignore ignore
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DT ignore ignore ignore
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DO ignore ignore ignore
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DY ignore ignore ignore
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RESB imm \340 8086
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RESW ignore ignore ignore
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RESD ignore ignore ignore
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RESQ ignore ignore ignore
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REST ignore ignore ignore
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RESO ignore ignore ignore
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RESY ignore ignore ignore
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;# Conventional instructions
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AAA void \1\x37 8086,NOLONG
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@ -2023,22 +2025,30 @@ PFRCP mmxreg,mmxrm \323\2\x0F\x0F\110\1\x86 PENT,3DNOW,SQ,CYRIX
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PFRSQRT mmxreg,mmxrm \323\2\x0F\x0F\110\1\x87 PENT,3DNOW,SQ,CYRIX
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;# Intel AVX instructions
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VPERMILTD2PS xmmreg,xmmreg,xmmrm,xmmreg [rvms: vex.nds.128.66.0f3a.w0 48 /r /is4=0] AVX,SANDYBRIDGE
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VPERMILTD2PS xmmreg,xmmreg,xmmreg,xmmrm [rvsm: vex.nds.128.66.0f3a.w1 48 /r /is4=0] AVX,SANDYBRIDGE
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VPERMILTD2PS ymmreg,ymmreg,ymmrm,ymmreg [rvms: vex.nds.256.66.0f3a.w0 48 /r /is4=0] AVX,SANDYBRIDGE
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VPERMILTD2PS ymmreg,ymmreg,ymmreg,ymmrm [rvsm: vex.nds.256.66.0f3a.w1 48 /r /is4=0] AVX,SANDYBRIDGE
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VPERMILMO2PS xmmreg,xmmreg,xmmrm,xmmreg [rvms: vex.nds.128.66.0f3a.w0 48 /r /is4=2] AVX,SANDYBRIDGE
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VPERMILMO2PS xmmreg,xmmreg,xmmreg,xmmrm [rvsm: vex.nds.128.66.0f3a.w1 48 /r /is4=2] AVX,SANDYBRIDGE
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VPERMILMO2PS ymmreg,ymmreg,ymmrm,ymmreg [rvms: vex.nds.256.66.0f3a.w0 48 /r /is4=2] AVX,SANDYBRIDGE
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VPERMILMO2PS ymmreg,ymmreg,ymmreg,ymmrm [rvsm: vex.nds.256.66.0f3a.w1 48 /r /is4=2] AVX,SANDYBRIDGE
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VPERMILMZ2PS xmmreg,xmmreg,xmmrm,xmmreg [rvms: vex.nds.128.66.0f3a.w0 48 /r /is4=3] AVX,SANDYBRIDGE
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VPERMILMZ2PS xmmreg,xmmreg,xmmreg,xmmrm [rvsm: vex.nds.128.66.0f3a.w1 48 /r /is4=3] AVX,SANDYBRIDGE
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VPERMILMZ2PS ymmreg,ymmreg,ymmrm,ymmreg [rvms: vex.nds.256.66.0f3a.w0 48 /r /is4=3] AVX,SANDYBRIDGE
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VPERMILMZ2PS ymmreg,ymmreg,ymmreg,ymmrm [rvsm: vex.nds.256.66.0f3a.w1 48 /r /is4=3] AVX,SANDYBRIDGE
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VPERMIL2PS xmmreg,xmmreg,xmmrm,xmmreg,imm [rvmsi: vex.nds.128.66.0f3a.w0 48 /r /is4] AVX,SANDYBRIDGE
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VPERMIL2PS xmmreg,xmmreg,xmmreg,xmmrm,imm [rvsmi: vex.nds.128.66.0f3a.w1 48 /r /is4] AVX,SANDYBRIDGE
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VPERMIL2PS ymmreg,ymmreg,ymmrm,ymmreg,imm [rvmsi: vex.nds.256.66.0f3a.w0 48 /r /is4] AVX,SANDYBRIDGE
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VPERMIL2PS ymmreg,ymmreg,ymmreg,ymmrm,imm [rvsmi: vex.nds.256.66.0f3a.w1 48 /r /is4] AVX,SANDYBRIDGE
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VADDPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 58 /r] AVX,SANDYBRIDGE,SO
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VADDPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f 58 /r] AVX,SANDYBRIDGE,SY
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VADDPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 58 /r] AVX,SANDYBRIDGE,SO
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VADDPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f 58 /r] AVX,SANDYBRIDGE,SY
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VADDPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f 58 /r] AVX,SANDYBRIDGE,SO
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VADDPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f 58 /r] AVX,SANDYBRIDGE,SY
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VADDPS xmmreg,xmmrm [r+vm: vex.nds.128.0f 58 /r] AVX,SANDYBRIDGE,SO
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VADDPS ymmreg,ymmrm [r+vm: vex.nds.256.0f 58 /r] AVX,SANDYBRIDGE,SY
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VPERMILTD2PS xmmreg,xmmreg,xmmrm,xmmreg [rvms: vex.nds.128.66.0f3a.w0 48 /r /is4=0] AVX,SANDYBRIDGE,SO
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VPERMILTD2PS xmmreg,xmmreg,xmmreg,xmmrm [rvsm: vex.nds.128.66.0f3a.w1 48 /r /is4=0] AVX,SANDYBRIDGE,SO
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VPERMILTD2PS ymmreg,ymmreg,ymmrm,ymmreg [rvms: vex.nds.256.66.0f3a.w0 48 /r /is4=0] AVX,SANDYBRIDGE,SY
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VPERMILTD2PS ymmreg,ymmreg,ymmreg,ymmrm [rvsm: vex.nds.256.66.0f3a.w1 48 /r /is4=0] AVX,SANDYBRIDGE,SY
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VPERMILMO2PS xmmreg,xmmreg,xmmrm,xmmreg [rvms: vex.nds.128.66.0f3a.w0 48 /r /is4=2] AVX,SANDYBRIDGE,SO
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VPERMILMO2PS xmmreg,xmmreg,xmmreg,xmmrm [rvsm: vex.nds.128.66.0f3a.w1 48 /r /is4=2] AVX,SANDYBRIDGE,SO
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VPERMILMO2PS ymmreg,ymmreg,ymmrm,ymmreg [rvms: vex.nds.256.66.0f3a.w0 48 /r /is4=2] AVX,SANDYBRIDGE,SY
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VPERMILMO2PS ymmreg,ymmreg,ymmreg,ymmrm [rvsm: vex.nds.256.66.0f3a.w1 48 /r /is4=2] AVX,SANDYBRIDGE,SY
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VPERMILMZ2PS xmmreg,xmmreg,xmmrm,xmmreg [rvms: vex.nds.128.66.0f3a.w0 48 /r /is4=3] AVX,SANDYBRIDGE,SO
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VPERMILMZ2PS xmmreg,xmmreg,xmmreg,xmmrm [rvsm: vex.nds.128.66.0f3a.w1 48 /r /is4=3] AVX,SANDYBRIDGE,SO
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VPERMILMZ2PS ymmreg,ymmreg,ymmrm,ymmreg [rvms: vex.nds.256.66.0f3a.w0 48 /r /is4=3] AVX,SANDYBRIDGE,SY
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VPERMILMZ2PS ymmreg,ymmreg,ymmreg,ymmrm [rvsm: vex.nds.256.66.0f3a.w1 48 /r /is4=3] AVX,SANDYBRIDGE,SY
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VPERMIL2PS xmmreg,xmmreg,xmmrm,xmmreg,imm [rvmsi: vex.nds.128.66.0f3a.w0 48 /r /is4] AVX,SANDYBRIDGE,SO
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VPERMIL2PS xmmreg,xmmreg,xmmreg,xmmrm,imm [rvsmi: vex.nds.128.66.0f3a.w1 48 /r /is4] AVX,SANDYBRIDGE,SO
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VPERMIL2PS ymmreg,ymmreg,ymmrm,ymmreg,imm [rvmsi: vex.nds.256.66.0f3a.w0 48 /r /is4] AVX,SANDYBRIDGE,SY
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VPERMIL2PS ymmreg,ymmreg,ymmreg,ymmrm,imm [rvsmi: vex.nds.256.66.0f3a.w1 48 /r /is4] AVX,SANDYBRIDGE,SY
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;# VIA (Centaur) security instructions
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XSTORE void \360\3\x0F\xA7\xC0 PENT,CYRIX
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3
insns.h
3
insns.h
@ -75,7 +75,8 @@ extern const uint8_t nasm_bytecodes[];
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#define IF_SD 0x0000000CUL /* unsized operands can't be non-dword */
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#define IF_SQ 0x00000010UL /* unsized operands can't be non-qword */
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#define IF_SO 0x00000014UL /* unsized operands can't be non-oword */
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#define IF_SZ 0x00000018UL /* unsized operands must match the bitsize */
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#define IF_SY 0x00000018UL /* unsized operands can't be non-yword */
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#define IF_SZ 0x0000001CUL /* unsized operands must match the bitsize */
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#define IF_SMASK 0x0000001CUL /* mask for unsized argument size */
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#define IF_AR0 0x00000020UL /* SB, SW, SD applies to argument 0 */
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#define IF_AR1 0x00000040UL /* SB, SW, SD applies to argument 1 */
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13
nasm.c
13
nasm.c
@ -1486,6 +1486,16 @@ static void assemble_file(char *fname)
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TYS_ELEMENTS(output_ins.oprs[0].
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offset) | TY_TBYTE;
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break;
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case I_RESO:
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typeinfo =
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TYS_ELEMENTS(output_ins.oprs[0].
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offset) | TY_OWORD;
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break;
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case I_RESY:
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typeinfo =
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TYS_ELEMENTS(output_ins.oprs[0].
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offset) | TY_YWORD;
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break;
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case I_DB:
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typeinfo |= TY_BYTE;
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break;
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@ -1507,6 +1517,9 @@ static void assemble_file(char *fname)
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case I_DO:
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typeinfo |= TY_OWORD;
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break;
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case I_DY:
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typeinfo |= TY_YWORD;
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break;
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default:
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typeinfo = TY_LABEL;
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12
nasm.h
12
nasm.h
@ -374,7 +374,7 @@ enum {
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*
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* The bits are assigned as follows:
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*
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* Bits 0-7, 29: sizes
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* Bits 0-7, 23, 29: sizes
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* 0: 8 bits (BYTE)
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* 1: 16 bits (WORD)
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* 2: 32 bits (DWORD)
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@ -383,6 +383,7 @@ enum {
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* 5: FAR
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* 6: NEAR
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* 7: SHORT
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* 23: 256 bits (YWORD)
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* 29: 128 bits (OWORD)
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*
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* Bits 8-11 modifiers
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@ -432,11 +433,10 @@ enum {
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* 18: BYTENESS32 (-128..127)
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* 19: BYTENESS64 (-128..127)
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*
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* Bits 20-26: register classes
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* Bits 20-22, 24-27: register classes
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* 20: REG_CDT (CRx, DRx, TRx)
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* 21: RM_GPR (REG_GPR) (integer register)
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* 22: REG_SREG
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* 23: IP_REG (RIP or EIP) [unused]
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* 24: FPUREG
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* 25: RM_MMX (MMXREG)
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* 26: RM_XMM (XMMREG)
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@ -459,12 +459,13 @@ typedef uint32_t opflags_t;
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#define BITS64 0x00000008U /* x64 and FPU only */
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#define BITS80 0x00000010U /* FPU only */
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#define BITS128 0x20000000U
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#define BITS256 0x00800000U
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#define FAR 0x00000020U /* grotty: this means 16:16 or */
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/* 16:32, like in CALL/JMP */
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#define NEAR 0x00000040U
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#define SHORT 0x00000080U /* and this means what it says :) */
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#define SIZE_MASK 0x200000FFU /* all the size attributes */
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#define SIZE_MASK 0x208000FFU /* all the size attributes */
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/* Modifiers */
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#define MODIFIER_MASK 0x00000f00U
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@ -955,6 +956,7 @@ struct dfmt {
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#define TY_QWORD 0x30
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#define TY_TBYTE 0x38
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#define TY_OWORD 0x40
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#define TY_YWORD 0x48
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#define TY_COMMON 0xE0
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#define TY_SEG 0xE8
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#define TY_EXTERN 0xF0
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@ -975,7 +977,7 @@ enum special_tokens {
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SPECIAL_ENUM_START = PREFIX_ENUM_LIMIT,
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S_ABS = SPECIAL_ENUM_START,
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S_BYTE, S_DWORD, S_FAR, S_LONG, S_NEAR, S_NOSPLIT,
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S_OWORD, S_QWORD, S_REL, S_SHORT, S_STRICT, S_TO, S_TWORD, S_WORD,
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S_OWORD, S_QWORD, S_REL, S_SHORT, S_STRICT, S_TO, S_TWORD, S_WORD, S_YWORD,
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SPECIAL_ENUM_LIMIT
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};
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14
parser.c
14
parser.c
@ -322,6 +322,7 @@ restart_parse:
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if (result->opcode == I_RESB || result->opcode == I_RESW ||
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result->opcode == I_RESD || result->opcode == I_RESQ ||
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result->opcode == I_REST || result->opcode == I_RESO ||
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result->opcode == I_RESY ||
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result->opcode == I_EQU || result->opcode == I_INCBIN) {
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critical = (pass0 < 2 ? 1 : 2);
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@ -331,7 +332,7 @@ restart_parse:
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if (result->opcode == I_DB || result->opcode == I_DW ||
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result->opcode == I_DD || result->opcode == I_DQ ||
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result->opcode == I_DT || result->opcode == I_DO ||
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result->opcode == I_INCBIN) {
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result->opcode == I_DY || result->opcode == I_INCBIN) {
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extop *eop, **tail = &result->eops, **fixptr;
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int oper_num = 0;
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@ -560,6 +561,11 @@ restart_parse:
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result->oprs[operand].type |= BITS128;
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setsize = 1;
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break;
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case S_YWORD:
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if (!setsize)
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result->oprs[operand].type |= BITS256;
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setsize = 1;
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break;
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case S_TO:
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result->oprs[operand].type |= TO;
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break;
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@ -857,7 +863,7 @@ while (operand < MAX_OPERANDS)
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result->oprs[operand++].type = 0;
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/*
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* Transform RESW, RESD, RESQ, REST, RESO into RESB.
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* Transform RESW, RESD, RESQ, REST, RESO, RESY into RESB.
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*/
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switch (result->opcode) {
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case I_RESW:
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@ -880,6 +886,10 @@ while (operand < MAX_OPERANDS)
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result->opcode = I_RESB;
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result->oprs[0].offset *= 16;
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break;
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case I_RESY:
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result->opcode = I_RESB;
|
||||
result->oprs[0].offset *= 32;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
@ -1744,9 +1744,9 @@ static void undef_smacro(Context *ctx, const char *mname)
|
||||
*/
|
||||
static int parse_size(const char *str) {
|
||||
static const char *size_names[] =
|
||||
{ "byte", "dword", "oword", "qword", "tword", "word" };
|
||||
{ "byte", "dword", "oword", "qword", "tword", "word", "yword" };
|
||||
static const int sizes[] =
|
||||
{ 0, 1, 4, 16, 8, 10, 2 };
|
||||
{ 0, 1, 4, 16, 8, 10, 2, 32 };
|
||||
|
||||
return sizes[bsii(str, size_names, elements(size_names))+1];
|
||||
}
|
||||
|
||||
@ -35,6 +35,7 @@ strict
|
||||
to
|
||||
tword
|
||||
word
|
||||
yword
|
||||
|
||||
% TOKEN_FLOAT, 0, 0
|
||||
__infinity__
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user