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https://github.com/netwide-assembler/nasm.git
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More work on bytecode compiler (not finished yet...)
More work on the bytecode compiler. Not all useful bytecodes are implemented yet, however.
This commit is contained in:
H. Peter Anvin
parent
4f0a3e64ee
commit
dfa2a842bd
152
insns.pl
152
insns.pl
@ -48,7 +48,7 @@ while (<F>) {
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next;
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}
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@fields = ($1, $2, $3, $4);
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($formatted, $nd) = format(@fields);
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($formatted, $nd) = format_insn(@fields);
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if ($formatted) {
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$insns++;
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$aname = "aa_$fields[0]";
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@ -105,7 +105,7 @@ if ( !defined($output) || $output eq 'b') {
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print STDERR "Writing insnsb.c...\n";
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open B, ">insnsb.c";
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print B "/* This file auto-generated from insns.dat by insns.pl" .
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" - don't edit it */\n\n";
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@ -127,7 +127,7 @@ if ( !defined($output) || $output eq 'b') {
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close B;
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}
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if ( !defined($output) || $output eq 'a' ) {
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print STDERR "Writing insnsa.c...\n";
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@ -284,7 +284,7 @@ if ( !defined($output) || $output eq 'n' ) {
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printf STDERR "Done: %d instructions\n", $insns;
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sub format(@) {
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sub format_insn(@) {
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my ($opcode, $operands, $codes, $flags) = @_;
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my $num, $nd = 0;
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my @bytecode;
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@ -485,20 +485,21 @@ sub startseq($) {
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#
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# r = register field in the modr/m
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# m = modr/m
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# v = VEX "v" field or DREX "src" field
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# v = VEX "v" field
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# d = DREX "dst" field
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# i = immediate
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# z = register field of is4 or imz2 field
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#
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# s = register field of is4 or imz2 field
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#
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sub byte_code_compile($) {
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my($str) = @_;
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my $opr;
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my $opc;
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my $opc;
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my @codes = ();
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my $litix = undef;
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my %oppos = ();
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my $i;
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my $op, $oq;
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if ($str =~ /^(\S*)\:\s*(.*\S)\s*$/) {
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$opr = "\L$1";
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$opc = "\L$2";
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@ -506,13 +507,47 @@ sub byte_code_compile($) {
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$opr = '';
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$opc = $str;
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}
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for ($i = 0; $i < length($opr); $i++) {
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$oppos{substr($opr,$i,1)} = $i;
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}
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$prefix_ok = 1;
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foreach $op (split($opc)) {
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if ($op =~ /^[0-9a-f]{2}$/) {
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if ($op eq 'o16') {
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push(@codes, 0320);
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} elsif ($op eq 'o32') {
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push(@codes, 0321);
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} elsif ($op eq 'o64') { # 64-bit operand size requiring REX.W
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push(@codes, 0324);
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} elsif ($op eq 'o64i') { # Implied 64-bit operand size (no REX.W)
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push(@codes, 0323);
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} elsif ($op eq 'a16') {
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push(@codes, 0310);
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} elsif ($op eq 'a32') {
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push(@codes, 0311);
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} elsif ($op eq 'a64') {
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push(@codes, 0313);
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} elsif ($op eq '!osp') {
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push(@codes, 0364);
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} elsif ($op eq '!asp') {
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push(@codes, 0365);
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} elsif ($op eq 'rex.l') {
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push(@codes, 0334);
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} elsif ($op eq 'repe') {
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push(@codes, 0335);
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} elsif ($prefix_ok && $op =~ /^(66|f2|f3|np)$/) {
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# 66/F2/F3 prefix used as an opcode extension, or np = no prefix
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if ($op eq '66') {
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push(@codes, 0366, 0331);
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} elsif ($op eq 'f2') {
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push(@codes, 0332, 0364);
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} elsif ($op eq 'f3') {
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push(@codes, 0333, 0364);
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} else {
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push(@codes, 0331, 0364);
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}
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} elsif ($op =~ /^[0-9a-f]{2}$/) {
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if (defined($litix) && $litix+$codes[$litix]+1 == scalar @codes) {
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$codes[$litix]++;
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push(@codes, hex $op);
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@ -520,17 +555,20 @@ sub byte_code_compile($) {
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$litix = scalar(@codes);
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push(@codes, 01, hex $op);
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}
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$prefix_ok = 0;
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} elsif ($op eq '/r') {
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if (!defined($oppos{'r'}) || !defined($oppos{'m'})) {
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die "$0: $line: $op requires r and m operands\n";
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}
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push(@codes, 0100 + ($oppos{'m'} << 3) + $oppos{'r'});
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$prefix_ok = 0;
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} elsif ($op =~ m:^/([0-7])$:) {
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if (!defined($oppos{'m'})) {
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die "$0: $line: $op requires m operand\n";
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}
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push(@codes, 0200 + ($oppos{'m'} << 3) + $1;
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} elsif ($op =~ /^vex\./) {
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push(@codes, 0200 + ($oppos{'m'} << 3) + $1);
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$prefix_ok = 0;
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} elsif ($op =~ /^vex(|\..*)$/) {
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my ($m,$w,$l,$p) = (undef,2,undef,0);
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foreach $oq (split(/\./, $op)) {
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if ($oq eq 'vex') {
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@ -568,4 +606,90 @@ sub byte_code_compile($) {
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}
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push(@codes, defined($oppos{'v'}) ? 0260+$oppos{'v'} : 0270,
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$m, ($w << 3)+($l << 2)+$p);
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}
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$prefix_ok = 0;
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} elsif ($op =~ /^drex(|..*)$/) {
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my ($oc0) = (0);
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foreach $oq (split(/\./, $op)) {
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if ($oq eq 'drex') {
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#prefix
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} elsif ($oq eq 'oc0') {
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$oc0 = 1;
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} else {
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die "$0: $line: undefined DREX subcode: $oq\n";
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}
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}
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if (!defined($oppos{'d'})) {
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die "$0: $line: DREX without a 'd' operand\n";
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}
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push(@codes, 0160+$oppos{'d'}+($oc0 ? 4 : 0));
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} elsif ($op =~ /^(imm8|imm8u|imm8s|imm16|imm32|imm32s|imm64|imm|immx|rel8|rel16|rel32|rel64|rel|seg|simm16|simm32|simm32s)$/) {
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if (!defined($oppos{'i'})) {
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die "$0: $op without 'i' operand\n";
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}
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if ($op eq 'imm8s') {
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push(@codes, 014+$oppos{'i'});
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} elsif ($op eq 'imm8') {
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push(@codes, 020+$oppos{'i'});
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} elsif ($op eq 'imm8u') {
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push(@codes, 024+$oppos{'i'});
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} elsif ($op eq 'imm16') {
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push(@codes, 030+$oppos{'i'});
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} elsif ($op eq 'imm') { # 16 or 32 bit operand
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push(@codes, 034+$oppos{'i'});
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} elsif ($op eq 'imm32') {
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push(@codes, 040+$oppos{'i'});
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} elsif ($op eq 'immx') { # 16, 32 or 64 bit operand
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push(@codes, 044+$oppos{'i'});
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} elsif ($op eq 'rel8') {
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push(@codes, 050+$oppos{'i'});
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} elsif ($op eq 'rel64') {
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push(@codes, 054+$oppos{'i'});
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} elsif ($op eq 'rel16') {
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push(@codes, 060+$oppos{'i'});
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} elsif ($op eq 'rel') { # 16 or 32 bit relative operand
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push(@codes, 064+$oppos{'i'});
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} elsif ($op eq 'rel32') {
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push(@codes, 070+$oppos{'i'});
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} elsif ($op eq 'seg') {
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push(@codes, 074+$oppos{'i'});
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} elsif ($op eq 'simm16') { # imm16 that can be bytified
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if (!defined($s_pos)) {
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die "$0: $line: $op without a +s byte\n";
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}
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$codes[$s_pos] += 0144;
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push(@codes, 0140+$oppos{'i'});
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} elsif ($op eq 'simm32') { # imm32 that can be bytified
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if (!defined($s_pos)) {
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die "$0: $line: $op without a +s byte\n";
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}
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$codes[$s_pos] += 0154;
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push(@codes, 0150+$oppos{'i'});
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} elsif ($op eq 'simm32s') {
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# imm32 that can be bytified, sign extended
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if (!defined($s_pos)) {
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die "$0: $line: $op without a +s byte\n";
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}
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$codes[$s_pos] += 0154;
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push(@codes, 0250+$oppos{'i'});
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}
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$prefix_ok = 0;
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} elsif ($op =~ /^([0-9a-f]{2})\+s$/) {
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if (!defined($oppos{'i'})) {
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die "$0: $op without 'i' operand\n";
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}
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$s_pos = scalar @codes;
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push(@codes, $oppos{'i'}, hex $1);
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$prefix_ok = 0;
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} elsif ($op =~ /^([0-9a-f]{2})\+c$/) {
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push(@codes, 0330, hex $1);
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$prefix_ok = 0;
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} elsif ($op =~ /^\\([0-7]+|x[0-9a-f]{2})$/) {
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# Escape to enter literal bytecodes
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push(@codes, oct $1);
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} else {
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die "$0: unknown operation: $op\n";
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}
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}
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return @codes;
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}
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