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Sync to public Intel EAS version 021.

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* http://www.intel.com/software/isa

   * Signed-off-by: Mark Charney <mark.charney@intel.com>
This commit is contained in:
Mark Charney 2014-10-09 13:45:17 -04:00 committed by Jim Kukunas
parent 8a076f4260
commit dcaef4b095
6 changed files with 1649 additions and 651 deletions
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34
assemble.c
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@ -2106,6 +2106,31 @@ done:
return merr;
}
static uint8_t get_broadcast_num(opflags_t opflags, opflags_t brsize)
{
opflags_t opsize = opflags & SIZE_MASK;
uint8_t brcast_num;
/*
* Due to discontinuity between BITS64 and BITS128 (BITS80),
* this cannot be a simple arithmetic calculation.
*/
if (brsize > BITS64)
errfunc(ERR_FATAL,
"size of broadcasting element is greater than 64 bits");
switch (opsize) {
case BITS64:
brcast_num = BITS64 / brsize;
break;
default:
brcast_num = (opsize / BITS128) * (BITS64 / brsize) * 2;
break;
}
return brcast_num;
}
static enum match_result matches(const struct itemplate *itemp,
insn *instruction, int bits)
{
@ -2255,8 +2280,7 @@ static enum match_result matches(const struct itemplate *itemp,
if (deco_brsize) {
template_opsize = (deco_brsize == BR_BITS32 ? BITS32 : BITS64);
/* calculate the proper number : {1to<brcast_num>} */
brcast_num = (itemp->opd[i] & SIZE_MASK) / BITS128 *
BITS64 / template_opsize * 2;
brcast_num = get_broadcast_num(itemp->opd[i], template_opsize);
} else {
template_opsize = 0;
}
@ -2279,12 +2303,12 @@ static enum match_result matches(const struct itemplate *itemp,
}
} else if (is_broadcast &&
(brcast_num !=
(8U << ((deco & BRNUM_MASK) >> BRNUM_SHIFT)))) {
(2U << ((deco & BRNUM_MASK) >> BRNUM_SHIFT)))) {
/*
* broadcasting opsize matches but the number of repeated memory
* element does not match.
* if 64b double precision float is broadcasted to zmm (512b),
* broadcasting decorator must be {1to8}.
* if 64b double precision float is broadcasted to ymm (256b),
* broadcasting decorator must be {1to4}.
*/
return MERR_BRNUMMISMATCH;
}

5
insns-iflags.pl
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@ -131,6 +131,11 @@ my %insns_flag_bit = (
"MPX" => [ 68 ,"MPX"],
"SHA" => [ 69 ,"SHA"],
"PREFETCHWT1" => [ 70 ,"PREFETCHWT1"],
"AVX512VL" => [ 71, "AVX-512 Vector Length Orthogonality"],
"AVX512DQ" => [ 72, "AVX-512 Dword and Qword"],
"AVX512BW" => [ 73, "AVX-512 Byte and Word"],
"AVX512IFMA" => [ 74, "AVX-512 IFMA instructions"],
"AVX512VBMI" => [ 75, "AVX-512 VBMI instructions"],
"VEX" => [ 94, "VEX or XOP encoded instruction"],
"EVEX" => [ 95, "EVEX encoded instruction"],

2247
insns.dat
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File diff suppressed because it is too large Load Diff

10
nasm.h
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@ -1042,7 +1042,9 @@ enum special_tokens {
enum decorator_tokens {
DECORATOR_ENUM_START = SPECIAL_ENUM_LIMIT,
BRC_1TO8 = DECORATOR_ENUM_START,
BRC_1TO2 = DECORATOR_ENUM_START,
BRC_1TO4,
BRC_1TO8,
BRC_1TO16,
BRC_RN,
BRC_RD,
@ -1147,8 +1149,10 @@ enum decorator_tokens {
#define BRNUM_MASK OP_GENMASK(BRNUM_BITS, BRNUM_SHIFT)
#define VAL_BRNUM(val) OP_GENVAL(val, BRNUM_BITS, BRNUM_SHIFT)
#define BR_1TO8 VAL_BRNUM(0)
#define BR_1TO16 VAL_BRNUM(1)
#define BR_1TO2 VAL_BRNUM(0)
#define BR_1TO4 VAL_BRNUM(1)
#define BR_1TO8 VAL_BRNUM(2)
#define BR_1TO16 VAL_BRNUM(3)
#define MASK OPMASK_MASK /* Opmask (k1 ~ 7) can be used */
#define Z Z_MASK

2
parser.c
View File

@ -951,7 +951,7 @@ is_expression:
*/
if (tokval.t_flag & TFLAG_BRDCAST) {
brace_flags |= GEN_BRDCAST(0) |
VAL_BRNUM(tokval.t_integer - BRC_1TO8);
VAL_BRNUM(tokval.t_integer - BRC_1TO2);
i = stdscan(NULL, &tokval);
} else if (i == TOKEN_OPMASK) {
brace_flags |= VAL_OPMASK(nasm_regvals[tokval.t_integer]);

2
tokens.dat
View File

@ -111,6 +111,8 @@ seg
wrt
% TOKEN_DECORATOR, 0, TFLAG_BRC | TFLAG_BRDCAST , BRC_1TO{1to*}
1to2
1to4
1to8
1to16