mirror of
https://github.com/netwide-assembler/nasm.git
synced 2025-01-30 16:41:05 +08:00
First cut at AVX machinery.
First cut at AVX machinery support. The only instruction implemented is VPERMIL2PS, and it's probably buggy. I'm checking this in with the hope that other people can start helping out with (a) testing this, and (b) adding instructions. NDISASM support is not there yet.
This commit is contained in:
H. Peter Anvin
parent
7117e80702
commit
d85d250fa2
119
assemble.c
119
assemble.c
@ -48,11 +48,25 @@
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* kindly to a zero byte in the _middle_ of a compile time
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* string constant, so I had to put this hack in.)
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* \171 - placement of DREX suffix in the absence of an EA
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* \172\ab - the register number from operand a in bits 7..4, with
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* the 4-bit immediate from operand b in bits 0..3.
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* \2ab - a ModRM, calculated on EA in operand a, with the spare
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* field equal to digit b.
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* \250..\253 - same as \150..\153, except warn if the 64-bit operand
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* is not equal to the truncated and sign-extended 32-bit
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* operand; used for 32-bit immediates in 64-bit mode.
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* \260..\263 - this instruction uses VEX rather than REX, with the
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* V field taken from operand 0..3.
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* \270 - this instruction uses VEX rather than REX, with the
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* V field set to 1111b.
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*
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* VEX prefixes are followed by the sequence:
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* \1mm\1wp where mm is the M field; and wp is:
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* 01 0ww lpp
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* ww = 0 for W = 0
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* ww = 1 for W = 1
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* ww = 2 for W used as REX.W
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*
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* \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
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* \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
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* \312 - (disassembler only) marker on LOOP, LOOPxx instructions.
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@ -190,7 +204,7 @@ static void out(int64_t offset, int32_t segto, const void *data,
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errfunc(ERR_PANIC, "OUT_ADDRESS with size > 8");
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return;
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}
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WRITEADDR(q, *(int64_t *)data, size);
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data = p;
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type = OUT_RAWDATA;
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@ -964,7 +978,7 @@ static int64_t calcsize(int32_t segment, int64_t offset, int bits,
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case 0163:
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length++;
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ins->rex |= REX_D;
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ins->drexdst = regval(&ins->oprs[c & 3]);
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ins->drexdst = regval(opx);
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break;
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case 0164:
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case 0165:
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@ -972,19 +986,40 @@ static int64_t calcsize(int32_t segment, int64_t offset, int bits,
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case 0167:
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length++;
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ins->rex |= REX_D|REX_OC;
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ins->drexdst = regval(&ins->oprs[c & 3]);
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ins->drexdst = regval(opx);
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break;
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case 0170:
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length++;
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break;
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case 0171:
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break;
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case 0172:
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codes++;
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length++;
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break;
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case 0250:
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case 0251:
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case 0252:
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case 0253:
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length += is_sbyte64(ins, c & 3) ? 1 : 4;
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break;
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case 0260:
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case 0261:
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case 0262:
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case 0263:
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length += 2;
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ins->rex |= REX_V;
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ins->drexdst = regval(opx);
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ins->vex_m = *codes++;
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ins->vex_wlp = *codes++;
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break;
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case 0270:
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length += 2;
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ins->rex |= REX_V;
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ins->drexdst = 0;
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ins->vex_m = *codes++;
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ins->vex_wlp = *codes++;
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break;
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case 0300:
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case 0301:
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case 0302:
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@ -1093,12 +1128,40 @@ static int64_t calcsize(int32_t segment, int64_t offset, int bits,
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ins->rex &= rex_mask;
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if (ins->rex & REX_D) {
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if (ins->rex & REX_V) {
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int bad32 = REX_R|REX_W|REX_X|REX_B;
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if (ins->rex & REX_H) {
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errfunc(ERR_NONFATAL, "cannot use high register in vex instruction");
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return -1;
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}
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switch (ins->vex_wlp & 030) {
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case 000:
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ins->rex &= ~REX_W;
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break;
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case 010:
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ins->rex |= REX_W;
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bad32 &= ~REX_W;
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break;
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default:
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/* Follow REX_W */
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break;
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}
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if (bits != 64 && ((ins->rex & bad32) || ins->drexdst > 7)) {
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errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
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return -1;
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}
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if (ins->vex_m != 1 || (ins->rex & (REX_W|REX_R|REX_B)))
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length += 3;
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else
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length += 2;
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} else if (ins->rex & REX_D) {
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if (ins->rex & REX_H) {
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errfunc(ERR_NONFATAL, "cannot use high register in drex instruction");
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return -1;
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}
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if (bits != 64 && ((ins->rex & (REX_W|REX_X|REX_B)) ||
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if (bits != 64 && ((ins->rex & (REX_R|REX_W|REX_X|REX_B)) ||
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ins->drexdst > 7)) {
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errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
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return -1;
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@ -1126,7 +1189,7 @@ static int64_t calcsize(int32_t segment, int64_t offset, int bits,
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}
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#define EMIT_REX() \
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if (!(ins->rex & REX_D) && (ins->rex & REX_REAL) && (bits == 64)) { \
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if (!(ins->rex & (REX_D|REX_V)) && (ins->rex & REX_REAL) && (bits == 64)) { \
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ins->rex = (ins->rex & REX_REAL)|REX_P; \
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out(offset, segment, &ins->rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG); \
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ins->rex = 0; \
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@ -1507,6 +1570,26 @@ static void gencode(int32_t segment, int64_t offset, int bits,
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offset++;
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break;
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case 0172:
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c = *codes++;
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opx = &ins->oprs[c >> 3];
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bytes[0] = regvals[opx->basereg] << 4;
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opx = &ins->oprs[c & 7];
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if (opx->segment != NO_SEG || opx->wrt != NO_SEG) {
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errfunc(ERR_NONFATAL,
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"non-absolute expression not permitted as argument %d",
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c & 7);
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} else {
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if (opx->offset & ~15) {
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errfunc(ERR_WARNING | ERR_WARN_NOV,
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"four-bit argument exceeds bounds");
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}
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bytes[0] |= opx->offset & 15;
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}
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out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
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offset++;
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break;
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case 0250:
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case 0251:
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case 0252:
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@ -1525,6 +1608,28 @@ static void gencode(int32_t segment, int64_t offset, int bits,
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}
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break;
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case 0260:
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case 0261:
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case 0262:
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case 0263:
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case 0270:
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codes += 2;
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if (ins->vex_m != 1 || (ins->rex & (REX_W|REX_X|REX_B))) {
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bytes[0] = 0xc4;
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bytes[1] = ins->vex_m | ((ins->rex & 7) << 5);
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bytes[2] = ((ins->rex & REX_W) << (7-3)) |
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(ins->drexdst << 3) | (ins->vex_wlp & 07);
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out(offset, segment, &bytes, OUT_RAWDATA, 3, NO_SEG, NO_SEG);
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offset += 3;
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} else {
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bytes[0] = 0xc5;
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bytes[1] = ((ins->rex & REX_R) << (7-2)) |
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(ins->drexdst << 3) | (ins->vex_wlp & 07);
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out(offset, segment, &bytes, OUT_RAWDATA, 2, NO_SEG, NO_SEG);
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offset += 2;
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}
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break;
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case 0300:
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case 0301:
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case 0302:
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@ -1887,7 +1992,7 @@ static int matches(const struct itemplate *itemp, insn * instruction, int bits)
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int32_t type = instruction->oprs[i].type;
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if (!(type & SIZE_MASK))
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type |= size[i];
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if (itemp->opd[i] & SAME_AS) {
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int j = itemp->opd[i] & ~SAME_AS;
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if (type != instruction->oprs[j].type ||
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10
disasm.c
10
disasm.c
@ -643,6 +643,16 @@ static int matches(const struct itemplate *t, uint8_t *data,
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return false;
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break;
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case 0172:
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{
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uint8_t ximm = *data++;
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c = *r++;
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ins->oprs[c >> 3].basereg = ximm >> 4;
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ins->oprs[c >> 3].segment |= SEG_RMREG;
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ins->oprs[c & 7].offset = ximm & 15;
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}
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break;
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case4(0200):
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case4(0204):
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case4(0210):
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@ -2023,6 +2023,12 @@ GETSEC void \2\x0F\x37 KATMAI
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PFRCP mmxreg,mmxrm \323\2\x0F\x0F\110\1\x86 PENT,3DNOW,SQ,CYRIX
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PFRSQRT mmxreg,mmxrm \323\2\x0F\x0F\110\1\x87 PENT,3DNOW,SQ,CYRIX
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;# Intel AVX instructions
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VPERMIL2PS xmmreg,xmmreg,xmmrm,xmmreg,imm \260\103\101\1\x48\123\172\34 AVX,SANDYBANKS
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VPERMIL2PS xmmreg,xmmreg,xmmreg,xmmrm,imm \260\103\111\1\x48\132\172\14 AVX,SANDYBANKS
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VPERMIL2PS ymmreg,ymmreg,ymmrm,ymmreg,imm \260\103\105\1\x48\123\172\34 AVX,SANDYBANKS
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VPERMIL2PS ymmreg,ymmreg,ymmreg,ymmrm,imm \260\103\115\1\x48\132\172\14 AVX,SANDYBANKS
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;# VIA (Centaur) security instructions
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XSTORE void \3\x0F\xA7\xC0 PENT,CYRIX
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XCRYPTECB void \333\3\x0F\xA7\xC8 PENT,CYRIX
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2
insns.h
2
insns.h
@ -98,6 +98,7 @@ extern const struct disasm_index itable[256];
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#define IF_SSE41 0x00800000UL /* it's an SSE4.1 instruction */
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#define IF_SSE42 0x00800000UL /* HACK NEED TO REORGANIZE THESE BITS */
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#define IF_SSE5 0x00800000UL /* HACK NEED TO REORGANIZE THESE BITS */
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#define IF_AVX 0x00800000UL /* HACK NEED TO REORGANIZE THESE BITS */
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#define IF_PMASK 0xFF000000UL /* the mask for processor types */
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#define IF_PLEVEL 0x0F000000UL /* the mask for processor instr. level */
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/* also the highest possible processor */
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@ -114,6 +115,7 @@ extern const struct disasm_index itable[256];
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#define IF_PRESCOTT 0x09000000UL /* Prescott instructions */
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#define IF_X86_64 0x0A000000UL /* x86-64 instruction (long or legacy mode) */
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#define IF_NEHALEM 0x0B000000UL /* Nehalem instruction */
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#define IF_SANDYBANKS 0x0C000000UL /* Sandy Banks instruction */
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#define IF_X64 (IF_LONG|IF_X86_64)
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#define IF_IA64 0x0F000000UL /* IA64 instructions (in x86 mode) */
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#define IF_CYRIX 0x10000000UL /* Cyrix-specific instruction */
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3
insns.pl
3
insns.pl
@ -241,8 +241,7 @@ sub format {
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$operands =~ s/imm(\d+)/imm|bits$1/g;
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$operands =~ s/imm/immediate/g;
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$operands =~ s/rm(\d+)/rm_gpr|bits$1/g;
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$operands =~ s/mmxrm/rm_mmx/g;
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$operands =~ s/xmmrm/rm_xmm/g;
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$operands =~ s/(mmx|xmm|ymm)rm/rm_$1/g;
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$operands =~ s/\=([0-9]+)/same_as|$1/g;
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if ($operands eq 'void') {
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@ops = ();
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12
nasm.c
12
nasm.c
@ -216,7 +216,7 @@ static void define_macros_early(void)
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strftime(temp, sizeof temp, "__UTC_TIME_NUM__=%H%M%S", &gm);
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pp_pre_define(temp);
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}
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if (gm_p)
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posix_time = posix_mktime(&gm);
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else if (lt_p)
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@ -502,7 +502,7 @@ static bool process_arg(char *p, char *q)
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case 'O': /* Optimization level */
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{
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int opt;
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if (!*param) {
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/* Naked -O == -Ox */
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optimizing = INT_MAX >> 1; /* Almost unlimited */
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@ -512,7 +512,7 @@ static bool process_arg(char *p, char *q)
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case '0': case '1': case '2': case '3': case '4':
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case '5': case '6': case '7': case '8': case '9':
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opt = strtoul(param, ¶m, 10);
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/* -O0 -> optimizing == -1, 0.98 behaviour */
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/* -O1 -> optimizing == 0, 0.98.09 behaviour */
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if (opt < 2)
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@ -520,18 +520,18 @@ static bool process_arg(char *p, char *q)
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else
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optimizing = opt;
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break;
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case 'v':
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case '+':
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param++;
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opt_verbose_info = true;
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break;
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case 'x':
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param++;
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optimizing = INT_MAX >> 1; /* Almost unlimited */
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break;
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default:
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report_error(ERR_FATAL,
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"unknown optimization option -O%c\n",
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27
nasm.h
27
nasm.h
@ -540,7 +540,7 @@ typedef uint32_t opflags_t;
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#define IP_REL 0x0002c000U /* IP-relative offset */
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/* memory which matches any type of r/m operand */
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#define MEMORY_ANY (MEMORY|RM_GPR|RM_MMX|RM_XMM)
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#define MEMORY_ANY (MEMORY|RM_GPR|RM_MMX|RM_XMM|RM_YMM)
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/* special type of immediate operand */
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#define UNITY 0x00012000U /* for shift/rotate instructions */
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@ -564,16 +564,17 @@ enum ccode { /* condition code names */
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/*
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* REX flags
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*/
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#define REX_OC 0x0200 /* DREX suffix has the OC0 bit set */
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#define REX_D 0x0100 /* Instruction uses DREX instead of REX */
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#define REX_H 0x80 /* High register present, REX forbidden */
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#define REX_P 0x40 /* REX prefix present/required */
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#define REX_L 0x20 /* Use LOCK prefix instead of REX.R */
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#define REX_W 0x08 /* 64-bit operand size */
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#define REX_R 0x04 /* ModRM reg extension */
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#define REX_X 0x02 /* SIB index extension */
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#define REX_B 0x01 /* ModRM r/m extension */
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#define REX_REAL 0x4f /* Actual REX prefix bits */
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#define REX_B 0x01 /* ModRM r/m extension */
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#define REX_X 0x02 /* SIB index extension */
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#define REX_R 0x04 /* ModRM reg extension */
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#define REX_W 0x08 /* 64-bit operand size */
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#define REX_L 0x20 /* Use LOCK prefix instead of REX.R */
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#define REX_P 0x40 /* REX prefix present/required */
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#define REX_H 0x80 /* High register present, REX forbidden */
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#define REX_D 0x0100 /* Instruction uses DREX instead of REX */
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#define REX_OC 0x0200 /* DREX suffix has the OC0 bit set */
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#define REX_V 0x0400 /* Instruction uses VEX instead of REX */
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/*
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* Note that because segment registers may be used as instruction
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@ -651,7 +652,7 @@ enum prefix_pos {
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MAXPREFIX /* Total number of prefix slots */
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};
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#define MAX_OPERANDS 4
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#define MAX_OPERANDS 5
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typedef struct insn { /* an instruction itself */
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char *label; /* the label defined, or NULL */
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@ -667,7 +668,9 @@ typedef struct insn { /* an instruction itself */
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int32_t times; /* repeat count (TIMES prefix) */
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int forw_ref; /* is there a forward reference? */
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int rex; /* Special REX Prefix */
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int drexdst; /* Destination register for DREX suffix */
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int drexdst; /* Destination register for DREX/VEX suffix */
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int vex_m; /* M register for VEX prefix */
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int vex_wlp; /* W, P and L information for VEX prefix */
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} insn;
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enum geninfo { GI_SWITCH };
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@ -671,7 +671,7 @@ void saa_wleb128u(struct SAA *psaa, int value)
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ptemp++;
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len++;
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} while (value != 0);
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saa_wbytes(psaa, temp, len);
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saa_wbytes(psaa, temp, len);
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}
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/* write signed LEB128 value to SAA */
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@ -703,8 +703,8 @@ void saa_wleb128s(struct SAA *psaa, int value)
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*ptemp = byte;
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ptemp++;
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len++;
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}
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saa_wbytes(psaa, temp, len);
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}
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saa_wbytes(psaa, temp, len);
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}
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void saa_rewind(struct SAA *s)
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@ -1585,14 +1585,14 @@ static bool if_condition(Token * tline, enum preproc_token ct)
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|
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iftype:
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t = tline = expand_smacro(tline);
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|
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while (tok_type_(t, TOK_WHITESPACE) ||
|
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(needtype == TOK_NUMBER &&
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tok_type_(t, TOK_OTHER) &&
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(t->text[0] == '-' || t->text[0] == '+') &&
|
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!t->text[1]))
|
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t = t->next;
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|
||||
|
||||
j = tok_type_(t, needtype);
|
||||
break;
|
||||
|
||||
|
||||
9
test/avx.asm
Normal file
9
test/avx.asm
Normal file
@ -0,0 +1,9 @@
|
||||
bits 64
|
||||
vpermil2ps xmm0,xmm1,[rdi],xmm3,0
|
||||
vpermil2ps xmm0,xmm1,xmm2,[rdi],1
|
||||
vpermil2ps ymm0,ymm1,ymm2,ymm3,2
|
||||
vpermil2ps ymm0,ymm1,ymm2,[rdi],3
|
||||
vpermil2ps ymm0,ymm1,[rdi],ymm3,2
|
||||
vpermil2ps ymm0,ymm1,ymm2,[rdi],3
|
||||
|
||||
|
||||
6
wsaa.h
6
wsaa.h
@ -32,13 +32,13 @@
|
||||
|
||||
#else /* !X86_MEMORY */
|
||||
|
||||
#define WSAACHAR(s,p,v) \
|
||||
#define WSAACHAR(s,p,v) \
|
||||
do { \
|
||||
*(uint8_t *)(p) = (v); \
|
||||
saa_wbytes(s, p, 1); \
|
||||
} while (0)
|
||||
|
||||
#define WSAASHORT(s,p,v) \
|
||||
#define WSAASHORT(s,p,v) \
|
||||
do { \
|
||||
uint16_t _wss_v = (v); \
|
||||
uint8_t *_wss_p = (uint8_t *)(p); \
|
||||
@ -58,7 +58,7 @@
|
||||
saa_wbytes(s, _wsl_p, 4); \
|
||||
} while (0)
|
||||
|
||||
#define WSAADLONG(s,p,v) \
|
||||
#define WSAADLONG(s,p,v) \
|
||||
do { \
|
||||
uint64_t _wsq_v = (v); \
|
||||
uint8_t *_wsq_p = (uint8_t *)(p); \
|
||||
|
||||
Loading…
Reference in New Issue
Block a user