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AVX-512: Add AVX-512CD instructions
Added Conflict Detection (AVX-512CD) instructions. These instructions are supported if CPUID.(EAX=07H, ECX=0):EBX.AVX512CD[bit 28] = 1. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
This commit is contained in:
Jin Kyu Song
Cyrill Gorcunov
parent
c257bb6ae0
commit
d4b2b5f17c
10
insns.dat
10
insns.dat
@ -4054,6 +4054,16 @@ KUNPCKBW kreg,kreg,kreg [rvm: vex.nds.l1.66.0f.w0 4b /r ] AVX512,FUTURE
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KXNORW kreg,kreg,kreg [rvm: vex.nds.l1.0f.w0 46 /r ] AVX512,FUTURE
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KXORW kreg,kreg,kreg [rvm: vex.nds.l1.0f.w0 47 /r ] AVX512,FUTURE
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; AVX-512CD (Conflict Detection) instructions
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VPBROADCASTMB2Q zmmreg,kreg [rm: evex.512.f3.0f38.w1 2a /r ] AVX512CD,FUTURE
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VPBROADCASTMW2D zmmreg,kreg [rm: evex.512.f3.0f38.w0 3a /r ] AVX512CD,FUTURE
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VPCONFLICTD zmmreg|mask|z,zmmrm512|b32 [rm:fv: evex.512.66.0f38.w0 c4 /r ] AVX512CD,FUTURE
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VPCONFLICTQ zmmreg|mask|z,zmmrm512|b64 [rm:fv: evex.512.66.0f38.w1 c4 /r ] AVX512CD,FUTURE
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VPLZCNTD zmmreg|mask|z,zmmrm512|b32 [rm:fv: evex.512.66.0f38.w0 44 /r ] AVX512CD,FUTURE
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VPLZCNTQ zmmreg|mask|z,zmmrm512|b64 [rm:fv: evex.512.66.0f38.w1 44 /r ] AVX512CD,FUTURE
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VPTESTNMD kreg|mask,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.f3.0f38.w0 27 /r ] AVX512CD,FUTURE
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VPTESTNMQ kreg|mask,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.f3.0f38.w1 27 /r ] AVX512CD,FUTURE
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;# Systematic names for the hinting nop instructions
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; These should be last in the file
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1
insns.h
1
insns.h
@ -128,6 +128,7 @@ extern const uint8_t nasm_bytecodes[];
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#define IF_TBM 0x1300000000UL /* HACK NEED TO REORGANIZE THESE BITS */
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#define IF_RTM 0x1400000000UL /* HACK NEED TO REORGANIZE THESE BITS */
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#define IF_INVPCID 0x1500000000UL /* HACK NEED TO REORGANIZE THESE BITS */
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#define IF_AVX512CD 0x1600000000UL /* AVX-512 Conflict Detection insns */
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#define IF_INSMASK 0xFF00000000UL /* the mask for instruction set types */
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#define IF_PMASK 0xFF000000UL /* the mask for processor types */
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#define IF_PLEVEL 0x0F000000UL /* the mask for processor instr. level */
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105
test/avx512cd.asm
Normal file
105
test/avx512cd.asm
Normal file
@ -0,0 +1,105 @@
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; AVX-512CD testcases from gas
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;------------------------
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;
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; This file is taken from there
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; https://gnu.googlesource.com/binutils/+/master/gas/testsuite/gas/i386/x86-64-avx512cd-intel.d
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; So the original author is "H.J. Lu" <hongjiu dot lu at intel dot com>
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;
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; Jin Kyu Song converted it for the nasm testing suite using gas2nasm.py
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%macro testcase 2
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%ifdef BIN
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db %1
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%endif
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%ifdef SRC
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%2
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%endif
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%endmacro
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bits 64
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testcase { 0x62, 0x02, 0x7d, 0x48, 0xc4, 0xf5 }, { vpconflictd zmm30,zmm29 }
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testcase { 0x62, 0x02, 0x7d, 0x4f, 0xc4, 0xf5 }, { vpconflictd zmm30\{k7\},zmm29 }
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testcase { 0x62, 0x02, 0x7d, 0xcf, 0xc4, 0xf5 }, { vpconflictd zmm30\{k7\}\{z\},zmm29 }
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testcase { 0x62, 0x62, 0x7d, 0x48, 0xc4, 0x31 }, { vpconflictd zmm30,ZWORD [rcx] }
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testcase { 0x62, 0x22, 0x7d, 0x48, 0xc4, 0xb4, 0xf0, 0x23, 0x01, 0x00, 0x00 }, { vpconflictd zmm30,ZWORD [rax+r14*8+0x123] }
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testcase { 0x62, 0x62, 0x7d, 0x58, 0xc4, 0x31 }, { vpconflictd zmm30,DWORD [rcx]\{1to16\} }
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testcase { 0x62, 0x62, 0x7d, 0x48, 0xc4, 0x72, 0x7f }, { vpconflictd zmm30,ZWORD [rdx+0x1fc0] }
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testcase { 0x62, 0x62, 0x7d, 0x48, 0xc4, 0xb2, 0x00, 0x20, 0x00, 0x00 }, { vpconflictd zmm30,ZWORD [rdx+0x2000] }
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testcase { 0x62, 0x62, 0x7d, 0x48, 0xc4, 0x72, 0x80 }, { vpconflictd zmm30,ZWORD [rdx-0x2000] }
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testcase { 0x62, 0x62, 0x7d, 0x48, 0xc4, 0xb2, 0xc0, 0xdf, 0xff, 0xff }, { vpconflictd zmm30,ZWORD [rdx-0x2040] }
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testcase { 0x62, 0x62, 0x7d, 0x58, 0xc4, 0x72, 0x7f }, { vpconflictd zmm30,DWORD [rdx+0x1fc]\{1to16\} }
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testcase { 0x62, 0x62, 0x7d, 0x58, 0xc4, 0xb2, 0x00, 0x02, 0x00, 0x00 }, { vpconflictd zmm30,DWORD [rdx+0x200]\{1to16\} }
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testcase { 0x62, 0x62, 0x7d, 0x58, 0xc4, 0x72, 0x80 }, { vpconflictd zmm30,DWORD [rdx-0x200]\{1to16\} }
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testcase { 0x62, 0x62, 0x7d, 0x58, 0xc4, 0xb2, 0xfc, 0xfd, 0xff, 0xff }, { vpconflictd zmm30,DWORD [rdx-0x204]\{1to16\} }
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testcase { 0x62, 0x02, 0xfd, 0x48, 0xc4, 0xf5 }, { vpconflictq zmm30,zmm29 }
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testcase { 0x62, 0x02, 0xfd, 0x4f, 0xc4, 0xf5 }, { vpconflictq zmm30\{k7\},zmm29 }
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testcase { 0x62, 0x02, 0xfd, 0xcf, 0xc4, 0xf5 }, { vpconflictq zmm30\{k7\}\{z\},zmm29 }
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testcase { 0x62, 0x62, 0xfd, 0x48, 0xc4, 0x31 }, { vpconflictq zmm30,ZWORD [rcx] }
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testcase { 0x62, 0x22, 0xfd, 0x48, 0xc4, 0xb4, 0xf0, 0x23, 0x01, 0x00, 0x00 }, { vpconflictq zmm30,ZWORD [rax+r14*8+0x123] }
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testcase { 0x62, 0x62, 0xfd, 0x58, 0xc4, 0x31 }, { vpconflictq zmm30,QWORD [rcx]\{1to8\} }
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testcase { 0x62, 0x62, 0xfd, 0x48, 0xc4, 0x72, 0x7f }, { vpconflictq zmm30,ZWORD [rdx+0x1fc0] }
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testcase { 0x62, 0x62, 0xfd, 0x48, 0xc4, 0xb2, 0x00, 0x20, 0x00, 0x00 }, { vpconflictq zmm30,ZWORD [rdx+0x2000] }
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testcase { 0x62, 0x62, 0xfd, 0x48, 0xc4, 0x72, 0x80 }, { vpconflictq zmm30,ZWORD [rdx-0x2000] }
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testcase { 0x62, 0x62, 0xfd, 0x48, 0xc4, 0xb2, 0xc0, 0xdf, 0xff, 0xff }, { vpconflictq zmm30,ZWORD [rdx-0x2040] }
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testcase { 0x62, 0x62, 0xfd, 0x58, 0xc4, 0x72, 0x7f }, { vpconflictq zmm30,QWORD [rdx+0x3f8]\{1to8\} }
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testcase { 0x62, 0x62, 0xfd, 0x58, 0xc4, 0xb2, 0x00, 0x04, 0x00, 0x00 }, { vpconflictq zmm30,QWORD [rdx+0x400]\{1to8\} }
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testcase { 0x62, 0x62, 0xfd, 0x58, 0xc4, 0x72, 0x80 }, { vpconflictq zmm30,QWORD [rdx-0x400]\{1to8\} }
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testcase { 0x62, 0x62, 0xfd, 0x58, 0xc4, 0xb2, 0xf8, 0xfb, 0xff, 0xff }, { vpconflictq zmm30,QWORD [rdx-0x408]\{1to8\} }
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testcase { 0x62, 0x02, 0x7d, 0x48, 0x44, 0xf5 }, { vplzcntd zmm30,zmm29 }
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testcase { 0x62, 0x02, 0x7d, 0x4f, 0x44, 0xf5 }, { vplzcntd zmm30\{k7\},zmm29 }
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testcase { 0x62, 0x02, 0x7d, 0xcf, 0x44, 0xf5 }, { vplzcntd zmm30\{k7\}\{z\},zmm29 }
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testcase { 0x62, 0x62, 0x7d, 0x48, 0x44, 0x31 }, { vplzcntd zmm30,ZWORD [rcx] }
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testcase { 0x62, 0x22, 0x7d, 0x48, 0x44, 0xb4, 0xf0, 0x23, 0x01, 0x00, 0x00 }, { vplzcntd zmm30,ZWORD [rax+r14*8+0x123] }
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testcase { 0x62, 0x62, 0x7d, 0x58, 0x44, 0x31 }, { vplzcntd zmm30,DWORD [rcx]\{1to16\} }
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testcase { 0x62, 0x62, 0x7d, 0x48, 0x44, 0x72, 0x7f }, { vplzcntd zmm30,ZWORD [rdx+0x1fc0] }
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testcase { 0x62, 0x62, 0x7d, 0x48, 0x44, 0xb2, 0x00, 0x20, 0x00, 0x00 }, { vplzcntd zmm30,ZWORD [rdx+0x2000] }
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testcase { 0x62, 0x62, 0x7d, 0x48, 0x44, 0x72, 0x80 }, { vplzcntd zmm30,ZWORD [rdx-0x2000] }
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testcase { 0x62, 0x62, 0x7d, 0x48, 0x44, 0xb2, 0xc0, 0xdf, 0xff, 0xff }, { vplzcntd zmm30,ZWORD [rdx-0x2040] }
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testcase { 0x62, 0x62, 0x7d, 0x58, 0x44, 0x72, 0x7f }, { vplzcntd zmm30,DWORD [rdx+0x1fc]\{1to16\} }
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testcase { 0x62, 0x62, 0x7d, 0x58, 0x44, 0xb2, 0x00, 0x02, 0x00, 0x00 }, { vplzcntd zmm30,DWORD [rdx+0x200]\{1to16\} }
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testcase { 0x62, 0x62, 0x7d, 0x58, 0x44, 0x72, 0x80 }, { vplzcntd zmm30,DWORD [rdx-0x200]\{1to16\} }
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testcase { 0x62, 0x62, 0x7d, 0x58, 0x44, 0xb2, 0xfc, 0xfd, 0xff, 0xff }, { vplzcntd zmm30,DWORD [rdx-0x204]\{1to16\} }
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testcase { 0x62, 0x02, 0xfd, 0x48, 0x44, 0xf5 }, { vplzcntq zmm30,zmm29 }
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testcase { 0x62, 0x02, 0xfd, 0x4f, 0x44, 0xf5 }, { vplzcntq zmm30\{k7\},zmm29 }
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testcase { 0x62, 0x02, 0xfd, 0xcf, 0x44, 0xf5 }, { vplzcntq zmm30\{k7\}\{z\},zmm29 }
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testcase { 0x62, 0x62, 0xfd, 0x48, 0x44, 0x31 }, { vplzcntq zmm30,ZWORD [rcx] }
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testcase { 0x62, 0x22, 0xfd, 0x48, 0x44, 0xb4, 0xf0, 0x23, 0x01, 0x00, 0x00 }, { vplzcntq zmm30,ZWORD [rax+r14*8+0x123] }
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testcase { 0x62, 0x62, 0xfd, 0x58, 0x44, 0x31 }, { vplzcntq zmm30,QWORD [rcx]\{1to8\} }
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testcase { 0x62, 0x62, 0xfd, 0x48, 0x44, 0x72, 0x7f }, { vplzcntq zmm30,ZWORD [rdx+0x1fc0] }
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testcase { 0x62, 0x62, 0xfd, 0x48, 0x44, 0xb2, 0x00, 0x20, 0x00, 0x00 }, { vplzcntq zmm30,ZWORD [rdx+0x2000] }
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testcase { 0x62, 0x62, 0xfd, 0x48, 0x44, 0x72, 0x80 }, { vplzcntq zmm30,ZWORD [rdx-0x2000] }
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testcase { 0x62, 0x62, 0xfd, 0x48, 0x44, 0xb2, 0xc0, 0xdf, 0xff, 0xff }, { vplzcntq zmm30,ZWORD [rdx-0x2040] }
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testcase { 0x62, 0x62, 0xfd, 0x58, 0x44, 0x72, 0x7f }, { vplzcntq zmm30,QWORD [rdx+0x3f8]\{1to8\} }
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testcase { 0x62, 0x62, 0xfd, 0x58, 0x44, 0xb2, 0x00, 0x04, 0x00, 0x00 }, { vplzcntq zmm30,QWORD [rdx+0x400]\{1to8\} }
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testcase { 0x62, 0x62, 0xfd, 0x58, 0x44, 0x72, 0x80 }, { vplzcntq zmm30,QWORD [rdx-0x400]\{1to8\} }
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testcase { 0x62, 0x62, 0xfd, 0x58, 0x44, 0xb2, 0xf8, 0xfb, 0xff, 0xff }, { vplzcntq zmm30,QWORD [rdx-0x408]\{1to8\} }
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testcase { 0x62, 0x92, 0x16, 0x40, 0x27, 0xec }, { vptestnmd k5,zmm29,zmm28 }
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testcase { 0x62, 0x92, 0x16, 0x47, 0x27, 0xec }, { vptestnmd k5\{k7\},zmm29,zmm28 }
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testcase { 0x62, 0xf2, 0x16, 0x40, 0x27, 0x29 }, { vptestnmd k5,zmm29,ZWORD [rcx] }
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testcase { 0x62, 0xb2, 0x16, 0x40, 0x27, 0xac, 0xf0, 0x23, 0x01, 0x00, 0x00 }, { vptestnmd k5,zmm29,ZWORD [rax+r14*8+0x123] }
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testcase { 0x62, 0xf2, 0x16, 0x50, 0x27, 0x29 }, { vptestnmd k5,zmm29,DWORD [rcx]\{1to16\} }
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testcase { 0x62, 0xf2, 0x16, 0x40, 0x27, 0x6a, 0x7f }, { vptestnmd k5,zmm29,ZWORD [rdx+0x1fc0] }
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testcase { 0x62, 0xf2, 0x16, 0x40, 0x27, 0xaa, 0x00, 0x20, 0x00, 0x00 }, { vptestnmd k5,zmm29,ZWORD [rdx+0x2000] }
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testcase { 0x62, 0xf2, 0x16, 0x40, 0x27, 0x6a, 0x80 }, { vptestnmd k5,zmm29,ZWORD [rdx-0x2000] }
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testcase { 0x62, 0xf2, 0x16, 0x40, 0x27, 0xaa, 0xc0, 0xdf, 0xff, 0xff }, { vptestnmd k5,zmm29,ZWORD [rdx-0x2040] }
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testcase { 0x62, 0xf2, 0x16, 0x50, 0x27, 0x6a, 0x7f }, { vptestnmd k5,zmm29,DWORD [rdx+0x1fc]\{1to16\} }
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testcase { 0x62, 0xf2, 0x16, 0x50, 0x27, 0xaa, 0x00, 0x02, 0x00, 0x00 }, { vptestnmd k5,zmm29,DWORD [rdx+0x200]\{1to16\} }
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testcase { 0x62, 0xf2, 0x16, 0x50, 0x27, 0x6a, 0x80 }, { vptestnmd k5,zmm29,DWORD [rdx-0x200]\{1to16\} }
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testcase { 0x62, 0xf2, 0x16, 0x50, 0x27, 0xaa, 0xfc, 0xfd, 0xff, 0xff }, { vptestnmd k5,zmm29,DWORD [rdx-0x204]\{1to16\} }
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testcase { 0x62, 0x92, 0x96, 0x40, 0x27, 0xec }, { vptestnmq k5,zmm29,zmm28 }
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testcase { 0x62, 0x92, 0x96, 0x47, 0x27, 0xec }, { vptestnmq k5\{k7\},zmm29,zmm28 }
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testcase { 0x62, 0xf2, 0x96, 0x40, 0x27, 0x29 }, { vptestnmq k5,zmm29,ZWORD [rcx] }
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testcase { 0x62, 0xb2, 0x96, 0x40, 0x27, 0xac, 0xf0, 0x23, 0x01, 0x00, 0x00 }, { vptestnmq k5,zmm29,ZWORD [rax+r14*8+0x123] }
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testcase { 0x62, 0xf2, 0x96, 0x50, 0x27, 0x29 }, { vptestnmq k5,zmm29,QWORD [rcx]\{1to8\} }
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testcase { 0x62, 0xf2, 0x96, 0x40, 0x27, 0x6a, 0x7f }, { vptestnmq k5,zmm29,ZWORD [rdx+0x1fc0] }
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testcase { 0x62, 0xf2, 0x96, 0x40, 0x27, 0xaa, 0x00, 0x20, 0x00, 0x00 }, { vptestnmq k5,zmm29,ZWORD [rdx+0x2000] }
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testcase { 0x62, 0xf2, 0x96, 0x40, 0x27, 0x6a, 0x80 }, { vptestnmq k5,zmm29,ZWORD [rdx-0x2000] }
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testcase { 0x62, 0xf2, 0x96, 0x40, 0x27, 0xaa, 0xc0, 0xdf, 0xff, 0xff }, { vptestnmq k5,zmm29,ZWORD [rdx-0x2040] }
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testcase { 0x62, 0xf2, 0x96, 0x50, 0x27, 0x6a, 0x7f }, { vptestnmq k5,zmm29,QWORD [rdx+0x3f8]\{1to8\} }
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testcase { 0x62, 0xf2, 0x96, 0x50, 0x27, 0xaa, 0x00, 0x04, 0x00, 0x00 }, { vptestnmq k5,zmm29,QWORD [rdx+0x400]\{1to8\} }
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testcase { 0x62, 0xf2, 0x96, 0x50, 0x27, 0x6a, 0x80 }, { vptestnmq k5,zmm29,QWORD [rdx-0x400]\{1to8\} }
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testcase { 0x62, 0xf2, 0x96, 0x50, 0x27, 0xaa, 0xf8, 0xfb, 0xff, 0xff }, { vptestnmq k5,zmm29,QWORD [rdx-0x408]\{1to8\} }
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testcase { 0x62, 0x62, 0x7e, 0x48, 0x3a, 0xf6 }, { vpbroadcastmw2d zmm30,k6 }
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testcase { 0x62, 0x62, 0xfe, 0x48, 0x2a, 0xf6 }, { vpbroadcastmb2q zmm30,k6 }
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