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https://github.com/netwide-assembler/nasm.git
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Actually generate SSE5 instructions
This checkin completes what is required to actually generate SSE5 instructions. No support in the disassembler yet. This checkin covers: - Support for actually generating DREX prefixes. - Support for matching operand "operand X must match Y"
This commit is contained in:
H. Peter Anvin
parent
401c07e20d
commit
cf5180a955
19
assemble.c
19
assemble.c
@ -856,6 +856,7 @@ static int32_t calcsize(int32_t segment, int32_t offset, int bits,
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case 0163:
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length++;
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ins->rex |= REX_D;
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ins->drexdst = regval(&ins->oprs[c & 3]);
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break;
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case 0164:
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case 0165:
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@ -863,6 +864,7 @@ static int32_t calcsize(int32_t segment, int32_t offset, int bits,
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case 0167:
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length++;
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ins->rex |= REX_D|REX_OC;
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ins->drexdst = regval(&ins->oprs[c & 3]);
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break;
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case 0170:
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length++;
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@ -974,6 +976,11 @@ static int32_t calcsize(int32_t segment, int32_t offset, int bits,
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errfunc(ERR_NONFATAL, "cannot use high register in drex instruction");
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return -1;
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}
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if (bits != 64 && ((ins->rex & (REX_W|REX_X|REX_B)) ||
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ins->drexdst > 7)) {
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errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
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return -1;
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}
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length++;
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} else if (ins->rex & REX_REAL) {
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if (ins->rex & REX_H) {
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@ -985,8 +992,8 @@ static int32_t calcsize(int32_t segment, int32_t offset, int bits,
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cpu >= IF_X86_64)) {
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length++;
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} else {
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errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
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return -1;
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errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
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return -1;
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}
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}
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@ -1358,7 +1365,6 @@ static void gencode(int32_t segment, int32_t offset, int bits,
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case 0165:
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case 0166:
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case 0167:
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ins->drexdst = regval(&ins->oprs[c & 3]);
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break;
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case 0170:
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@ -1663,7 +1669,12 @@ static int matches(const struct itemplate *itemp, insn * instruction, int bits)
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* Check that the operand flags all match up
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*/
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for (i = 0; i < itemp->operands; i++) {
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if (itemp->opd[i] & ~instruction->oprs[i].type ||
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if (itemp->opd[i] & SAME_AS) {
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int j = itemp->opd[i] & ~SAME_AS;
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if (instruction->oprs[i].type != instruction->oprs[j].type ||
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instruction->oprs[i].basereg != instruction->oprs[j].basereg)
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return 0;
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} else if (itemp->opd[i] & ~instruction->oprs[i].type ||
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((itemp->opd[i] & SIZE_MASK) &&
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((itemp->opd[i] ^ instruction->oprs[i].type) & SIZE_MASK))) {
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if ((itemp->opd[i] & ~instruction->oprs[i].type & ~SIZE_MASK) ||
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18
insns.dat
18
insns.dat
@ -2020,3 +2020,21 @@ PCMPGTQ xmmreg,xmmrm \366\3\x0F\x38\x37\110 SSE42
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POPCNT reg16,rm16 \320\333\2\x0F\xB8\110 NEHALEM
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POPCNT reg32,rm32 \321\333\2\x0F\xB8\110 NEHALEM
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POPCNT reg64,rm32 \324\333\2\x0F\xB8\110 NEHALEM,X64
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; AMD SSE5 instructions
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FMSUBPS xmmreg,=0,xmmreg,xmmrm \160\3\x0F\x24\x08\132 SSE5
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FMSUBPS xmmreg,=0,xmmrm,xmmreg \164\3\x0F\x24\x08\123 SSE5
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FMSUBPS xmmreg,xmmreg,xmmrm,=0 \160\3\x0F\x24\x0C\121 SSE5
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FMSUBPS xmmreg,xmmrm,xmmreg,=0 \164\3\x0F\x24\x0C\112 SSE5
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FMSUBPD xmmreg,=0,xmmreg,xmmrm \160\3\x0F\x24\x09\132 SSE5
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FMSUBPD xmmreg,=0,xmmrm,xmmreg \164\3\x0F\x24\x09\123 SSE5
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FMSUBPD xmmreg,xmmreg,xmmrm,=0 \160\3\x0F\x24\x0D\121 SSE5
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FMSUBPD xmmreg,xmmrm,xmmreg,=0 \164\3\x0F\x24\x0D\112 SSE5
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FMSUBSS xmmreg,=0,xmmreg,xmmrm \160\3\x0F\x24\x0A\132 SSE5
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FMSUBSS xmmreg,=0,xmmrm,xmmreg \164\3\x0F\x24\x0A\123 SSE5
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FMSUBSS xmmreg,xmmreg,xmmrm,=0 \160\3\x0F\x24\x0E\121 SSE5
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FMSUBSS xmmreg,xmmrm,xmmreg,=0 \164\3\x0F\x24\x0E\112 SSE5
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FMSUBSD xmmreg,=0,xmmreg,xmmrm \160\3\x0F\x24\x0B\132 SSE5
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FMSUBSD xmmreg,=0,xmmrm,xmmreg \164\3\x0F\x24\x0B\123 SSE5
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FMSUBSD xmmreg,xmmreg,xmmrm,=0 \160\3\x0F\x24\x0F\121 SSE5
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FMSUBSD xmmreg,xmmrm,xmmreg,=0 \164\3\x0F\x24\x0F\112 SSE5
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3
insns.h
3
insns.h
@ -21,7 +21,7 @@
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struct itemplate {
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enum opcode opcode; /* the token, passed from "parser.c" */
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int operands; /* number of operands */
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int32_t opd[MAX_OPERANDS]; /* bit flags for operand types */
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opflags_t opd[MAX_OPERANDS]; /* bit flags for operand types */
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const char *code; /* the code it assembles to */
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uint32_t flags; /* some flags */
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};
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@ -90,6 +90,7 @@ extern const struct itemplate * const * const itable[];
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#define IF_SSSE3 0x00200000UL /* it's an SSSE3 instruction */
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#define IF_SSE41 0x00400000UL /* it's an SSE4.1 instruction */
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#define IF_SSE42 0x00800000UL /* it's an SSE4.2 instruction */
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#define IF_SSE5 0x00800000UL /* HACK NEED TO REORGANIZE THESE BITS */
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#define IF_PMASK 0xFF000000UL /* the mask for processor types */
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#define IF_PLEVEL 0x0F000000UL /* the mask for processor instr. level */
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/* also the highest possible processor */
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1
insns.pl
1
insns.pl
@ -218,6 +218,7 @@ sub format {
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$operands =~ s/rm(\d+)/rm_gpr|bits$1/g;
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$operands =~ s/mmxrm/rm_mmx/g;
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$operands =~ s/xmmrm/rm_xmm/g;
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$operands =~ s/\=([0-9]+)/same_as|$1/g;
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if ($operands eq 'void') {
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@ops = ();
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} else {
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12
nasm.h
12
nasm.h
@ -438,9 +438,16 @@ enum {
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* 25: RM_MMX (MMXREG)
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* 26: RM_XMM (XMMREG)
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*
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* Bits 27-31 are currently unallocated.
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* Bits 27-29 & 31 are currently unallocated.
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*
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* 30: SAME_AS
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* Special flag only used in instruction patterns; means this operand
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* has to be identical to another operand. Currently only supported
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* for registers.
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*/
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typedef uint32_t opflags_t;
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/* Size, and other attributes, of the operand */
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#define BITS8 0x00000001L
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#define BITS16 0x00000002L
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@ -527,6 +534,9 @@ enum {
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#define UNITY 0x00012000L /* for shift/rotate instructions */
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#define SBYTE 0x00022000L /* for op r16/32,immediate instrs. */
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/* special flags */
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#define SAME_AS 0x40000000L
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/* Register names automatically generated from regs.dat */
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#include "regs.h"
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16
test/fmsub.asm
Normal file
16
test/fmsub.asm
Normal file
@ -0,0 +1,16 @@
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bits 64
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fmsubps xmm0,xmm0,xmm1,xmm2
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fmsubps xmm0,xmm0,xmm1,[rax]
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fmsubps xmm0,xmm0,xmm1,[rax+0x77]
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fmsubps xmm0,xmm0,xmm1,[rax+0x7777]
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fmsubps xmm1,xmm2,xmm3,xmm1
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fmsubps xmm1,xmm2,[rax],xmm1
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fmsubps xmm1,xmm2,[rax+0x77],xmm1
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fmsubps xmm1,xmm2,[rax+0x7777],xmm1
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fmsubps xmm0,[rax],xmm2,xmm0
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fmsubps xmm0,[rax+0x77],xmm2,xmm0
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fmsubps xmm0,[rax+0x7777],xmm2,xmm0
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fmsubps xmm14,[rax],xmm2,xmm14
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fmsubps xmm14,[rax+0x77],xmm2,xmm14
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fmsubps xmm14,[rax+0x7777],xmm2,xmm14
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