From f0b01552802fdeac5bdb7f1d4d2977a429c5588d Mon Sep 17 00:00:00 2001 From: Cyrill Gorcunov Date: Mon, 24 Aug 2020 13:48:31 +0300 Subject: [PATCH 01/34] travis: add a64 test Signed-off-by: Cyrill Gorcunov --- travis/test/a64.asm | 22 ++++++++++++++++++++++ travis/test/a64.bin.t | 1 + travis/test/a64.json | 18 ++++++++++++++++++ 3 files changed, 41 insertions(+) create mode 100644 travis/test/a64.asm create mode 100644 travis/test/a64.bin.t create mode 100644 travis/test/a64.json diff --git a/travis/test/a64.asm b/travis/test/a64.asm new file mode 100644 index 00000000..057c29fc --- /dev/null +++ b/travis/test/a64.asm @@ -0,0 +1,22 @@ + bits 64 +start: + invlpga eax, ecx + invlpga rax, ecx + jecxz start + jrcxz start + loop start, ecx + loop start, rcx + loope start, ecx + loope start, rcx + loopz start, ecx + loopz start, rcx + loopne start, ecx + loopne start, rcx + loopnz start, ecx + loopnz start, rcx + clzero eax + clzero rax + movdir64b eax, [edi] + movdir64b rax, [rdi] + umonitor eax + umonitor rax diff --git a/travis/test/a64.bin.t b/travis/test/a64.bin.t new file mode 100644 index 00000000..b13b9e53 --- /dev/null +++ b/travis/test/a64.bin.t @@ -0,0 +1 @@ +gßßgãöãôgâñâïgáìáêgáçáågàâààgàÝàÛgüügf8øf8øgó®ðó®ð \ No newline at end of file diff --git a/travis/test/a64.json b/travis/test/a64.json new file mode 100644 index 00000000..f734b11e --- /dev/null +++ b/travis/test/a64.json @@ -0,0 +1,18 @@ +[ + { + "description": "Test 64 bit address (-Ox)", + "id": "a64", + "format": "bin", + "source": "a64.asm", + "option": "-Ox", + "target": [ + { "output": "a64.bin" } + ] + }, + { + "description": "Test 64 bit address (-O0)", + "ref": "a64", + "option": "-O0", + "update": "false" + } +] From 3d1f5ce8e7eb3eee5482ad69d2d27456e657ad51 Mon Sep 17 00:00:00 2001 From: Cyrill Gorcunov Date: Mon, 24 Aug 2020 13:50:43 +0300 Subject: [PATCH 02/34] travis: update absolute To match test/ instance. Signed-off-by: Cyrill Gorcunov --- travis/test/absolute.asm | 3 +++ 1 file changed, 3 insertions(+) diff --git a/travis/test/absolute.asm b/travis/test/absolute.asm index 38532ec9..8a72a9b5 100644 --- a/travis/test/absolute.asm +++ b/travis/test/absolute.asm @@ -1,4 +1,7 @@ +%ifmacro org org 7c00h +%endif + init_foo: jmp init_bar nop From 355d8bf40c926b28d9a6ce9f4e721b99a9826831 Mon Sep 17 00:00:00 2001 From: Cyrill Gorcunov Date: Mon, 24 Aug 2020 13:55:02 +0300 Subject: [PATCH 03/34] travis: add amx test Signed-off-by: Cyrill Gorcunov --- travis/test/amx.asm | 36 ++++++++++++++++++++++++++++++++++++ travis/test/amx.bin.t | 1 + travis/test/amx.json | 12 ++++++++++++ 3 files changed, 49 insertions(+) create mode 100644 travis/test/amx.asm create mode 100644 travis/test/amx.bin.t create mode 100644 travis/test/amx.json diff --git a/travis/test/amx.asm b/travis/test/amx.asm new file mode 100644 index 00000000..88455508 --- /dev/null +++ b/travis/test/amx.asm @@ -0,0 +1,36 @@ + bits 64 + +%macro amx 1 + %define treg tmm %+ %1 + + ldtilecfg [rsi] + sttilecfg [rdi] + + tilezero treg + + tileloadd treg, [rax] + tileloadd treg, [rax,rdx] + tileloadd treg, [rax,rdx*2] + + tileloaddt1 treg, [rax] + tileloaddt1 treg, [rax,rdx] + tileloaddt1 treg, [rax,rdx*2] + + tdpbf16ps treg, treg, treg + tdpbssd treg, treg, treg + tdpbusd treg, treg, treg + tdpbsud treg, treg, treg + tdpbuud treg, treg, treg + + tilestored [rax], treg + tilestored [rax,rdx], treg + tilestored [rax,rdx*2], treg + + tilerelease +%endmacro + +%assign n 0 + %rep 8 + amx n + %assign n n+1 + %endrep diff --git a/travis/test/amx.bin.t b/travis/test/amx.bin.t new file mode 100644 index 00000000..ad28ba5b --- /dev/null +++ b/travis/test/amx.bin.t @@ -0,0 +1 @@ +ÄâxIÄâyIÄâ{IÀÄâ{K Äâ{KÄâ{KPÄâyK ÄâyKÄâyKPÄâz\ÀÄâ{^ÀÄây^ÀÄâz^ÀÄâx^ÀÄâzK ÄâzKÄâzKPÄâxIÀÄâxIÄâyIÄâ{IÈÄâ{K Äâ{K Äâ{K PÄâyK ÄâyK ÄâyK PÄâr\ÉÄâs^ÉÄâq^ÉÄâr^ÉÄâp^ÉÄâzK ÄâzK ÄâzK PÄâxIÀÄâxIÄâyIÄâ{IÐÄâ{K Äâ{KÄâ{KPÄâyK ÄâyKÄâyKPÄâj\ÒÄâk^ÒÄâi^ÒÄâj^ÒÄâh^ÒÄâzK ÄâzKÄâzKPÄâxIÀÄâxIÄâyIÄâ{IØÄâ{K Äâ{KÄâ{KPÄâyK ÄâyKÄâyKPÄâb\ÛÄâc^ÛÄâa^ÛÄâb^ÛÄâ`^ÛÄâzK ÄâzKÄâzKPÄâxIÀÄâxIÄâyIÄâ{IàÄâ{K$ Äâ{K$Äâ{K$PÄâyK$ ÄâyK$ÄâyK$PÄâZ\äÄâ[^äÄâY^äÄâZ^äÄâX^äÄâzK$ ÄâzK$ÄâzK$PÄâxIÀÄâxIÄâyIÄâ{IèÄâ{K, Äâ{K,Äâ{K,PÄâyK, ÄâyK,ÄâyK,PÄâR\íÄâS^íÄâQ^íÄâR^íÄâP^íÄâzK, ÄâzK,ÄâzK,PÄâxIÀÄâxIÄâyIÄâ{IðÄâ{K4 Äâ{K4Äâ{K4PÄâyK4 ÄâyK4ÄâyK4PÄâJ\öÄâK^öÄâI^öÄâJ^öÄâH^öÄâzK4 ÄâzK4ÄâzK4PÄâxIÀÄâxIÄâyIÄâ{IøÄâ{K< Äâ{K<Äâ{K Date: Mon, 24 Aug 2020 14:01:38 +0300 Subject: [PATCH 04/34] travis: add br3104312 Signed-off-by: Cyrill Gorcunov --- travis/test/br3104312.asm | 11 +++++++++++ travis/test/br3104312.json | 11 +++++++++++ travis/test/br3104312.stderr | 2 ++ 3 files changed, 24 insertions(+) create mode 100644 travis/test/br3104312.asm create mode 100644 travis/test/br3104312.json create mode 100644 travis/test/br3104312.stderr diff --git a/travis/test/br3104312.asm b/travis/test/br3104312.asm new file mode 100644 index 00000000..3b9509bd --- /dev/null +++ b/travis/test/br3104312.asm @@ -0,0 +1,11 @@ +%if 1 < 8000_0002h + %warning No bug with 8000_0002h +%else + %warning Bug with 8000_0002h +%endif + +%if 1 < 8000_0001h + %warning No bug with 8000_0001h +%else + %warning Bug with 8000_0001h +%endif diff --git a/travis/test/br3104312.json b/travis/test/br3104312.json new file mode 100644 index 00000000..17358171 --- /dev/null +++ b/travis/test/br3104312.json @@ -0,0 +1,11 @@ +[ + { + "description": "Test 8000_0001h and 8000_0002h bugs", + "id": "br3104312", + "source": "br3104312.asm", + "option": "-E", + "target": [ + { "stderr": "br3104312.stderr" } + ] + } +] diff --git a/travis/test/br3104312.stderr b/travis/test/br3104312.stderr new file mode 100644 index 00000000..a7fbdb69 --- /dev/null +++ b/travis/test/br3104312.stderr @@ -0,0 +1,2 @@ +./travis/test/br3104312.asm:2: warning: No bug with 8000_0002h [-w+user] +./travis/test/br3104312.asm:8: warning: No bug with 8000_0001h [-w+user] \ No newline at end of file From b2fb88596e502dcd015c2f1479d35d814abdf66d Mon Sep 17 00:00:00 2001 From: Cyrill Gorcunov Date: Mon, 24 Aug 2020 16:23:53 +0300 Subject: [PATCH 05/34] travis: add avx2 Initial conversion by nasm64developer. Signed-off-by: Cyrill Gorcunov --- travis/test/avx2.asm | 1608 ++++++++++++++++++++++++++++++++++++++++ travis/test/avx2.bin.t | Bin 0 -> 7970 bytes travis/test/avx2.json | 11 + 3 files changed, 1619 insertions(+) create mode 100644 travis/test/avx2.asm create mode 100644 travis/test/avx2.bin.t create mode 100644 travis/test/avx2.json diff --git a/travis/test/avx2.asm b/travis/test/avx2.asm new file mode 100644 index 00000000..b6228513 --- /dev/null +++ b/travis/test/avx2.asm @@ -0,0 +1,1608 @@ +; AVX testcases from gas +;------------------------ + +; +; This file is taken from there +; http://sourceware.org/ml/binutils/2011-06/msg00150.html +; So the original author is "H.J. Lu" +; +; nasm64developer adopted it for the nasm testing suite + +%macro testcase 2 + %ifdef BIN + db %1 + %endif + %ifdef SRC + %2 + %endif +%endmacro + +bits 32 + +; b/gas/testsuite/gas/i386/avx-gather-intel.d +testcase { 0xc4, 0xe2, 0xe9, 0x92, 0x4c, 0x7d, 0x00 }, { vgatherdpd xmm1,QWORD [ebp+xmm7*2+0x0],xmm2 } +testcase { 0xc4, 0xe2, 0xe9, 0x93, 0x4c, 0x7d, 0x00 }, { vgatherqpd xmm1,QWORD [ebp+xmm7*2+0x0],xmm2 } +testcase { 0xc4, 0xe2, 0xed, 0x92, 0x4c, 0x7d, 0x00 }, { vgatherdpd ymm1,QWORD [ebp+xmm7*2+0x0],ymm2 } +testcase { 0xc4, 0xe2, 0xed, 0x93, 0x4c, 0x7d, 0x00 }, { vgatherqpd ymm1,QWORD [ebp+ymm7*2+0x0],ymm2 } +testcase { 0xc4, 0xe2, 0xd5, 0x92, 0x34, 0x25, 0x08, 0x00, 0x00, 0x00 }, { vgatherdpd ymm6,QWORD [xmm4*1+0x8],ymm5 } +testcase { 0xc4, 0xe2, 0xd5, 0x92, 0x34, 0x25, 0xf8, 0xff, 0xff, 0xff }, { vgatherdpd ymm6,QWORD [xmm4*1-0x8],ymm5 } +testcase { 0xc4, 0xe2, 0xd5, 0x92, 0x34, 0x25, 0x00, 0x00, 0x00, 0x00 }, { vgatherdpd ymm6,QWORD [xmm4*1+0x0],ymm5 } +testcase { 0xc4, 0xe2, 0xd5, 0x92, 0x34, 0x25, 0x98, 0x02, 0x00, 0x00 }, { vgatherdpd ymm6,QWORD [xmm4*1+0x298],ymm5 } +testcase { 0xc4, 0xe2, 0xd5, 0x92, 0x34, 0xe5, 0x08, 0x00, 0x00, 0x00 }, { vgatherdpd ymm6,QWORD [xmm4*8+0x8],ymm5 } +testcase { 0xc4, 0xe2, 0xd5, 0x92, 0x34, 0xe5, 0xf8, 0xff, 0xff, 0xff }, { vgatherdpd ymm6,QWORD [xmm4*8-0x8],ymm5 } +testcase { 0xc4, 0xe2, 0xd5, 0x92, 0x34, 0xe5, 0x00, 0x00, 0x00, 0x00 }, { vgatherdpd ymm6,QWORD [xmm4*8+0x0],ymm5 } +testcase { 0xc4, 0xe2, 0xd5, 0x92, 0x34, 0xe5, 0x98, 0x02, 0x00, 0x00 }, { vgatherdpd ymm6,QWORD [xmm4*8+0x298],ymm5 } +testcase { 0xc4, 0xe2, 0x69, 0x92, 0x4c, 0x7d, 0x00 }, { vgatherdps xmm1,DWORD [ebp+xmm7*2+0x0],xmm2 } +testcase { 0xc4, 0xe2, 0x69, 0x93, 0x4c, 0x7d, 0x00 }, { vgatherqps xmm1,DWORD [ebp+xmm7*2+0x0],xmm2 } +testcase { 0xc4, 0xe2, 0x6d, 0x92, 0x4c, 0x7d, 0x00 }, { vgatherdps ymm1,DWORD [ebp+ymm7*2+0x0],ymm2 } +testcase { 0xc4, 0xe2, 0x6d, 0x93, 0x4c, 0x7d, 0x00 }, { vgatherqps xmm1,DWORD [ebp+ymm7*2+0x0],xmm2 } +testcase { 0xc4, 0xe2, 0x51, 0x92, 0x34, 0x25, 0x08, 0x00, 0x00, 0x00 }, { vgatherdps xmm6,DWORD [xmm4*1+0x8],xmm5 } +testcase { 0xc4, 0xe2, 0x51, 0x92, 0x34, 0x25, 0xf8, 0xff, 0xff, 0xff }, { vgatherdps xmm6,DWORD [xmm4*1-0x8],xmm5 } +testcase { 0xc4, 0xe2, 0x51, 0x92, 0x34, 0x25, 0x00, 0x00, 0x00, 0x00 }, { vgatherdps xmm6,DWORD [xmm4*1+0x0],xmm5 } +testcase { 0xc4, 0xe2, 0x51, 0x92, 0x34, 0x25, 0x98, 0x02, 0x00, 0x00 }, { vgatherdps xmm6,DWORD [xmm4*1+0x298],xmm5 } +testcase { 0xc4, 0xe2, 0x51, 0x92, 0x34, 0xe5, 0x08, 0x00, 0x00, 0x00 }, { vgatherdps xmm6,DWORD [xmm4*8+0x8],xmm5 } +testcase { 0xc4, 0xe2, 0x51, 0x92, 0x34, 0xe5, 0xf8, 0xff, 0xff, 0xff }, { vgatherdps xmm6,DWORD [xmm4*8-0x8],xmm5 } +testcase { 0xc4, 0xe2, 0x51, 0x92, 0x34, 0xe5, 0x00, 0x00, 0x00, 0x00 }, { vgatherdps xmm6,DWORD [xmm4*8+0x0],xmm5 } +testcase { 0xc4, 0xe2, 0x51, 0x92, 0x34, 0xe5, 0x98, 0x02, 0x00, 0x00 }, { vgatherdps xmm6,DWORD [xmm4*8+0x298],xmm5 } +testcase { 0xc4, 0xe2, 0x69, 0x90, 0x4c, 0x7d, 0x00 }, { vpgatherdd xmm1,DWORD [ebp+xmm7*2+0x0],xmm2 } +testcase { 0xc4, 0xe2, 0x69, 0x91, 0x4c, 0x7d, 0x00 }, { vpgatherqd xmm1,DWORD [ebp+xmm7*2+0x0],xmm2 } +testcase { 0xc4, 0xe2, 0x6d, 0x90, 0x4c, 0x7d, 0x00 }, { vpgatherdd ymm1,DWORD [ebp+ymm7*2+0x0],ymm2 } +testcase { 0xc4, 0xe2, 0x6d, 0x91, 0x4c, 0x7d, 0x00 }, { vpgatherqd xmm1,DWORD [ebp+ymm7*2+0x0],xmm2 } +testcase { 0xc4, 0xe2, 0x51, 0x90, 0x34, 0x25, 0x08, 0x00, 0x00, 0x00 }, { vpgatherdd xmm6,DWORD [xmm4*1+0x8],xmm5 } +testcase { 0xc4, 0xe2, 0x51, 0x90, 0x34, 0x25, 0xf8, 0xff, 0xff, 0xff }, { vpgatherdd xmm6,DWORD [xmm4*1-0x8],xmm5 } +testcase { 0xc4, 0xe2, 0x51, 0x90, 0x34, 0x25, 0x00, 0x00, 0x00, 0x00 }, { vpgatherdd xmm6,DWORD [xmm4*1+0x0],xmm5 } +testcase { 0xc4, 0xe2, 0x51, 0x90, 0x34, 0x25, 0x98, 0x02, 0x00, 0x00 }, { vpgatherdd xmm6,DWORD [xmm4*1+0x298],xmm5 } +testcase { 0xc4, 0xe2, 0x51, 0x90, 0x34, 0xe5, 0x08, 0x00, 0x00, 0x00 }, { vpgatherdd xmm6,DWORD [xmm4*8+0x8],xmm5 } +testcase { 0xc4, 0xe2, 0x51, 0x90, 0x34, 0xe5, 0xf8, 0xff, 0xff, 0xff }, { vpgatherdd xmm6,DWORD [xmm4*8-0x8],xmm5 } +testcase { 0xc4, 0xe2, 0x51, 0x90, 0x34, 0xe5, 0x00, 0x00, 0x00, 0x00 }, { vpgatherdd xmm6,DWORD [xmm4*8+0x0],xmm5 } +testcase { 0xc4, 0xe2, 0x51, 0x90, 0x34, 0xe5, 0x98, 0x02, 0x00, 0x00 }, { vpgatherdd xmm6,DWORD [xmm4*8+0x298],xmm5 } +testcase { 0xc4, 0xe2, 0xe9, 0x90, 0x4c, 0x7d, 0x00 }, { vpgatherdq xmm1,QWORD [ebp+xmm7*2+0x0],xmm2 } +testcase { 0xc4, 0xe2, 0xe9, 0x91, 0x4c, 0x7d, 0x00 }, { vpgatherqq xmm1,QWORD [ebp+xmm7*2+0x0],xmm2 } +testcase { 0xc4, 0xe2, 0xed, 0x90, 0x4c, 0x7d, 0x00 }, { vpgatherdq ymm1,QWORD [ebp+xmm7*2+0x0],ymm2 } +testcase { 0xc4, 0xe2, 0xed, 0x91, 0x4c, 0x7d, 0x00 }, { vpgatherqq ymm1,QWORD [ebp+ymm7*2+0x0],ymm2 } +testcase { 0xc4, 0xe2, 0xd5, 0x90, 0x34, 0x25, 0x08, 0x00, 0x00, 0x00 }, { vpgatherdq ymm6,QWORD [xmm4*1+0x8],ymm5 } +testcase { 0xc4, 0xe2, 0xd5, 0x90, 0x34, 0x25, 0xf8, 0xff, 0xff, 0xff }, { vpgatherdq ymm6,QWORD [xmm4*1-0x8],ymm5 } +testcase { 0xc4, 0xe2, 0xd5, 0x90, 0x34, 0x25, 0x00, 0x00, 0x00, 0x00 }, { vpgatherdq ymm6,QWORD [xmm4*1+0x0],ymm5 } +testcase { 0xc4, 0xe2, 0xd5, 0x90, 0x34, 0x25, 0x98, 0x02, 0x00, 0x00 }, { vpgatherdq ymm6,QWORD [xmm4*1+0x298],ymm5 } +testcase { 0xc4, 0xe2, 0xd5, 0x90, 0x34, 0xe5, 0x08, 0x00, 0x00, 0x00 }, { vpgatherdq ymm6,QWORD [xmm4*8+0x8],ymm5 } +testcase { 0xc4, 0xe2, 0xd5, 0x90, 0x34, 0xe5, 0xf8, 0xff, 0xff, 0xff }, { vpgatherdq ymm6,QWORD [xmm4*8-0x8],ymm5 } +testcase { 0xc4, 0xe2, 0xd5, 0x90, 0x34, 0xe5, 0x00, 0x00, 0x00, 0x00 }, { vpgatherdq ymm6,QWORD [xmm4*8+0x0],ymm5 } +testcase { 0xc4, 0xe2, 0xd5, 0x90, 0x34, 0xe5, 0x98, 0x02, 0x00, 0x00 }, { vpgatherdq ymm6,QWORD [xmm4*8+0x298],ymm5 } + +; b/gas/testsuite/gas/i386/avx2-intel.d +testcase { 0xc4, 0xe2, 0x5d, 0x8c, 0x31 }, { vpmaskmovd ymm6,ymm4,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x8e, 0x21 }, { vpmaskmovd YWORD [ecx],ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0xdd, 0x8c, 0x31 }, { vpmaskmovq ymm6,ymm4,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0xcd, 0x8e, 0x21 }, { vpmaskmovq YWORD [ecx],ymm6,ymm4 } +testcase { 0xc4, 0xe3, 0xfd, 0x01, 0xd6, 0x07 }, { vpermpd ymm2,ymm6,0x7 } +testcase { 0xc4, 0xe3, 0xfd, 0x01, 0x31, 0x07 }, { vpermpd ymm6,YWORD [ecx],0x7 } +testcase { 0xc4, 0xe3, 0xfd, 0x00, 0xd6, 0x07 }, { vpermq ymm2,ymm6,0x7 } +testcase { 0xc4, 0xe3, 0xfd, 0x00, 0x31, 0x07 }, { vpermq ymm6,YWORD [ecx],0x7 } +testcase { 0xc4, 0xe2, 0x4d, 0x36, 0xd4 }, { vpermd ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x36, 0x11 }, { vpermd ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x16, 0xd4 }, { vpermps ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x16, 0x11 }, { vpermps ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x47, 0xd4 }, { vpsllvd ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x47, 0x11 }, { vpsllvd ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0xcd, 0x47, 0xd4 }, { vpsllvq ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0xcd, 0x47, 0x11 }, { vpsllvq ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x46, 0xd4 }, { vpsravd ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x46, 0x11 }, { vpsravd ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x45, 0xd4 }, { vpsrlvd ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x45, 0x11 }, { vpsrlvd ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0xcd, 0x45, 0xd4 }, { vpsrlvq ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0xcd, 0x45, 0x11 }, { vpsrlvq ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x2a, 0x21 }, { vmovntdqa ymm4,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x19, 0xf4 }, { vbroadcastsd ymm6,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x18, 0xf4 }, { vbroadcastss ymm6,xmm4 } +testcase { 0xc4, 0xe3, 0x4d, 0x02, 0xd4, 0x07 }, { vpblendd ymm2,ymm6,ymm4,0x7 } +testcase { 0xc4, 0xe3, 0x4d, 0x02, 0x11, 0x07 }, { vpblendd ymm2,ymm6,YWORD [ecx],0x7 } +testcase { 0xc4, 0xe3, 0x4d, 0x46, 0xd4, 0x07 }, { vperm2i128 ymm2,ymm6,ymm4,0x7 } +testcase { 0xc4, 0xe3, 0x4d, 0x46, 0x11, 0x07 }, { vperm2i128 ymm2,ymm6,YWORD [ecx],0x7 } +testcase { 0xc4, 0xe3, 0x5d, 0x38, 0xf4, 0x07 }, { vinserti128 ymm6,ymm4,xmm4,0x7 } +testcase { 0xc4, 0xe3, 0x5d, 0x38, 0x31, 0x07 }, { vinserti128 ymm6,ymm4,OWORD [ecx],0x7 } +testcase { 0xc4, 0xe2, 0x7d, 0x5a, 0x21 }, { vbroadcasti128 ymm4,OWORD [ecx] } +testcase { 0xc4, 0xe2, 0x49, 0x47, 0xd4 }, { vpsllvd xmm2,xmm6,xmm4 } +testcase { 0xc4, 0xe2, 0x49, 0x47, 0x39 }, { vpsllvd xmm7,xmm6,OWORD [ecx] } +testcase { 0xc4, 0xe2, 0xc9, 0x47, 0xd4 }, { vpsllvq xmm2,xmm6,xmm4 } +testcase { 0xc4, 0xe2, 0xc9, 0x47, 0x39 }, { vpsllvq xmm7,xmm6,OWORD [ecx] } +testcase { 0xc4, 0xe2, 0x49, 0x46, 0xd4 }, { vpsravd xmm2,xmm6,xmm4 } +testcase { 0xc4, 0xe2, 0x49, 0x46, 0x39 }, { vpsravd xmm7,xmm6,OWORD [ecx] } +testcase { 0xc4, 0xe2, 0x49, 0x45, 0xd4 }, { vpsrlvd xmm2,xmm6,xmm4 } +testcase { 0xc4, 0xe2, 0x49, 0x45, 0x39 }, { vpsrlvd xmm7,xmm6,OWORD [ecx] } +testcase { 0xc4, 0xe2, 0xc9, 0x45, 0xd4 }, { vpsrlvq xmm2,xmm6,xmm4 } +testcase { 0xc4, 0xe2, 0xc9, 0x45, 0x39 }, { vpsrlvq xmm7,xmm6,OWORD [ecx] } +testcase { 0xc4, 0xe2, 0x59, 0x8c, 0x31 }, { vpmaskmovd xmm6,xmm4,OWORD [ecx] } +testcase { 0xc4, 0xe2, 0xd9, 0x8c, 0x31 }, { vpmaskmovq xmm6,xmm4,OWORD [ecx] } +testcase { 0xc4, 0xe3, 0x7d, 0x39, 0xe6, 0x07 }, { vextracti128 xmm6,ymm4,0x7 } +testcase { 0xc4, 0xe3, 0x7d, 0x39, 0x21, 0x07 }, { vextracti128 OWORD [ecx],ymm4,0x7 } +testcase { 0xc4, 0xe2, 0x49, 0x8e, 0x21 }, { vpmaskmovd OWORD [ecx],xmm6,xmm4 } +testcase { 0xc4, 0xe2, 0xc9, 0x8e, 0x21 }, { vpmaskmovq OWORD [ecx],xmm6,xmm4 } +testcase { 0xc4, 0xe3, 0x49, 0x02, 0xd4, 0x07 }, { vpblendd xmm2,xmm6,xmm4,0x7 } +testcase { 0xc4, 0xe3, 0x49, 0x02, 0x11, 0x07 }, { vpblendd xmm2,xmm6,OWORD [ecx],0x7 } +testcase { 0xc4, 0xe2, 0x79, 0x59, 0xf4 }, { vpbroadcastq xmm6,xmm4 } +testcase { 0xc4, 0xe2, 0x79, 0x59, 0x21 }, { vpbroadcastq xmm4,QWORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x59, 0xf4 }, { vpbroadcastq ymm6,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x59, 0x21 }, { vpbroadcastq ymm4,QWORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x58, 0xe4 }, { vpbroadcastd ymm4,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x58, 0x21 }, { vpbroadcastd ymm4,DWORD [ecx] } +testcase { 0xc4, 0xe2, 0x79, 0x58, 0xf4 }, { vpbroadcastd xmm6,xmm4 } +testcase { 0xc4, 0xe2, 0x79, 0x58, 0x21 }, { vpbroadcastd xmm4,DWORD [ecx] } +testcase { 0xc4, 0xe2, 0x79, 0x79, 0xf4 }, { vpbroadcastw xmm6,xmm4 } +testcase { 0xc4, 0xe2, 0x79, 0x79, 0x21 }, { vpbroadcastw xmm4,WORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x79, 0xf4 }, { vpbroadcastw ymm6,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x79, 0x21 }, { vpbroadcastw ymm4,WORD [ecx] } +testcase { 0xc4, 0xe2, 0x79, 0x78, 0xf4 }, { vpbroadcastb xmm6,xmm4 } +testcase { 0xc4, 0xe2, 0x79, 0x78, 0x21 }, { vpbroadcastb xmm4,BYTE [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x78, 0xf4 }, { vpbroadcastb ymm6,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x78, 0x21 }, { vpbroadcastb ymm4,BYTE [ecx] } +testcase { 0xc4, 0xe2, 0x79, 0x18, 0xf4 }, { vbroadcastss xmm6,xmm4 } +testcase { 0xc4, 0xe2, 0x5d, 0x8c, 0x31 }, { vpmaskmovd ymm6,ymm4,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x8e, 0x21 }, { vpmaskmovd YWORD [ecx],ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x5d, 0x8c, 0x31 }, { vpmaskmovd ymm6,ymm4,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x8e, 0x21 }, { vpmaskmovd YWORD [ecx],ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0xdd, 0x8c, 0x31 }, { vpmaskmovq ymm6,ymm4,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0xcd, 0x8e, 0x21 }, { vpmaskmovq YWORD [ecx],ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0xdd, 0x8c, 0x31 }, { vpmaskmovq ymm6,ymm4,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0xcd, 0x8e, 0x21 }, { vpmaskmovq YWORD [ecx],ymm6,ymm4 } +testcase { 0xc4, 0xe3, 0xfd, 0x01, 0xd6, 0x07 }, { vpermpd ymm2,ymm6,0x7 } +testcase { 0xc4, 0xe3, 0xfd, 0x01, 0x31, 0x07 }, { vpermpd ymm6,YWORD [ecx],0x7 } +testcase { 0xc4, 0xe3, 0xfd, 0x01, 0x31, 0x07 }, { vpermpd ymm6,YWORD [ecx],0x7 } +testcase { 0xc4, 0xe3, 0xfd, 0x00, 0xd6, 0x07 }, { vpermq ymm2,ymm6,0x7 } +testcase { 0xc4, 0xe3, 0xfd, 0x00, 0x31, 0x07 }, { vpermq ymm6,YWORD [ecx],0x7 } +testcase { 0xc4, 0xe3, 0xfd, 0x00, 0x31, 0x07 }, { vpermq ymm6,YWORD [ecx],0x7 } +testcase { 0xc4, 0xe2, 0x4d, 0x36, 0xd4 }, { vpermd ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x36, 0x11 }, { vpermd ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x36, 0x11 }, { vpermd ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x16, 0xd4 }, { vpermps ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x16, 0x11 }, { vpermps ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x16, 0x11 }, { vpermps ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x47, 0xd4 }, { vpsllvd ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x47, 0x11 }, { vpsllvd ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x47, 0x11 }, { vpsllvd ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0xcd, 0x47, 0xd4 }, { vpsllvq ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0xcd, 0x47, 0x11 }, { vpsllvq ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0xcd, 0x47, 0x11 }, { vpsllvq ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x46, 0xd4 }, { vpsravd ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x46, 0x11 }, { vpsravd ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x46, 0x11 }, { vpsravd ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x45, 0xd4 }, { vpsrlvd ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x45, 0x11 }, { vpsrlvd ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x45, 0x11 }, { vpsrlvd ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0xcd, 0x45, 0xd4 }, { vpsrlvq ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0xcd, 0x45, 0x11 }, { vpsrlvq ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0xcd, 0x45, 0x11 }, { vpsrlvq ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x2a, 0x21 }, { vmovntdqa ymm4,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x2a, 0x21 }, { vmovntdqa ymm4,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x19, 0xf4 }, { vbroadcastsd ymm6,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x18, 0xf4 }, { vbroadcastss ymm6,xmm4 } +testcase { 0xc4, 0xe3, 0x4d, 0x02, 0xd4, 0x07 }, { vpblendd ymm2,ymm6,ymm4,0x7 } +testcase { 0xc4, 0xe3, 0x4d, 0x02, 0x11, 0x07 }, { vpblendd ymm2,ymm6,YWORD [ecx],0x7 } +testcase { 0xc4, 0xe3, 0x4d, 0x02, 0x11, 0x07 }, { vpblendd ymm2,ymm6,YWORD [ecx],0x7 } +testcase { 0xc4, 0xe3, 0x4d, 0x46, 0xd4, 0x07 }, { vperm2i128 ymm2,ymm6,ymm4,0x7 } +testcase { 0xc4, 0xe3, 0x4d, 0x46, 0x11, 0x07 }, { vperm2i128 ymm2,ymm6,YWORD [ecx],0x7 } +testcase { 0xc4, 0xe3, 0x4d, 0x46, 0x11, 0x07 }, { vperm2i128 ymm2,ymm6,YWORD [ecx],0x7 } +testcase { 0xc4, 0xe3, 0x5d, 0x38, 0xf4, 0x07 }, { vinserti128 ymm6,ymm4,xmm4,0x7 } +testcase { 0xc4, 0xe3, 0x5d, 0x38, 0x31, 0x07 }, { vinserti128 ymm6,ymm4,OWORD [ecx],0x7 } +testcase { 0xc4, 0xe3, 0x5d, 0x38, 0x31, 0x07 }, { vinserti128 ymm6,ymm4,OWORD [ecx],0x7 } +testcase { 0xc4, 0xe2, 0x7d, 0x5a, 0x21 }, { vbroadcasti128 ymm4,OWORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x5a, 0x21 }, { vbroadcasti128 ymm4,OWORD [ecx] } +testcase { 0xc4, 0xe2, 0x49, 0x47, 0xd4 }, { vpsllvd xmm2,xmm6,xmm4 } +testcase { 0xc4, 0xe2, 0x49, 0x47, 0x39 }, { vpsllvd xmm7,xmm6,OWORD [ecx] } +testcase { 0xc4, 0xe2, 0x49, 0x47, 0x39 }, { vpsllvd xmm7,xmm6,OWORD [ecx] } +testcase { 0xc4, 0xe2, 0xc9, 0x47, 0xd4 }, { vpsllvq xmm2,xmm6,xmm4 } +testcase { 0xc4, 0xe2, 0xc9, 0x47, 0x39 }, { vpsllvq xmm7,xmm6,OWORD [ecx] } +testcase { 0xc4, 0xe2, 0xc9, 0x47, 0x39 }, { vpsllvq xmm7,xmm6,OWORD [ecx] } +testcase { 0xc4, 0xe2, 0x49, 0x46, 0xd4 }, { vpsravd xmm2,xmm6,xmm4 } +testcase { 0xc4, 0xe2, 0x49, 0x46, 0x39 }, { vpsravd xmm7,xmm6,OWORD [ecx] } +testcase { 0xc4, 0xe2, 0x49, 0x46, 0x39 }, { vpsravd xmm7,xmm6,OWORD [ecx] } +testcase { 0xc4, 0xe2, 0x49, 0x45, 0xd4 }, { vpsrlvd xmm2,xmm6,xmm4 } +testcase { 0xc4, 0xe2, 0x49, 0x45, 0x39 }, { vpsrlvd xmm7,xmm6,OWORD [ecx] } +testcase { 0xc4, 0xe2, 0x49, 0x45, 0x39 }, { vpsrlvd xmm7,xmm6,OWORD [ecx] } +testcase { 0xc4, 0xe2, 0xc9, 0x45, 0xd4 }, { vpsrlvq xmm2,xmm6,xmm4 } +testcase { 0xc4, 0xe2, 0xc9, 0x45, 0x39 }, { vpsrlvq xmm7,xmm6,OWORD [ecx] } +testcase { 0xc4, 0xe2, 0xc9, 0x45, 0x39 }, { vpsrlvq xmm7,xmm6,OWORD [ecx] } +testcase { 0xc4, 0xe2, 0x59, 0x8c, 0x31 }, { vpmaskmovd xmm6,xmm4,OWORD [ecx] } +testcase { 0xc4, 0xe2, 0x59, 0x8c, 0x31 }, { vpmaskmovd xmm6,xmm4,OWORD [ecx] } +testcase { 0xc4, 0xe2, 0xd9, 0x8c, 0x31 }, { vpmaskmovq xmm6,xmm4,OWORD [ecx] } +testcase { 0xc4, 0xe2, 0xd9, 0x8c, 0x31 }, { vpmaskmovq xmm6,xmm4,OWORD [ecx] } +testcase { 0xc4, 0xe3, 0x7d, 0x39, 0xe6, 0x07 }, { vextracti128 xmm6,ymm4,0x7 } +testcase { 0xc4, 0xe3, 0x7d, 0x39, 0x21, 0x07 }, { vextracti128 OWORD [ecx],ymm4,0x7 } +testcase { 0xc4, 0xe3, 0x7d, 0x39, 0x21, 0x07 }, { vextracti128 OWORD [ecx],ymm4,0x7 } +testcase { 0xc4, 0xe2, 0x49, 0x8e, 0x21 }, { vpmaskmovd OWORD [ecx],xmm6,xmm4 } +testcase { 0xc4, 0xe2, 0x49, 0x8e, 0x21 }, { vpmaskmovd OWORD [ecx],xmm6,xmm4 } +testcase { 0xc4, 0xe2, 0xc9, 0x8e, 0x21 }, { vpmaskmovq OWORD [ecx],xmm6,xmm4 } +testcase { 0xc4, 0xe2, 0xc9, 0x8e, 0x21 }, { vpmaskmovq OWORD [ecx],xmm6,xmm4 } +testcase { 0xc4, 0xe3, 0x49, 0x02, 0xd4, 0x07 }, { vpblendd xmm2,xmm6,xmm4,0x7 } +testcase { 0xc4, 0xe3, 0x49, 0x02, 0x11, 0x07 }, { vpblendd xmm2,xmm6,OWORD [ecx],0x7 } +testcase { 0xc4, 0xe3, 0x49, 0x02, 0x11, 0x07 }, { vpblendd xmm2,xmm6,OWORD [ecx],0x7 } +testcase { 0xc4, 0xe2, 0x79, 0x59, 0xf4 }, { vpbroadcastq xmm6,xmm4 } +testcase { 0xc4, 0xe2, 0x79, 0x59, 0x21 }, { vpbroadcastq xmm4,QWORD [ecx] } +testcase { 0xc4, 0xe2, 0x79, 0x59, 0x21 }, { vpbroadcastq xmm4,QWORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x59, 0xf4 }, { vpbroadcastq ymm6,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x59, 0x21 }, { vpbroadcastq ymm4,QWORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x59, 0x21 }, { vpbroadcastq ymm4,QWORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x58, 0xe4 }, { vpbroadcastd ymm4,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x58, 0x21 }, { vpbroadcastd ymm4,DWORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x58, 0x21 }, { vpbroadcastd ymm4,DWORD [ecx] } +testcase { 0xc4, 0xe2, 0x79, 0x58, 0xf4 }, { vpbroadcastd xmm6,xmm4 } +testcase { 0xc4, 0xe2, 0x79, 0x58, 0x21 }, { vpbroadcastd xmm4,DWORD [ecx] } +testcase { 0xc4, 0xe2, 0x79, 0x58, 0x21 }, { vpbroadcastd xmm4,DWORD [ecx] } +testcase { 0xc4, 0xe2, 0x79, 0x79, 0xf4 }, { vpbroadcastw xmm6,xmm4 } +testcase { 0xc4, 0xe2, 0x79, 0x79, 0x21 }, { vpbroadcastw xmm4,WORD [ecx] } +testcase { 0xc4, 0xe2, 0x79, 0x79, 0x21 }, { vpbroadcastw xmm4,WORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x79, 0xf4 }, { vpbroadcastw ymm6,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x79, 0x21 }, { vpbroadcastw ymm4,WORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x79, 0x21 }, { vpbroadcastw ymm4,WORD [ecx] } +testcase { 0xc4, 0xe2, 0x79, 0x78, 0xf4 }, { vpbroadcastb xmm6,xmm4 } +testcase { 0xc4, 0xe2, 0x79, 0x78, 0x21 }, { vpbroadcastb xmm4,BYTE [ecx] } +testcase { 0xc4, 0xe2, 0x79, 0x78, 0x21 }, { vpbroadcastb xmm4,BYTE [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x78, 0xf4 }, { vpbroadcastb ymm6,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x78, 0x21 }, { vpbroadcastb ymm4,BYTE [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x78, 0x21 }, { vpbroadcastb ymm4,BYTE [ecx] } +testcase { 0xc4, 0xe2, 0x79, 0x18, 0xf4 }, { vbroadcastss xmm6,xmm4 } + +; b/gas/testsuite/gas/i386/avx256int-intel.d +testcase { 0xc5, 0xfd, 0xd7, 0xcc }, { vpmovmskb ecx,ymm4 } +testcase { 0xc5, 0xed, 0x72, 0xf6, 0x07 }, { vpslld ymm2,ymm6,0x7 } +testcase { 0xc5, 0xed, 0x73, 0xfe, 0x07 }, { vpslldq ymm2,ymm6,0x7 } +testcase { 0xc5, 0xed, 0x73, 0xf6, 0x07 }, { vpsllq ymm2,ymm6,0x7 } +testcase { 0xc5, 0xed, 0x71, 0xf6, 0x07 }, { vpsllw ymm2,ymm6,0x7 } +testcase { 0xc5, 0xed, 0x72, 0xe6, 0x07 }, { vpsrad ymm2,ymm6,0x7 } +testcase { 0xc5, 0xed, 0x71, 0xe6, 0x07 }, { vpsraw ymm2,ymm6,0x7 } +testcase { 0xc5, 0xed, 0x72, 0xd6, 0x07 }, { vpsrld ymm2,ymm6,0x7 } +testcase { 0xc5, 0xed, 0x73, 0xde, 0x07 }, { vpsrldq ymm2,ymm6,0x7 } +testcase { 0xc5, 0xed, 0x73, 0xd6, 0x07 }, { vpsrlq ymm2,ymm6,0x7 } +testcase { 0xc5, 0xed, 0x71, 0xd6, 0x07 }, { vpsrlw ymm2,ymm6,0x7 } +testcase { 0xc5, 0xfd, 0x70, 0xd6, 0x07 }, { vpshufd ymm2,ymm6,0x7 } +testcase { 0xc5, 0xfd, 0x70, 0x31, 0x07 }, { vpshufd ymm6,YWORD [ecx],0x7 } +testcase { 0xc5, 0xfe, 0x70, 0xd6, 0x07 }, { vpshufhw ymm2,ymm6,0x7 } +testcase { 0xc5, 0xfe, 0x70, 0x31, 0x07 }, { vpshufhw ymm6,YWORD [ecx],0x7 } +testcase { 0xc5, 0xff, 0x70, 0xd6, 0x07 }, { vpshuflw ymm2,ymm6,0x7 } +testcase { 0xc5, 0xff, 0x70, 0x31, 0x07 }, { vpshuflw ymm6,YWORD [ecx],0x7 } +testcase { 0xc5, 0xcd, 0x6b, 0xd4 }, { vpackssdw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x6b, 0x11 }, { vpackssdw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0x63, 0xd4 }, { vpacksswb ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x63, 0x11 }, { vpacksswb ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x2b, 0xd4 }, { vpackusdw ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x2b, 0x11 }, { vpackusdw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0x67, 0xd4 }, { vpackuswb ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x67, 0x11 }, { vpackuswb ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xfc, 0xd4 }, { vpaddb ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xfc, 0x11 }, { vpaddb ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xfd, 0xd4 }, { vpaddw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xfd, 0x11 }, { vpaddw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xfe, 0xd4 }, { vpaddd ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xfe, 0x11 }, { vpaddd ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xd4, 0xd4 }, { vpaddq ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xd4, 0x11 }, { vpaddq ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xec, 0xd4 }, { vpaddsb ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xec, 0x11 }, { vpaddsb ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xed, 0xd4 }, { vpaddsw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xed, 0x11 }, { vpaddsw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xdc, 0xd4 }, { vpaddusb ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xdc, 0x11 }, { vpaddusb ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xdd, 0xd4 }, { vpaddusw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xdd, 0x11 }, { vpaddusw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xdb, 0xd4 }, { vpand ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xdb, 0x11 }, { vpand ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xdf, 0xd4 }, { vpandn ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xdf, 0x11 }, { vpandn ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xe0, 0xd4 }, { vpavgb ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xe0, 0x11 }, { vpavgb ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xe3, 0xd4 }, { vpavgw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xe3, 0x11 }, { vpavgw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0x74, 0xd4 }, { vpcmpeqb ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x74, 0x11 }, { vpcmpeqb ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0x75, 0xd4 }, { vpcmpeqw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x75, 0x11 }, { vpcmpeqw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0x76, 0xd4 }, { vpcmpeqd ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x76, 0x11 }, { vpcmpeqd ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x29, 0xd4 }, { vpcmpeqq ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x29, 0x11 }, { vpcmpeqq ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0x64, 0xd4 }, { vpcmpgtb ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x64, 0x11 }, { vpcmpgtb ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0x65, 0xd4 }, { vpcmpgtw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x65, 0x11 }, { vpcmpgtw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0x66, 0xd4 }, { vpcmpgtd ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x66, 0x11 }, { vpcmpgtd ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x37, 0xd4 }, { vpcmpgtq ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x37, 0x11 }, { vpcmpgtq ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x01, 0xd4 }, { vphaddw ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x01, 0x11 }, { vphaddw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x02, 0xd4 }, { vphaddd ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x02, 0x11 }, { vphaddd ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x03, 0xd4 }, { vphaddsw ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x03, 0x11 }, { vphaddsw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x05, 0xd4 }, { vphsubw ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x05, 0x11 }, { vphsubw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x06, 0xd4 }, { vphsubd ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x06, 0x11 }, { vphsubd ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x07, 0xd4 }, { vphsubsw ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x07, 0x11 }, { vphsubsw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xf5, 0xd4 }, { vpmaddwd ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xf5, 0x11 }, { vpmaddwd ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x04, 0xd4 }, { vpmaddubsw ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x04, 0x11 }, { vpmaddubsw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x3c, 0xd4 }, { vpmaxsb ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x3c, 0x11 }, { vpmaxsb ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xee, 0xd4 }, { vpmaxsw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xee, 0x11 }, { vpmaxsw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x3d, 0xd4 }, { vpmaxsd ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x3d, 0x11 }, { vpmaxsd ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xde, 0xd4 }, { vpmaxub ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xde, 0x11 }, { vpmaxub ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x3e, 0xd4 }, { vpmaxuw ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x3e, 0x11 }, { vpmaxuw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x3f, 0xd4 }, { vpmaxud ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x3f, 0x11 }, { vpmaxud ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x38, 0xd4 }, { vpminsb ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x38, 0x11 }, { vpminsb ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xea, 0xd4 }, { vpminsw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xea, 0x11 }, { vpminsw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x39, 0xd4 }, { vpminsd ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x39, 0x11 }, { vpminsd ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xda, 0xd4 }, { vpminub ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xda, 0x11 }, { vpminub ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x3a, 0xd4 }, { vpminuw ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x3a, 0x11 }, { vpminuw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x3b, 0xd4 }, { vpminud ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x3b, 0x11 }, { vpminud ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xe4, 0xd4 }, { vpmulhuw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xe4, 0x11 }, { vpmulhuw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x0b, 0xd4 }, { vpmulhrsw ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x0b, 0x11 }, { vpmulhrsw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xe5, 0xd4 }, { vpmulhw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xe5, 0x11 }, { vpmulhw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xd5, 0xd4 }, { vpmullw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xd5, 0x11 }, { vpmullw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x40, 0xd4 }, { vpmulld ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x40, 0x11 }, { vpmulld ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xf4, 0xd4 }, { vpmuludq ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xf4, 0x11 }, { vpmuludq ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x28, 0xd4 }, { vpmuldq ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x28, 0x11 }, { vpmuldq ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xeb, 0xd4 }, { vpor ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xeb, 0x11 }, { vpor ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xf6, 0xd4 }, { vpsadbw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xf6, 0x11 }, { vpsadbw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x00, 0xd4 }, { vpshufb ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x00, 0x11 }, { vpshufb ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x08, 0xd4 }, { vpsignb ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x08, 0x11 }, { vpsignb ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x09, 0xd4 }, { vpsignw ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x09, 0x11 }, { vpsignw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x0a, 0xd4 }, { vpsignd ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x0a, 0x11 }, { vpsignd ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xf8, 0xd4 }, { vpsubb ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xf8, 0x11 }, { vpsubb ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xf9, 0xd4 }, { vpsubw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xf9, 0x11 }, { vpsubw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xfa, 0xd4 }, { vpsubd ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xfa, 0x11 }, { vpsubd ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xfb, 0xd4 }, { vpsubq ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xfb, 0x11 }, { vpsubq ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xe8, 0xd4 }, { vpsubsb ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xe8, 0x11 }, { vpsubsb ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xe9, 0xd4 }, { vpsubsw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xe9, 0x11 }, { vpsubsw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xd8, 0xd4 }, { vpsubusb ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xd8, 0x11 }, { vpsubusb ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xd9, 0xd4 }, { vpsubusw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xd9, 0x11 }, { vpsubusw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0x68, 0xd4 }, { vpunpckhbw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x68, 0x11 }, { vpunpckhbw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0x69, 0xd4 }, { vpunpckhwd ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x69, 0x11 }, { vpunpckhwd ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0x6a, 0xd4 }, { vpunpckhdq ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x6a, 0x11 }, { vpunpckhdq ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0x6d, 0xd4 }, { vpunpckhqdq ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x6d, 0x11 }, { vpunpckhqdq ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0x60, 0xd4 }, { vpunpcklbw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x60, 0x11 }, { vpunpcklbw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0x61, 0xd4 }, { vpunpcklwd ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x61, 0x11 }, { vpunpcklwd ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0x62, 0xd4 }, { vpunpckldq ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x62, 0x11 }, { vpunpckldq ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0x6c, 0xd4 }, { vpunpcklqdq ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x6c, 0x11 }, { vpunpcklqdq ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xef, 0xd4 }, { vpxor ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xef, 0x11 }, { vpxor ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x1c, 0xf4 }, { vpabsb ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x1c, 0x21 }, { vpabsb ymm4,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x1d, 0xf4 }, { vpabsw ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x1d, 0x21 }, { vpabsw ymm4,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x1e, 0xf4 }, { vpabsd ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x1e, 0x21 }, { vpabsd ymm4,YWORD [ecx] } +testcase { 0xc4, 0xe3, 0x4d, 0x42, 0xd4, 0x07 }, { vmpsadbw ymm2,ymm6,ymm4,0x7 } +testcase { 0xc4, 0xe3, 0x4d, 0x42, 0x11, 0x07 }, { vmpsadbw ymm2,ymm6,YWORD [ecx],0x7 } +testcase { 0xc4, 0xe3, 0x4d, 0x0f, 0xd4, 0x07 }, { vpalignr ymm2,ymm6,ymm4,0x7 } +testcase { 0xc4, 0xe3, 0x4d, 0x0f, 0x11, 0x07 }, { vpalignr ymm2,ymm6,YWORD [ecx],0x7 } +testcase { 0xc4, 0xe3, 0x4d, 0x0e, 0xd4, 0x07 }, { vpblendw ymm2,ymm6,ymm4,0x7 } +testcase { 0xc4, 0xe3, 0x4d, 0x0e, 0x11, 0x07 }, { vpblendw ymm2,ymm6,YWORD [ecx],0x7 } +testcase { 0xc4, 0xe3, 0x6d, 0x4c, 0xfe, 0x40 }, { vpblendvb ymm7,ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe3, 0x6d, 0x4c, 0x39, 0x40 }, { vpblendvb ymm7,ymm2,YWORD [ecx],ymm4 } +testcase { 0xc5, 0xcd, 0xf1, 0xd4 }, { vpsllw ymm2,ymm6,xmm4 } +testcase { 0xc5, 0xcd, 0xf1, 0x11 }, { vpsllw ymm2,ymm6,OWORD [ecx] } +testcase { 0xc5, 0xcd, 0xf2, 0xd4 }, { vpslld ymm2,ymm6,xmm4 } +testcase { 0xc5, 0xcd, 0xf2, 0x11 }, { vpslld ymm2,ymm6,OWORD [ecx] } +testcase { 0xc5, 0xcd, 0xf3, 0xd4 }, { vpsllq ymm2,ymm6,xmm4 } +testcase { 0xc5, 0xcd, 0xf3, 0x11 }, { vpsllq ymm2,ymm6,OWORD [ecx] } +testcase { 0xc5, 0xcd, 0xe1, 0xd4 }, { vpsraw ymm2,ymm6,xmm4 } +testcase { 0xc5, 0xcd, 0xe1, 0x11 }, { vpsraw ymm2,ymm6,OWORD [ecx] } +testcase { 0xc5, 0xcd, 0xe2, 0xd4 }, { vpsrad ymm2,ymm6,xmm4 } +testcase { 0xc5, 0xcd, 0xe2, 0x11 }, { vpsrad ymm2,ymm6,OWORD [ecx] } +testcase { 0xc5, 0xcd, 0xd1, 0xd4 }, { vpsrlw ymm2,ymm6,xmm4 } +testcase { 0xc5, 0xcd, 0xd1, 0x11 }, { vpsrlw ymm2,ymm6,OWORD [ecx] } +testcase { 0xc5, 0xcd, 0xd2, 0xd4 }, { vpsrld ymm2,ymm6,xmm4 } +testcase { 0xc5, 0xcd, 0xd2, 0x11 }, { vpsrld ymm2,ymm6,OWORD [ecx] } +testcase { 0xc5, 0xcd, 0xd3, 0xd4 }, { vpsrlq ymm2,ymm6,xmm4 } +testcase { 0xc5, 0xcd, 0xd3, 0x11 }, { vpsrlq ymm2,ymm6,OWORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x20, 0xe4 }, { vpmovsxbw ymm4,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x20, 0x21 }, { vpmovsxbw ymm4,OWORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x23, 0xe4 }, { vpmovsxwd ymm4,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x23, 0x21 }, { vpmovsxwd ymm4,OWORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x25, 0xe4 }, { vpmovsxdq ymm4,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x25, 0x21 }, { vpmovsxdq ymm4,OWORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x30, 0xe4 }, { vpmovzxbw ymm4,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x30, 0x21 }, { vpmovzxbw ymm4,OWORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x33, 0xe4 }, { vpmovzxwd ymm4,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x33, 0x21 }, { vpmovzxwd ymm4,OWORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x35, 0xe4 }, { vpmovzxdq ymm4,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x35, 0x21 }, { vpmovzxdq ymm4,OWORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x21, 0xf4 }, { vpmovsxbd ymm6,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x21, 0x21 }, { vpmovsxbd ymm4,QWORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x24, 0xf4 }, { vpmovsxwq ymm6,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x24, 0x21 }, { vpmovsxwq ymm4,QWORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x31, 0xf4 }, { vpmovzxbd ymm6,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x31, 0x21 }, { vpmovzxbd ymm4,QWORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x34, 0xf4 }, { vpmovzxwq ymm6,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x34, 0x21 }, { vpmovzxwq ymm4,QWORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x22, 0xe4 }, { vpmovsxbq ymm4,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x22, 0x21 }, { vpmovsxbq ymm4,DWORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x32, 0xe4 }, { vpmovzxbq ymm4,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x32, 0x21 }, { vpmovzxbq ymm4,DWORD [ecx] } +testcase { 0xc5, 0xfd, 0xd7, 0xcc }, { vpmovmskb ecx,ymm4 } +testcase { 0xc5, 0xed, 0x72, 0xf6, 0x07 }, { vpslld ymm2,ymm6,0x7 } +testcase { 0xc5, 0xed, 0x73, 0xfe, 0x07 }, { vpslldq ymm2,ymm6,0x7 } +testcase { 0xc5, 0xed, 0x73, 0xf6, 0x07 }, { vpsllq ymm2,ymm6,0x7 } +testcase { 0xc5, 0xed, 0x71, 0xf6, 0x07 }, { vpsllw ymm2,ymm6,0x7 } +testcase { 0xc5, 0xed, 0x72, 0xe6, 0x07 }, { vpsrad ymm2,ymm6,0x7 } +testcase { 0xc5, 0xed, 0x71, 0xe6, 0x07 }, { vpsraw ymm2,ymm6,0x7 } +testcase { 0xc5, 0xed, 0x72, 0xd6, 0x07 }, { vpsrld ymm2,ymm6,0x7 } +testcase { 0xc5, 0xed, 0x73, 0xde, 0x07 }, { vpsrldq ymm2,ymm6,0x7 } +testcase { 0xc5, 0xed, 0x73, 0xd6, 0x07 }, { vpsrlq ymm2,ymm6,0x7 } +testcase { 0xc5, 0xed, 0x71, 0xd6, 0x07 }, { vpsrlw ymm2,ymm6,0x7 } +testcase { 0xc5, 0xfd, 0x70, 0xd6, 0x07 }, { vpshufd ymm2,ymm6,0x7 } +testcase { 0xc5, 0xfd, 0x70, 0x31, 0x07 }, { vpshufd ymm6,YWORD [ecx],0x7 } +testcase { 0xc5, 0xfd, 0x70, 0x31, 0x07 }, { vpshufd ymm6,YWORD [ecx],0x7 } +testcase { 0xc5, 0xfe, 0x70, 0xd6, 0x07 }, { vpshufhw ymm2,ymm6,0x7 } +testcase { 0xc5, 0xfe, 0x70, 0x31, 0x07 }, { vpshufhw ymm6,YWORD [ecx],0x7 } +testcase { 0xc5, 0xfe, 0x70, 0x31, 0x07 }, { vpshufhw ymm6,YWORD [ecx],0x7 } +testcase { 0xc5, 0xff, 0x70, 0xd6, 0x07 }, { vpshuflw ymm2,ymm6,0x7 } +testcase { 0xc5, 0xff, 0x70, 0x31, 0x07 }, { vpshuflw ymm6,YWORD [ecx],0x7 } +testcase { 0xc5, 0xff, 0x70, 0x31, 0x07 }, { vpshuflw ymm6,YWORD [ecx],0x7 } +testcase { 0xc5, 0xcd, 0x6b, 0xd4 }, { vpackssdw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x6b, 0x11 }, { vpackssdw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0x6b, 0x11 }, { vpackssdw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0x63, 0xd4 }, { vpacksswb ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x63, 0x11 }, { vpacksswb ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0x63, 0x11 }, { vpacksswb ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x2b, 0xd4 }, { vpackusdw ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x2b, 0x11 }, { vpackusdw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x2b, 0x11 }, { vpackusdw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0x67, 0xd4 }, { vpackuswb ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x67, 0x11 }, { vpackuswb ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0x67, 0x11 }, { vpackuswb ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xfc, 0xd4 }, { vpaddb ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xfc, 0x11 }, { vpaddb ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xfc, 0x11 }, { vpaddb ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xfd, 0xd4 }, { vpaddw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xfd, 0x11 }, { vpaddw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xfd, 0x11 }, { vpaddw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xfe, 0xd4 }, { vpaddd ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xfe, 0x11 }, { vpaddd ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xfe, 0x11 }, { vpaddd ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xd4, 0xd4 }, { vpaddq ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xd4, 0x11 }, { vpaddq ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xd4, 0x11 }, { vpaddq ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xec, 0xd4 }, { vpaddsb ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xec, 0x11 }, { vpaddsb ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xec, 0x11 }, { vpaddsb ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xed, 0xd4 }, { vpaddsw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xed, 0x11 }, { vpaddsw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xed, 0x11 }, { vpaddsw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xdc, 0xd4 }, { vpaddusb ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xdc, 0x11 }, { vpaddusb ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xdc, 0x11 }, { vpaddusb ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xdd, 0xd4 }, { vpaddusw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xdd, 0x11 }, { vpaddusw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xdd, 0x11 }, { vpaddusw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xdb, 0xd4 }, { vpand ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xdb, 0x11 }, { vpand ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xdb, 0x11 }, { vpand ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xdf, 0xd4 }, { vpandn ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xdf, 0x11 }, { vpandn ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xdf, 0x11 }, { vpandn ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xe0, 0xd4 }, { vpavgb ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xe0, 0x11 }, { vpavgb ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xe0, 0x11 }, { vpavgb ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xe3, 0xd4 }, { vpavgw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xe3, 0x11 }, { vpavgw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xe3, 0x11 }, { vpavgw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0x74, 0xd4 }, { vpcmpeqb ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x74, 0x11 }, { vpcmpeqb ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0x74, 0x11 }, { vpcmpeqb ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0x75, 0xd4 }, { vpcmpeqw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x75, 0x11 }, { vpcmpeqw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0x75, 0x11 }, { vpcmpeqw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0x76, 0xd4 }, { vpcmpeqd ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x76, 0x11 }, { vpcmpeqd ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0x76, 0x11 }, { vpcmpeqd ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x29, 0xd4 }, { vpcmpeqq ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x29, 0x11 }, { vpcmpeqq ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x29, 0x11 }, { vpcmpeqq ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0x64, 0xd4 }, { vpcmpgtb ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x64, 0x11 }, { vpcmpgtb ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0x64, 0x11 }, { vpcmpgtb ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0x65, 0xd4 }, { vpcmpgtw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x65, 0x11 }, { vpcmpgtw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0x65, 0x11 }, { vpcmpgtw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0x66, 0xd4 }, { vpcmpgtd ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x66, 0x11 }, { vpcmpgtd ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0x66, 0x11 }, { vpcmpgtd ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x37, 0xd4 }, { vpcmpgtq ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x37, 0x11 }, { vpcmpgtq ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x37, 0x11 }, { vpcmpgtq ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x01, 0xd4 }, { vphaddw ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x01, 0x11 }, { vphaddw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x01, 0x11 }, { vphaddw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x02, 0xd4 }, { vphaddd ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x02, 0x11 }, { vphaddd ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x02, 0x11 }, { vphaddd ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x03, 0xd4 }, { vphaddsw ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x03, 0x11 }, { vphaddsw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x03, 0x11 }, { vphaddsw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x05, 0xd4 }, { vphsubw ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x05, 0x11 }, { vphsubw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x05, 0x11 }, { vphsubw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x06, 0xd4 }, { vphsubd ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x06, 0x11 }, { vphsubd ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x06, 0x11 }, { vphsubd ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x07, 0xd4 }, { vphsubsw ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x07, 0x11 }, { vphsubsw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x07, 0x11 }, { vphsubsw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xf5, 0xd4 }, { vpmaddwd ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xf5, 0x11 }, { vpmaddwd ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xf5, 0x11 }, { vpmaddwd ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x04, 0xd4 }, { vpmaddubsw ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x04, 0x11 }, { vpmaddubsw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x04, 0x11 }, { vpmaddubsw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x3c, 0xd4 }, { vpmaxsb ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x3c, 0x11 }, { vpmaxsb ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x3c, 0x11 }, { vpmaxsb ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xee, 0xd4 }, { vpmaxsw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xee, 0x11 }, { vpmaxsw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xee, 0x11 }, { vpmaxsw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x3d, 0xd4 }, { vpmaxsd ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x3d, 0x11 }, { vpmaxsd ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x3d, 0x11 }, { vpmaxsd ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xde, 0xd4 }, { vpmaxub ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xde, 0x11 }, { vpmaxub ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xde, 0x11 }, { vpmaxub ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x3e, 0xd4 }, { vpmaxuw ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x3e, 0x11 }, { vpmaxuw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x3e, 0x11 }, { vpmaxuw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x3f, 0xd4 }, { vpmaxud ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x3f, 0x11 }, { vpmaxud ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x3f, 0x11 }, { vpmaxud ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x38, 0xd4 }, { vpminsb ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x38, 0x11 }, { vpminsb ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x38, 0x11 }, { vpminsb ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xea, 0xd4 }, { vpminsw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xea, 0x11 }, { vpminsw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xea, 0x11 }, { vpminsw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x39, 0xd4 }, { vpminsd ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x39, 0x11 }, { vpminsd ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x39, 0x11 }, { vpminsd ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xda, 0xd4 }, { vpminub ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xda, 0x11 }, { vpminub ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xda, 0x11 }, { vpminub ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x3a, 0xd4 }, { vpminuw ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x3a, 0x11 }, { vpminuw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x3a, 0x11 }, { vpminuw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x3b, 0xd4 }, { vpminud ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x3b, 0x11 }, { vpminud ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x3b, 0x11 }, { vpminud ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xe4, 0xd4 }, { vpmulhuw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xe4, 0x11 }, { vpmulhuw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xe4, 0x11 }, { vpmulhuw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x0b, 0xd4 }, { vpmulhrsw ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x0b, 0x11 }, { vpmulhrsw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x0b, 0x11 }, { vpmulhrsw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xe5, 0xd4 }, { vpmulhw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xe5, 0x11 }, { vpmulhw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xe5, 0x11 }, { vpmulhw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xd5, 0xd4 }, { vpmullw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xd5, 0x11 }, { vpmullw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xd5, 0x11 }, { vpmullw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x40, 0xd4 }, { vpmulld ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x40, 0x11 }, { vpmulld ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x40, 0x11 }, { vpmulld ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xf4, 0xd4 }, { vpmuludq ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xf4, 0x11 }, { vpmuludq ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xf4, 0x11 }, { vpmuludq ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x28, 0xd4 }, { vpmuldq ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x28, 0x11 }, { vpmuldq ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x28, 0x11 }, { vpmuldq ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xeb, 0xd4 }, { vpor ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xeb, 0x11 }, { vpor ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xeb, 0x11 }, { vpor ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xf6, 0xd4 }, { vpsadbw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xf6, 0x11 }, { vpsadbw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xf6, 0x11 }, { vpsadbw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x00, 0xd4 }, { vpshufb ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x00, 0x11 }, { vpshufb ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x00, 0x11 }, { vpshufb ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x08, 0xd4 }, { vpsignb ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x08, 0x11 }, { vpsignb ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x08, 0x11 }, { vpsignb ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x09, 0xd4 }, { vpsignw ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x09, 0x11 }, { vpsignw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x09, 0x11 }, { vpsignw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x0a, 0xd4 }, { vpsignd ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x0a, 0x11 }, { vpsignd ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x4d, 0x0a, 0x11 }, { vpsignd ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xf8, 0xd4 }, { vpsubb ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xf8, 0x11 }, { vpsubb ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xf8, 0x11 }, { vpsubb ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xf9, 0xd4 }, { vpsubw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xf9, 0x11 }, { vpsubw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xf9, 0x11 }, { vpsubw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xfa, 0xd4 }, { vpsubd ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xfa, 0x11 }, { vpsubd ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xfa, 0x11 }, { vpsubd ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xfb, 0xd4 }, { vpsubq ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xfb, 0x11 }, { vpsubq ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xfb, 0x11 }, { vpsubq ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xe8, 0xd4 }, { vpsubsb ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xe8, 0x11 }, { vpsubsb ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xe8, 0x11 }, { vpsubsb ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xe9, 0xd4 }, { vpsubsw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xe9, 0x11 }, { vpsubsw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xe9, 0x11 }, { vpsubsw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xd8, 0xd4 }, { vpsubusb ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xd8, 0x11 }, { vpsubusb ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xd8, 0x11 }, { vpsubusb ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xd9, 0xd4 }, { vpsubusw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xd9, 0x11 }, { vpsubusw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xd9, 0x11 }, { vpsubusw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0x68, 0xd4 }, { vpunpckhbw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x68, 0x11 }, { vpunpckhbw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0x68, 0x11 }, { vpunpckhbw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0x69, 0xd4 }, { vpunpckhwd ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x69, 0x11 }, { vpunpckhwd ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0x69, 0x11 }, { vpunpckhwd ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0x6a, 0xd4 }, { vpunpckhdq ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x6a, 0x11 }, { vpunpckhdq ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0x6a, 0x11 }, { vpunpckhdq ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0x6d, 0xd4 }, { vpunpckhqdq ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x6d, 0x11 }, { vpunpckhqdq ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0x6d, 0x11 }, { vpunpckhqdq ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0x60, 0xd4 }, { vpunpcklbw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x60, 0x11 }, { vpunpcklbw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0x60, 0x11 }, { vpunpcklbw ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0x61, 0xd4 }, { vpunpcklwd ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x61, 0x11 }, { vpunpcklwd ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0x61, 0x11 }, { vpunpcklwd ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0x62, 0xd4 }, { vpunpckldq ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x62, 0x11 }, { vpunpckldq ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0x62, 0x11 }, { vpunpckldq ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0x6c, 0xd4 }, { vpunpcklqdq ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x6c, 0x11 }, { vpunpcklqdq ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0x6c, 0x11 }, { vpunpcklqdq ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xef, 0xd4 }, { vpxor ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xef, 0x11 }, { vpxor ymm2,ymm6,YWORD [ecx] } +testcase { 0xc5, 0xcd, 0xef, 0x11 }, { vpxor ymm2,ymm6,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x1c, 0xf4 }, { vpabsb ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x1c, 0x21 }, { vpabsb ymm4,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x1c, 0x21 }, { vpabsb ymm4,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x1d, 0xf4 }, { vpabsw ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x1d, 0x21 }, { vpabsw ymm4,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x1d, 0x21 }, { vpabsw ymm4,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x1e, 0xf4 }, { vpabsd ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x1e, 0x21 }, { vpabsd ymm4,YWORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x1e, 0x21 }, { vpabsd ymm4,YWORD [ecx] } +testcase { 0xc4, 0xe3, 0x4d, 0x42, 0xd4, 0x07 }, { vmpsadbw ymm2,ymm6,ymm4,0x7 } +testcase { 0xc4, 0xe3, 0x4d, 0x42, 0x11, 0x07 }, { vmpsadbw ymm2,ymm6,YWORD [ecx],0x7 } +testcase { 0xc4, 0xe3, 0x4d, 0x42, 0x11, 0x07 }, { vmpsadbw ymm2,ymm6,YWORD [ecx],0x7 } +testcase { 0xc4, 0xe3, 0x4d, 0x0f, 0xd4, 0x07 }, { vpalignr ymm2,ymm6,ymm4,0x7 } +testcase { 0xc4, 0xe3, 0x4d, 0x0f, 0x11, 0x07 }, { vpalignr ymm2,ymm6,YWORD [ecx],0x7 } +testcase { 0xc4, 0xe3, 0x4d, 0x0f, 0x11, 0x07 }, { vpalignr ymm2,ymm6,YWORD [ecx],0x7 } +testcase { 0xc4, 0xe3, 0x4d, 0x0e, 0xd4, 0x07 }, { vpblendw ymm2,ymm6,ymm4,0x7 } +testcase { 0xc4, 0xe3, 0x4d, 0x0e, 0x11, 0x07 }, { vpblendw ymm2,ymm6,YWORD [ecx],0x7 } +testcase { 0xc4, 0xe3, 0x4d, 0x0e, 0x11, 0x07 }, { vpblendw ymm2,ymm6,YWORD [ecx],0x7 } +testcase { 0xc4, 0xe3, 0x6d, 0x4c, 0xfe, 0x40 }, { vpblendvb ymm7,ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe3, 0x6d, 0x4c, 0x39, 0x40 }, { vpblendvb ymm7,ymm2,YWORD [ecx],ymm4 } +testcase { 0xc4, 0xe3, 0x6d, 0x4c, 0x39, 0x40 }, { vpblendvb ymm7,ymm2,YWORD [ecx],ymm4 } +testcase { 0xc5, 0xcd, 0xf1, 0xd4 }, { vpsllw ymm2,ymm6,xmm4 } +testcase { 0xc5, 0xcd, 0xf1, 0x11 }, { vpsllw ymm2,ymm6,OWORD [ecx] } +testcase { 0xc5, 0xcd, 0xf1, 0x11 }, { vpsllw ymm2,ymm6,OWORD [ecx] } +testcase { 0xc5, 0xcd, 0xf2, 0xd4 }, { vpslld ymm2,ymm6,xmm4 } +testcase { 0xc5, 0xcd, 0xf2, 0x11 }, { vpslld ymm2,ymm6,OWORD [ecx] } +testcase { 0xc5, 0xcd, 0xf2, 0x11 }, { vpslld ymm2,ymm6,OWORD [ecx] } +testcase { 0xc5, 0xcd, 0xf3, 0xd4 }, { vpsllq ymm2,ymm6,xmm4 } +testcase { 0xc5, 0xcd, 0xf3, 0x11 }, { vpsllq ymm2,ymm6,OWORD [ecx] } +testcase { 0xc5, 0xcd, 0xf3, 0x11 }, { vpsllq ymm2,ymm6,OWORD [ecx] } +testcase { 0xc5, 0xcd, 0xe1, 0xd4 }, { vpsraw ymm2,ymm6,xmm4 } +testcase { 0xc5, 0xcd, 0xe1, 0x11 }, { vpsraw ymm2,ymm6,OWORD [ecx] } +testcase { 0xc5, 0xcd, 0xe1, 0x11 }, { vpsraw ymm2,ymm6,OWORD [ecx] } +testcase { 0xc5, 0xcd, 0xe2, 0xd4 }, { vpsrad ymm2,ymm6,xmm4 } +testcase { 0xc5, 0xcd, 0xe2, 0x11 }, { vpsrad ymm2,ymm6,OWORD [ecx] } +testcase { 0xc5, 0xcd, 0xe2, 0x11 }, { vpsrad ymm2,ymm6,OWORD [ecx] } +testcase { 0xc5, 0xcd, 0xd1, 0xd4 }, { vpsrlw ymm2,ymm6,xmm4 } +testcase { 0xc5, 0xcd, 0xd1, 0x11 }, { vpsrlw ymm2,ymm6,OWORD [ecx] } +testcase { 0xc5, 0xcd, 0xd1, 0x11 }, { vpsrlw ymm2,ymm6,OWORD [ecx] } +testcase { 0xc5, 0xcd, 0xd2, 0xd4 }, { vpsrld ymm2,ymm6,xmm4 } +testcase { 0xc5, 0xcd, 0xd2, 0x11 }, { vpsrld ymm2,ymm6,OWORD [ecx] } +testcase { 0xc5, 0xcd, 0xd2, 0x11 }, { vpsrld ymm2,ymm6,OWORD [ecx] } +testcase { 0xc5, 0xcd, 0xd3, 0xd4 }, { vpsrlq ymm2,ymm6,xmm4 } +testcase { 0xc5, 0xcd, 0xd3, 0x11 }, { vpsrlq ymm2,ymm6,OWORD [ecx] } +testcase { 0xc5, 0xcd, 0xd3, 0x11 }, { vpsrlq ymm2,ymm6,OWORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x20, 0xe4 }, { vpmovsxbw ymm4,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x20, 0x21 }, { vpmovsxbw ymm4,OWORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x20, 0x21 }, { vpmovsxbw ymm4,OWORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x23, 0xe4 }, { vpmovsxwd ymm4,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x23, 0x21 }, { vpmovsxwd ymm4,OWORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x23, 0x21 }, { vpmovsxwd ymm4,OWORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x25, 0xe4 }, { vpmovsxdq ymm4,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x25, 0x21 }, { vpmovsxdq ymm4,OWORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x25, 0x21 }, { vpmovsxdq ymm4,OWORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x30, 0xe4 }, { vpmovzxbw ymm4,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x30, 0x21 }, { vpmovzxbw ymm4,OWORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x30, 0x21 }, { vpmovzxbw ymm4,OWORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x33, 0xe4 }, { vpmovzxwd ymm4,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x33, 0x21 }, { vpmovzxwd ymm4,OWORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x33, 0x21 }, { vpmovzxwd ymm4,OWORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x35, 0xe4 }, { vpmovzxdq ymm4,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x35, 0x21 }, { vpmovzxdq ymm4,OWORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x35, 0x21 }, { vpmovzxdq ymm4,OWORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x21, 0xf4 }, { vpmovsxbd ymm6,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x21, 0x21 }, { vpmovsxbd ymm4,QWORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x21, 0x21 }, { vpmovsxbd ymm4,QWORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x24, 0xf4 }, { vpmovsxwq ymm6,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x24, 0x21 }, { vpmovsxwq ymm4,QWORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x24, 0x21 }, { vpmovsxwq ymm4,QWORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x31, 0xf4 }, { vpmovzxbd ymm6,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x31, 0x21 }, { vpmovzxbd ymm4,QWORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x31, 0x21 }, { vpmovzxbd ymm4,QWORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x34, 0xf4 }, { vpmovzxwq ymm6,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x34, 0x21 }, { vpmovzxwq ymm4,QWORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x34, 0x21 }, { vpmovzxwq ymm4,QWORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x22, 0xe4 }, { vpmovsxbq ymm4,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x22, 0x21 }, { vpmovsxbq ymm4,DWORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x22, 0x21 }, { vpmovsxbq ymm4,DWORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x32, 0xe4 }, { vpmovzxbq ymm4,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x32, 0x21 }, { vpmovzxbq ymm4,DWORD [ecx] } +testcase { 0xc4, 0xe2, 0x7d, 0x32, 0x21 }, { vpmovzxbq ymm4,DWORD [ecx] } + +bits 64 + +; b/gas/testsuite/gas/i386/x86-64-avx-gather-intel.d +testcase { 0xc4, 0xe2, 0xe9, 0x92, 0x4c, 0x7d, 0x00 }, { vgatherdpd xmm1,QWORD [rbp+xmm7*2+0x0],xmm2 } +testcase { 0xc4, 0xe2, 0xe9, 0x93, 0x4c, 0x7d, 0x00 }, { vgatherqpd xmm1,QWORD [rbp+xmm7*2+0x0],xmm2 } +testcase { 0xc4, 0xe2, 0xed, 0x92, 0x4c, 0x7d, 0x00 }, { vgatherdpd ymm1,QWORD [rbp+xmm7*2+0x0],ymm2 } +testcase { 0xc4, 0xe2, 0xed, 0x93, 0x4c, 0x7d, 0x00 }, { vgatherqpd ymm1,QWORD [rbp+ymm7*2+0x0],ymm2 } +testcase { 0xc4, 0x02, 0x99, 0x92, 0x5c, 0x75, 0x00 }, { vgatherdpd xmm11,QWORD [r13+xmm14*2+0x0],xmm12 } +testcase { 0xc4, 0x02, 0x99, 0x93, 0x5c, 0x75, 0x00 }, { vgatherqpd xmm11,QWORD [r13+xmm14*2+0x0],xmm12 } +testcase { 0xc4, 0x02, 0x9d, 0x92, 0x5c, 0x75, 0x00 }, { vgatherdpd ymm11,QWORD [r13+xmm14*2+0x0],ymm12 } +testcase { 0xc4, 0x02, 0x9d, 0x93, 0x5c, 0x75, 0x00 }, { vgatherqpd ymm11,QWORD [r13+ymm14*2+0x0],ymm12 } +testcase { 0xc4, 0xe2, 0xd5, 0x92, 0x34, 0x25, 0x08, 0x00, 0x00, 0x00 }, { vgatherdpd ymm6,QWORD [xmm4*1+0x8],ymm5 } +testcase { 0xc4, 0xe2, 0xd5, 0x92, 0x34, 0x25, 0xf8, 0xff, 0xff, 0xff }, { vgatherdpd ymm6,QWORD [xmm4*1-0x8],ymm5 } +testcase { 0xc4, 0xe2, 0xd5, 0x92, 0x34, 0x25, 0x00, 0x00, 0x00, 0x00 }, { vgatherdpd ymm6,QWORD [xmm4*1+0x0],ymm5 } +testcase { 0xc4, 0xe2, 0xd5, 0x92, 0x34, 0x25, 0x98, 0x02, 0x00, 0x00 }, { vgatherdpd ymm6,QWORD [xmm4*1+0x298],ymm5 } +testcase { 0xc4, 0xe2, 0xd5, 0x92, 0x34, 0xe5, 0x08, 0x00, 0x00, 0x00 }, { vgatherdpd ymm6,QWORD [xmm4*8+0x8],ymm5 } +testcase { 0xc4, 0xe2, 0xd5, 0x92, 0x34, 0xe5, 0xf8, 0xff, 0xff, 0xff }, { vgatherdpd ymm6,QWORD [xmm4*8-0x8],ymm5 } +testcase { 0xc4, 0xe2, 0xd5, 0x92, 0x34, 0xe5, 0x00, 0x00, 0x00, 0x00 }, { vgatherdpd ymm6,QWORD [xmm4*8+0x0],ymm5 } +testcase { 0xc4, 0xe2, 0xd5, 0x92, 0x34, 0xe5, 0x98, 0x02, 0x00, 0x00 }, { vgatherdpd ymm6,QWORD [xmm4*8+0x298],ymm5 } +testcase { 0xc4, 0xa2, 0xd5, 0x92, 0x34, 0x35, 0x08, 0x00, 0x00, 0x00 }, { vgatherdpd ymm6,QWORD [xmm14*1+0x8],ymm5 } +testcase { 0xc4, 0xa2, 0xd5, 0x92, 0x34, 0x35, 0xf8, 0xff, 0xff, 0xff }, { vgatherdpd ymm6,QWORD [xmm14*1-0x8],ymm5 } +testcase { 0xc4, 0xa2, 0xd5, 0x92, 0x34, 0x35, 0x00, 0x00, 0x00, 0x00 }, { vgatherdpd ymm6,QWORD [xmm14*1+0x0],ymm5 } +testcase { 0xc4, 0xa2, 0xd5, 0x92, 0x34, 0x35, 0x98, 0x02, 0x00, 0x00 }, { vgatherdpd ymm6,QWORD [xmm14*1+0x298],ymm5 } +testcase { 0xc4, 0xa2, 0xd5, 0x92, 0x34, 0xf5, 0x08, 0x00, 0x00, 0x00 }, { vgatherdpd ymm6,QWORD [xmm14*8+0x8],ymm5 } +testcase { 0xc4, 0xa2, 0xd5, 0x92, 0x34, 0xf5, 0xf8, 0xff, 0xff, 0xff }, { vgatherdpd ymm6,QWORD [xmm14*8-0x8],ymm5 } +testcase { 0xc4, 0xa2, 0xd5, 0x92, 0x34, 0xf5, 0x00, 0x00, 0x00, 0x00 }, { vgatherdpd ymm6,QWORD [xmm14*8+0x0],ymm5 } +testcase { 0xc4, 0xa2, 0xd5, 0x92, 0x34, 0xf5, 0x98, 0x02, 0x00, 0x00 }, { vgatherdpd ymm6,QWORD [xmm14*8+0x298],ymm5 } +testcase { 0xc4, 0xe2, 0x69, 0x92, 0x4c, 0x7d, 0x00 }, { vgatherdps xmm1,DWORD [rbp+xmm7*2+0x0],xmm2 } +testcase { 0xc4, 0xe2, 0x69, 0x93, 0x4c, 0x7d, 0x00 }, { vgatherqps xmm1,DWORD [rbp+xmm7*2+0x0],xmm2 } +testcase { 0xc4, 0xe2, 0x6d, 0x92, 0x4c, 0x7d, 0x00 }, { vgatherdps ymm1,DWORD [rbp+ymm7*2+0x0],ymm2 } +testcase { 0xc4, 0xe2, 0x6d, 0x93, 0x4c, 0x7d, 0x00 }, { vgatherqps xmm1,DWORD [rbp+ymm7*2+0x0],xmm2 } +testcase { 0xc4, 0x02, 0x19, 0x92, 0x5c, 0x75, 0x00 }, { vgatherdps xmm11,DWORD [r13+xmm14*2+0x0],xmm12 } +testcase { 0xc4, 0x02, 0x19, 0x93, 0x5c, 0x75, 0x00 }, { vgatherqps xmm11,DWORD [r13+xmm14*2+0x0],xmm12 } +testcase { 0xc4, 0x02, 0x1d, 0x92, 0x5c, 0x75, 0x00 }, { vgatherdps ymm11,DWORD [r13+ymm14*2+0x0],ymm12 } +testcase { 0xc4, 0x02, 0x1d, 0x93, 0x5c, 0x75, 0x00 }, { vgatherqps xmm11,DWORD [r13+ymm14*2+0x0],xmm12 } +testcase { 0xc4, 0xe2, 0x51, 0x92, 0x34, 0x25, 0x08, 0x00, 0x00, 0x00 }, { vgatherdps xmm6,DWORD [xmm4*1+0x8],xmm5 } +testcase { 0xc4, 0xe2, 0x51, 0x92, 0x34, 0x25, 0xf8, 0xff, 0xff, 0xff }, { vgatherdps xmm6,DWORD [xmm4*1-0x8],xmm5 } +testcase { 0xc4, 0xe2, 0x51, 0x92, 0x34, 0x25, 0x00, 0x00, 0x00, 0x00 }, { vgatherdps xmm6,DWORD [xmm4*1+0x0],xmm5 } +testcase { 0xc4, 0xe2, 0x51, 0x92, 0x34, 0x25, 0x98, 0x02, 0x00, 0x00 }, { vgatherdps xmm6,DWORD [xmm4*1+0x298],xmm5 } +testcase { 0xc4, 0xe2, 0x51, 0x92, 0x34, 0xe5, 0x08, 0x00, 0x00, 0x00 }, { vgatherdps xmm6,DWORD [xmm4*8+0x8],xmm5 } +testcase { 0xc4, 0xe2, 0x51, 0x92, 0x34, 0xe5, 0xf8, 0xff, 0xff, 0xff }, { vgatherdps xmm6,DWORD [xmm4*8-0x8],xmm5 } +testcase { 0xc4, 0xe2, 0x51, 0x92, 0x34, 0xe5, 0x00, 0x00, 0x00, 0x00 }, { vgatherdps xmm6,DWORD [xmm4*8+0x0],xmm5 } +testcase { 0xc4, 0xe2, 0x51, 0x92, 0x34, 0xe5, 0x98, 0x02, 0x00, 0x00 }, { vgatherdps xmm6,DWORD [xmm4*8+0x298],xmm5 } +testcase { 0xc4, 0xa2, 0x51, 0x92, 0x34, 0x35, 0x08, 0x00, 0x00, 0x00 }, { vgatherdps xmm6,DWORD [xmm14*1+0x8],xmm5 } +testcase { 0xc4, 0xa2, 0x51, 0x92, 0x34, 0x35, 0xf8, 0xff, 0xff, 0xff }, { vgatherdps xmm6,DWORD [xmm14*1-0x8],xmm5 } +testcase { 0xc4, 0xa2, 0x51, 0x92, 0x34, 0x35, 0x00, 0x00, 0x00, 0x00 }, { vgatherdps xmm6,DWORD [xmm14*1+0x0],xmm5 } +testcase { 0xc4, 0xa2, 0x51, 0x92, 0x34, 0x35, 0x98, 0x02, 0x00, 0x00 }, { vgatherdps xmm6,DWORD [xmm14*1+0x298],xmm5 } +testcase { 0xc4, 0xa2, 0x51, 0x92, 0x34, 0xf5, 0x08, 0x00, 0x00, 0x00 }, { vgatherdps xmm6,DWORD [xmm14*8+0x8],xmm5 } +testcase { 0xc4, 0xa2, 0x51, 0x92, 0x34, 0xf5, 0xf8, 0xff, 0xff, 0xff }, { vgatherdps xmm6,DWORD [xmm14*8-0x8],xmm5 } +testcase { 0xc4, 0xa2, 0x51, 0x92, 0x34, 0xf5, 0x00, 0x00, 0x00, 0x00 }, { vgatherdps xmm6,DWORD [xmm14*8+0x0],xmm5 } +testcase { 0xc4, 0xa2, 0x51, 0x92, 0x34, 0xf5, 0x98, 0x02, 0x00, 0x00 }, { vgatherdps xmm6,DWORD [xmm14*8+0x298],xmm5 } +testcase { 0xc4, 0xe2, 0x69, 0x90, 0x4c, 0x7d, 0x00 }, { vpgatherdd xmm1,DWORD [rbp+xmm7*2+0x0],xmm2 } +testcase { 0xc4, 0xe2, 0x69, 0x91, 0x4c, 0x7d, 0x00 }, { vpgatherqd xmm1,DWORD [rbp+xmm7*2+0x0],xmm2 } +testcase { 0xc4, 0xe2, 0x6d, 0x90, 0x4c, 0x7d, 0x00 }, { vpgatherdd ymm1,DWORD [rbp+ymm7*2+0x0],ymm2 } +testcase { 0xc4, 0xe2, 0x6d, 0x91, 0x4c, 0x7d, 0x00 }, { vpgatherqd xmm1,DWORD [rbp+ymm7*2+0x0],xmm2 } +testcase { 0xc4, 0x02, 0x19, 0x90, 0x5c, 0x75, 0x00 }, { vpgatherdd xmm11,DWORD [r13+xmm14*2+0x0],xmm12 } +testcase { 0xc4, 0x02, 0x19, 0x91, 0x5c, 0x75, 0x00 }, { vpgatherqd xmm11,DWORD [r13+xmm14*2+0x0],xmm12 } +testcase { 0xc4, 0x02, 0x1d, 0x90, 0x5c, 0x75, 0x00 }, { vpgatherdd ymm11,DWORD [r13+ymm14*2+0x0],ymm12 } +testcase { 0xc4, 0x02, 0x1d, 0x91, 0x5c, 0x75, 0x00 }, { vpgatherqd xmm11,DWORD [r13+ymm14*2+0x0],xmm12 } +testcase { 0xc4, 0xe2, 0x51, 0x90, 0x34, 0x25, 0x08, 0x00, 0x00, 0x00 }, { vpgatherdd xmm6,DWORD [xmm4*1+0x8],xmm5 } +testcase { 0xc4, 0xe2, 0x51, 0x90, 0x34, 0x25, 0xf8, 0xff, 0xff, 0xff }, { vpgatherdd xmm6,DWORD [xmm4*1-0x8],xmm5 } +testcase { 0xc4, 0xe2, 0x51, 0x90, 0x34, 0x25, 0x00, 0x00, 0x00, 0x00 }, { vpgatherdd xmm6,DWORD [xmm4*1+0x0],xmm5 } +testcase { 0xc4, 0xe2, 0x51, 0x90, 0x34, 0x25, 0x98, 0x02, 0x00, 0x00 }, { vpgatherdd xmm6,DWORD [xmm4*1+0x298],xmm5 } +testcase { 0xc4, 0xe2, 0x51, 0x90, 0x34, 0xe5, 0x08, 0x00, 0x00, 0x00 }, { vpgatherdd xmm6,DWORD [xmm4*8+0x8],xmm5 } +testcase { 0xc4, 0xe2, 0x51, 0x90, 0x34, 0xe5, 0xf8, 0xff, 0xff, 0xff }, { vpgatherdd xmm6,DWORD [xmm4*8-0x8],xmm5 } +testcase { 0xc4, 0xe2, 0x51, 0x90, 0x34, 0xe5, 0x00, 0x00, 0x00, 0x00 }, { vpgatherdd xmm6,DWORD [xmm4*8+0x0],xmm5 } +testcase { 0xc4, 0xe2, 0x51, 0x90, 0x34, 0xe5, 0x98, 0x02, 0x00, 0x00 }, { vpgatherdd xmm6,DWORD [xmm4*8+0x298],xmm5 } +testcase { 0xc4, 0xa2, 0x51, 0x90, 0x34, 0x35, 0x08, 0x00, 0x00, 0x00 }, { vpgatherdd xmm6,DWORD [xmm14*1+0x8],xmm5 } +testcase { 0xc4, 0xa2, 0x51, 0x90, 0x34, 0x35, 0xf8, 0xff, 0xff, 0xff }, { vpgatherdd xmm6,DWORD [xmm14*1-0x8],xmm5 } +testcase { 0xc4, 0xa2, 0x51, 0x90, 0x34, 0x35, 0x00, 0x00, 0x00, 0x00 }, { vpgatherdd xmm6,DWORD [xmm14*1+0x0],xmm5 } +testcase { 0xc4, 0xa2, 0x51, 0x90, 0x34, 0x35, 0x98, 0x02, 0x00, 0x00 }, { vpgatherdd xmm6,DWORD [xmm14*1+0x298],xmm5 } +testcase { 0xc4, 0xa2, 0x51, 0x90, 0x34, 0xf5, 0x08, 0x00, 0x00, 0x00 }, { vpgatherdd xmm6,DWORD [xmm14*8+0x8],xmm5 } +testcase { 0xc4, 0xa2, 0x51, 0x90, 0x34, 0xf5, 0xf8, 0xff, 0xff, 0xff }, { vpgatherdd xmm6,DWORD [xmm14*8-0x8],xmm5 } +testcase { 0xc4, 0xa2, 0x51, 0x90, 0x34, 0xf5, 0x00, 0x00, 0x00, 0x00 }, { vpgatherdd xmm6,DWORD [xmm14*8+0x0],xmm5 } +testcase { 0xc4, 0xa2, 0x51, 0x90, 0x34, 0xf5, 0x98, 0x02, 0x00, 0x00 }, { vpgatherdd xmm6,DWORD [xmm14*8+0x298],xmm5 } +testcase { 0xc4, 0xe2, 0xe9, 0x90, 0x4c, 0x7d, 0x00 }, { vpgatherdq xmm1,QWORD [rbp+xmm7*2+0x0],xmm2 } +testcase { 0xc4, 0xe2, 0xe9, 0x91, 0x4c, 0x7d, 0x00 }, { vpgatherqq xmm1,QWORD [rbp+xmm7*2+0x0],xmm2 } +testcase { 0xc4, 0xe2, 0xed, 0x90, 0x4c, 0x7d, 0x00 }, { vpgatherdq ymm1,QWORD [rbp+xmm7*2+0x0],ymm2 } +testcase { 0xc4, 0xe2, 0xed, 0x91, 0x4c, 0x7d, 0x00 }, { vpgatherqq ymm1,QWORD [rbp+ymm7*2+0x0],ymm2 } +testcase { 0xc4, 0x02, 0x99, 0x90, 0x5c, 0x75, 0x00 }, { vpgatherdq xmm11,QWORD [r13+xmm14*2+0x0],xmm12 } +testcase { 0xc4, 0x02, 0x99, 0x91, 0x5c, 0x75, 0x00 }, { vpgatherqq xmm11,QWORD [r13+xmm14*2+0x0],xmm12 } +testcase { 0xc4, 0x02, 0x9d, 0x90, 0x5c, 0x75, 0x00 }, { vpgatherdq ymm11,QWORD [r13+xmm14*2+0x0],ymm12 } +testcase { 0xc4, 0x02, 0x9d, 0x91, 0x5c, 0x75, 0x00 }, { vpgatherqq ymm11,QWORD [r13+ymm14*2+0x0],ymm12 } +testcase { 0xc4, 0xe2, 0xd5, 0x90, 0x34, 0x25, 0x08, 0x00, 0x00, 0x00 }, { vpgatherdq ymm6,QWORD [xmm4*1+0x8],ymm5 } +testcase { 0xc4, 0xe2, 0xd5, 0x90, 0x34, 0x25, 0xf8, 0xff, 0xff, 0xff }, { vpgatherdq ymm6,QWORD [xmm4*1-0x8],ymm5 } +testcase { 0xc4, 0xe2, 0xd5, 0x90, 0x34, 0x25, 0x00, 0x00, 0x00, 0x00 }, { vpgatherdq ymm6,QWORD [xmm4*1+0x0],ymm5 } +testcase { 0xc4, 0xe2, 0xd5, 0x90, 0x34, 0x25, 0x98, 0x02, 0x00, 0x00 }, { vpgatherdq ymm6,QWORD [xmm4*1+0x298],ymm5 } +testcase { 0xc4, 0xe2, 0xd5, 0x90, 0x34, 0xe5, 0x08, 0x00, 0x00, 0x00 }, { vpgatherdq ymm6,QWORD [xmm4*8+0x8],ymm5 } +testcase { 0xc4, 0xe2, 0xd5, 0x90, 0x34, 0xe5, 0xf8, 0xff, 0xff, 0xff }, { vpgatherdq ymm6,QWORD [xmm4*8-0x8],ymm5 } +testcase { 0xc4, 0xe2, 0xd5, 0x90, 0x34, 0xe5, 0x00, 0x00, 0x00, 0x00 }, { vpgatherdq ymm6,QWORD [xmm4*8+0x0],ymm5 } +testcase { 0xc4, 0xe2, 0xd5, 0x90, 0x34, 0xe5, 0x98, 0x02, 0x00, 0x00 }, { vpgatherdq ymm6,QWORD [xmm4*8+0x298],ymm5 } +testcase { 0xc4, 0xa2, 0xd5, 0x90, 0x34, 0x35, 0x08, 0x00, 0x00, 0x00 }, { vpgatherdq ymm6,QWORD [xmm14*1+0x8],ymm5 } +testcase { 0xc4, 0xa2, 0xd5, 0x90, 0x34, 0x35, 0xf8, 0xff, 0xff, 0xff }, { vpgatherdq ymm6,QWORD [xmm14*1-0x8],ymm5 } +testcase { 0xc4, 0xa2, 0xd5, 0x90, 0x34, 0x35, 0x00, 0x00, 0x00, 0x00 }, { vpgatherdq ymm6,QWORD [xmm14*1+0x0],ymm5 } +testcase { 0xc4, 0xa2, 0xd5, 0x90, 0x34, 0x35, 0x98, 0x02, 0x00, 0x00 }, { vpgatherdq ymm6,QWORD [xmm14*1+0x298],ymm5 } +testcase { 0xc4, 0xa2, 0xd5, 0x90, 0x34, 0xf5, 0x08, 0x00, 0x00, 0x00 }, { vpgatherdq ymm6,QWORD [xmm14*8+0x8],ymm5 } +testcase { 0xc4, 0xa2, 0xd5, 0x90, 0x34, 0xf5, 0xf8, 0xff, 0xff, 0xff }, { vpgatherdq ymm6,QWORD [xmm14*8-0x8],ymm5 } +testcase { 0xc4, 0xa2, 0xd5, 0x90, 0x34, 0xf5, 0x00, 0x00, 0x00, 0x00 }, { vpgatherdq ymm6,QWORD [xmm14*8+0x0],ymm5 } +testcase { 0xc4, 0xa2, 0xd5, 0x90, 0x34, 0xf5, 0x98, 0x02, 0x00, 0x00 }, { vpgatherdq ymm6,QWORD [xmm14*8+0x298],ymm5 } + +; b/gas/testsuite/gas/i386/x86-64-avx2-intel.d +testcase { 0xc4, 0xe2, 0x5d, 0x8c, 0x31 }, { vpmaskmovd ymm6,ymm4,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x8e, 0x21 }, { vpmaskmovd YWORD [rcx],ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0xdd, 0x8c, 0x31 }, { vpmaskmovq ymm6,ymm4,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0xcd, 0x8e, 0x21 }, { vpmaskmovq YWORD [rcx],ymm6,ymm4 } +testcase { 0xc4, 0xe3, 0xfd, 0x01, 0xd6, 0x07 }, { vpermpd ymm2,ymm6,0x7 } +testcase { 0xc4, 0xe3, 0xfd, 0x01, 0x31, 0x07 }, { vpermpd ymm6,YWORD [rcx],0x7 } +testcase { 0xc4, 0xe3, 0xfd, 0x00, 0xd6, 0x07 }, { vpermq ymm2,ymm6,0x7 } +testcase { 0xc4, 0xe3, 0xfd, 0x00, 0x31, 0x07 }, { vpermq ymm6,YWORD [rcx],0x7 } +testcase { 0xc4, 0xe2, 0x4d, 0x36, 0xd4 }, { vpermd ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x36, 0x11 }, { vpermd ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x16, 0xd4 }, { vpermps ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x16, 0x11 }, { vpermps ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x47, 0xd4 }, { vpsllvd ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x47, 0x11 }, { vpsllvd ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0xcd, 0x47, 0xd4 }, { vpsllvq ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0xcd, 0x47, 0x11 }, { vpsllvq ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x46, 0xd4 }, { vpsravd ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x46, 0x11 }, { vpsravd ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x45, 0xd4 }, { vpsrlvd ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x45, 0x11 }, { vpsrlvd ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0xcd, 0x45, 0xd4 }, { vpsrlvq ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0xcd, 0x45, 0x11 }, { vpsrlvq ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x2a, 0x21 }, { vmovntdqa ymm4,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x19, 0xf4 }, { vbroadcastsd ymm6,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x18, 0xf4 }, { vbroadcastss ymm6,xmm4 } +testcase { 0xc4, 0xe3, 0x4d, 0x02, 0xd4, 0x07 }, { vpblendd ymm2,ymm6,ymm4,0x7 } +testcase { 0xc4, 0xe3, 0x4d, 0x02, 0x11, 0x07 }, { vpblendd ymm2,ymm6,YWORD [rcx],0x7 } +testcase { 0xc4, 0xe3, 0x4d, 0x46, 0xd4, 0x07 }, { vperm2i128 ymm2,ymm6,ymm4,0x7 } +testcase { 0xc4, 0xe3, 0x4d, 0x46, 0x11, 0x07 }, { vperm2i128 ymm2,ymm6,YWORD [rcx],0x7 } +testcase { 0xc4, 0xe3, 0x5d, 0x38, 0xf4, 0x07 }, { vinserti128 ymm6,ymm4,xmm4,0x7 } +testcase { 0xc4, 0xe3, 0x5d, 0x38, 0x31, 0x07 }, { vinserti128 ymm6,ymm4,OWORD [rcx],0x7 } +testcase { 0xc4, 0xe2, 0x7d, 0x5a, 0x21 }, { vbroadcasti128 ymm4,OWORD [rcx] } +testcase { 0xc4, 0xe2, 0x49, 0x47, 0xd4 }, { vpsllvd xmm2,xmm6,xmm4 } +testcase { 0xc4, 0xe2, 0x49, 0x47, 0x39 }, { vpsllvd xmm7,xmm6,OWORD [rcx] } +testcase { 0xc4, 0xe2, 0xc9, 0x47, 0xd4 }, { vpsllvq xmm2,xmm6,xmm4 } +testcase { 0xc4, 0xe2, 0xc9, 0x47, 0x39 }, { vpsllvq xmm7,xmm6,OWORD [rcx] } +testcase { 0xc4, 0xe2, 0x49, 0x46, 0xd4 }, { vpsravd xmm2,xmm6,xmm4 } +testcase { 0xc4, 0xe2, 0x49, 0x46, 0x39 }, { vpsravd xmm7,xmm6,OWORD [rcx] } +testcase { 0xc4, 0xe2, 0x49, 0x45, 0xd4 }, { vpsrlvd xmm2,xmm6,xmm4 } +testcase { 0xc4, 0xe2, 0x49, 0x45, 0x39 }, { vpsrlvd xmm7,xmm6,OWORD [rcx] } +testcase { 0xc4, 0xe2, 0xc9, 0x45, 0xd4 }, { vpsrlvq xmm2,xmm6,xmm4 } +testcase { 0xc4, 0xe2, 0xc9, 0x45, 0x39 }, { vpsrlvq xmm7,xmm6,OWORD [rcx] } +testcase { 0xc4, 0xe2, 0x59, 0x8c, 0x31 }, { vpmaskmovd xmm6,xmm4,OWORD [rcx] } +testcase { 0xc4, 0xe2, 0xd9, 0x8c, 0x31 }, { vpmaskmovq xmm6,xmm4,OWORD [rcx] } +testcase { 0xc4, 0xe3, 0x7d, 0x39, 0xe6, 0x07 }, { vextracti128 xmm6,ymm4,0x7 } +testcase { 0xc4, 0xe3, 0x7d, 0x39, 0x21, 0x07 }, { vextracti128 OWORD [rcx],ymm4,0x7 } +testcase { 0xc4, 0xe2, 0x49, 0x8e, 0x21 }, { vpmaskmovd OWORD [rcx],xmm6,xmm4 } +testcase { 0xc4, 0xe2, 0xc9, 0x8e, 0x21 }, { vpmaskmovq OWORD [rcx],xmm6,xmm4 } +testcase { 0xc4, 0xe3, 0x49, 0x02, 0xd4, 0x07 }, { vpblendd xmm2,xmm6,xmm4,0x7 } +testcase { 0xc4, 0xe3, 0x49, 0x02, 0x11, 0x07 }, { vpblendd xmm2,xmm6,OWORD [rcx],0x7 } +testcase { 0xc4, 0xe2, 0x79, 0x59, 0xf4 }, { vpbroadcastq xmm6,xmm4 } +testcase { 0xc4, 0xe2, 0x79, 0x59, 0x21 }, { vpbroadcastq xmm4,QWORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x59, 0xf4 }, { vpbroadcastq ymm6,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x59, 0x21 }, { vpbroadcastq ymm4,QWORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x58, 0xe4 }, { vpbroadcastd ymm4,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x58, 0x21 }, { vpbroadcastd ymm4,DWORD [rcx] } +testcase { 0xc4, 0xe2, 0x79, 0x58, 0xf4 }, { vpbroadcastd xmm6,xmm4 } +testcase { 0xc4, 0xe2, 0x79, 0x58, 0x21 }, { vpbroadcastd xmm4,DWORD [rcx] } +testcase { 0xc4, 0xe2, 0x79, 0x79, 0xf4 }, { vpbroadcastw xmm6,xmm4 } +testcase { 0xc4, 0xe2, 0x79, 0x79, 0x21 }, { vpbroadcastw xmm4,WORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x79, 0xf4 }, { vpbroadcastw ymm6,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x79, 0x21 }, { vpbroadcastw ymm4,WORD [rcx] } +testcase { 0xc4, 0xe2, 0x79, 0x78, 0xf4 }, { vpbroadcastb xmm6,xmm4 } +testcase { 0xc4, 0xe2, 0x79, 0x78, 0x21 }, { vpbroadcastb xmm4,BYTE [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x78, 0xf4 }, { vpbroadcastb ymm6,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x78, 0x21 }, { vpbroadcastb ymm4,BYTE [rcx] } +testcase { 0xc4, 0xe2, 0x79, 0x18, 0xf4 }, { vbroadcastss xmm6,xmm4 } +testcase { 0xc4, 0xe2, 0x5d, 0x8c, 0x31 }, { vpmaskmovd ymm6,ymm4,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x8e, 0x21 }, { vpmaskmovd YWORD [rcx],ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x5d, 0x8c, 0x31 }, { vpmaskmovd ymm6,ymm4,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x8e, 0x21 }, { vpmaskmovd YWORD [rcx],ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0xdd, 0x8c, 0x31 }, { vpmaskmovq ymm6,ymm4,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0xcd, 0x8e, 0x21 }, { vpmaskmovq YWORD [rcx],ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0xdd, 0x8c, 0x31 }, { vpmaskmovq ymm6,ymm4,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0xcd, 0x8e, 0x21 }, { vpmaskmovq YWORD [rcx],ymm6,ymm4 } +testcase { 0xc4, 0xe3, 0xfd, 0x01, 0xd6, 0x07 }, { vpermpd ymm2,ymm6,0x7 } +testcase { 0xc4, 0xe3, 0xfd, 0x01, 0x31, 0x07 }, { vpermpd ymm6,YWORD [rcx],0x7 } +testcase { 0xc4, 0xe3, 0xfd, 0x01, 0x31, 0x07 }, { vpermpd ymm6,YWORD [rcx],0x7 } +testcase { 0xc4, 0xe3, 0xfd, 0x00, 0xd6, 0x07 }, { vpermq ymm2,ymm6,0x7 } +testcase { 0xc4, 0xe3, 0xfd, 0x00, 0x31, 0x07 }, { vpermq ymm6,YWORD [rcx],0x7 } +testcase { 0xc4, 0xe3, 0xfd, 0x00, 0x31, 0x07 }, { vpermq ymm6,YWORD [rcx],0x7 } +testcase { 0xc4, 0xe2, 0x4d, 0x36, 0xd4 }, { vpermd ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x36, 0x11 }, { vpermd ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x36, 0x11 }, { vpermd ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x16, 0xd4 }, { vpermps ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x16, 0x11 }, { vpermps ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x16, 0x11 }, { vpermps ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x47, 0xd4 }, { vpsllvd ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x47, 0x11 }, { vpsllvd ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x47, 0x11 }, { vpsllvd ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0xcd, 0x47, 0xd4 }, { vpsllvq ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0xcd, 0x47, 0x11 }, { vpsllvq ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0xcd, 0x47, 0x11 }, { vpsllvq ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x46, 0xd4 }, { vpsravd ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x46, 0x11 }, { vpsravd ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x46, 0x11 }, { vpsravd ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x45, 0xd4 }, { vpsrlvd ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x45, 0x11 }, { vpsrlvd ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x45, 0x11 }, { vpsrlvd ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0xcd, 0x45, 0xd4 }, { vpsrlvq ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0xcd, 0x45, 0x11 }, { vpsrlvq ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0xcd, 0x45, 0x11 }, { vpsrlvq ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x2a, 0x21 }, { vmovntdqa ymm4,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x2a, 0x21 }, { vmovntdqa ymm4,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x19, 0xf4 }, { vbroadcastsd ymm6,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x18, 0xf4 }, { vbroadcastss ymm6,xmm4 } +testcase { 0xc4, 0xe3, 0x4d, 0x02, 0xd4, 0x07 }, { vpblendd ymm2,ymm6,ymm4,0x7 } +testcase { 0xc4, 0xe3, 0x4d, 0x02, 0x11, 0x07 }, { vpblendd ymm2,ymm6,YWORD [rcx],0x7 } +testcase { 0xc4, 0xe3, 0x4d, 0x02, 0x11, 0x07 }, { vpblendd ymm2,ymm6,YWORD [rcx],0x7 } +testcase { 0xc4, 0xe3, 0x4d, 0x46, 0xd4, 0x07 }, { vperm2i128 ymm2,ymm6,ymm4,0x7 } +testcase { 0xc4, 0xe3, 0x4d, 0x46, 0x11, 0x07 }, { vperm2i128 ymm2,ymm6,YWORD [rcx],0x7 } +testcase { 0xc4, 0xe3, 0x4d, 0x46, 0x11, 0x07 }, { vperm2i128 ymm2,ymm6,YWORD [rcx],0x7 } +testcase { 0xc4, 0xe3, 0x5d, 0x38, 0xf4, 0x07 }, { vinserti128 ymm6,ymm4,xmm4,0x7 } +testcase { 0xc4, 0xe3, 0x5d, 0x38, 0x31, 0x07 }, { vinserti128 ymm6,ymm4,OWORD [rcx],0x7 } +testcase { 0xc4, 0xe3, 0x5d, 0x38, 0x31, 0x07 }, { vinserti128 ymm6,ymm4,OWORD [rcx],0x7 } +testcase { 0xc4, 0xe2, 0x7d, 0x5a, 0x21 }, { vbroadcasti128 ymm4,OWORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x5a, 0x21 }, { vbroadcasti128 ymm4,OWORD [rcx] } +testcase { 0xc4, 0xe2, 0x49, 0x47, 0xd4 }, { vpsllvd xmm2,xmm6,xmm4 } +testcase { 0xc4, 0xe2, 0x49, 0x47, 0x39 }, { vpsllvd xmm7,xmm6,OWORD [rcx] } +testcase { 0xc4, 0xe2, 0x49, 0x47, 0x39 }, { vpsllvd xmm7,xmm6,OWORD [rcx] } +testcase { 0xc4, 0xe2, 0xc9, 0x47, 0xd4 }, { vpsllvq xmm2,xmm6,xmm4 } +testcase { 0xc4, 0xe2, 0xc9, 0x47, 0x39 }, { vpsllvq xmm7,xmm6,OWORD [rcx] } +testcase { 0xc4, 0xe2, 0xc9, 0x47, 0x39 }, { vpsllvq xmm7,xmm6,OWORD [rcx] } +testcase { 0xc4, 0xe2, 0x49, 0x46, 0xd4 }, { vpsravd xmm2,xmm6,xmm4 } +testcase { 0xc4, 0xe2, 0x49, 0x46, 0x39 }, { vpsravd xmm7,xmm6,OWORD [rcx] } +testcase { 0xc4, 0xe2, 0x49, 0x46, 0x39 }, { vpsravd xmm7,xmm6,OWORD [rcx] } +testcase { 0xc4, 0xe2, 0x49, 0x45, 0xd4 }, { vpsrlvd xmm2,xmm6,xmm4 } +testcase { 0xc4, 0xe2, 0x49, 0x45, 0x39 }, { vpsrlvd xmm7,xmm6,OWORD [rcx] } +testcase { 0xc4, 0xe2, 0x49, 0x45, 0x39 }, { vpsrlvd xmm7,xmm6,OWORD [rcx] } +testcase { 0xc4, 0xe2, 0xc9, 0x45, 0xd4 }, { vpsrlvq xmm2,xmm6,xmm4 } +testcase { 0xc4, 0xe2, 0xc9, 0x45, 0x39 }, { vpsrlvq xmm7,xmm6,OWORD [rcx] } +testcase { 0xc4, 0xe2, 0xc9, 0x45, 0x39 }, { vpsrlvq xmm7,xmm6,OWORD [rcx] } +testcase { 0xc4, 0xe2, 0x59, 0x8c, 0x31 }, { vpmaskmovd xmm6,xmm4,OWORD [rcx] } +testcase { 0xc4, 0xe2, 0x59, 0x8c, 0x31 }, { vpmaskmovd xmm6,xmm4,OWORD [rcx] } +testcase { 0xc4, 0xe2, 0xd9, 0x8c, 0x31 }, { vpmaskmovq xmm6,xmm4,OWORD [rcx] } +testcase { 0xc4, 0xe2, 0xd9, 0x8c, 0x31 }, { vpmaskmovq xmm6,xmm4,OWORD [rcx] } +testcase { 0xc4, 0xe3, 0x7d, 0x39, 0xe6, 0x07 }, { vextracti128 xmm6,ymm4,0x7 } +testcase { 0xc4, 0xe3, 0x7d, 0x39, 0x21, 0x07 }, { vextracti128 OWORD [rcx],ymm4,0x7 } +testcase { 0xc4, 0xe3, 0x7d, 0x39, 0x21, 0x07 }, { vextracti128 OWORD [rcx],ymm4,0x7 } +testcase { 0xc4, 0xe2, 0x49, 0x8e, 0x21 }, { vpmaskmovd OWORD [rcx],xmm6,xmm4 } +testcase { 0xc4, 0xe2, 0x49, 0x8e, 0x21 }, { vpmaskmovd OWORD [rcx],xmm6,xmm4 } +testcase { 0xc4, 0xe2, 0xc9, 0x8e, 0x21 }, { vpmaskmovq OWORD [rcx],xmm6,xmm4 } +testcase { 0xc4, 0xe2, 0xc9, 0x8e, 0x21 }, { vpmaskmovq OWORD [rcx],xmm6,xmm4 } +testcase { 0xc4, 0xe3, 0x49, 0x02, 0xd4, 0x07 }, { vpblendd xmm2,xmm6,xmm4,0x7 } +testcase { 0xc4, 0xe3, 0x49, 0x02, 0x11, 0x07 }, { vpblendd xmm2,xmm6,OWORD [rcx],0x7 } +testcase { 0xc4, 0xe3, 0x49, 0x02, 0x11, 0x07 }, { vpblendd xmm2,xmm6,OWORD [rcx],0x7 } +testcase { 0xc4, 0xe2, 0x79, 0x59, 0xf4 }, { vpbroadcastq xmm6,xmm4 } +testcase { 0xc4, 0xe2, 0x79, 0x59, 0x21 }, { vpbroadcastq xmm4,QWORD [rcx] } +testcase { 0xc4, 0xe2, 0x79, 0x59, 0x21 }, { vpbroadcastq xmm4,QWORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x59, 0xf4 }, { vpbroadcastq ymm6,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x59, 0x21 }, { vpbroadcastq ymm4,QWORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x59, 0x21 }, { vpbroadcastq ymm4,QWORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x58, 0xe4 }, { vpbroadcastd ymm4,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x58, 0x21 }, { vpbroadcastd ymm4,DWORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x58, 0x21 }, { vpbroadcastd ymm4,DWORD [rcx] } +testcase { 0xc4, 0xe2, 0x79, 0x58, 0xf4 }, { vpbroadcastd xmm6,xmm4 } +testcase { 0xc4, 0xe2, 0x79, 0x58, 0x21 }, { vpbroadcastd xmm4,DWORD [rcx] } +testcase { 0xc4, 0xe2, 0x79, 0x58, 0x21 }, { vpbroadcastd xmm4,DWORD [rcx] } +testcase { 0xc4, 0xe2, 0x79, 0x79, 0xf4 }, { vpbroadcastw xmm6,xmm4 } +testcase { 0xc4, 0xe2, 0x79, 0x79, 0x21 }, { vpbroadcastw xmm4,WORD [rcx] } +testcase { 0xc4, 0xe2, 0x79, 0x79, 0x21 }, { vpbroadcastw xmm4,WORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x79, 0xf4 }, { vpbroadcastw ymm6,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x79, 0x21 }, { vpbroadcastw ymm4,WORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x79, 0x21 }, { vpbroadcastw ymm4,WORD [rcx] } +testcase { 0xc4, 0xe2, 0x79, 0x78, 0xf4 }, { vpbroadcastb xmm6,xmm4 } +testcase { 0xc4, 0xe2, 0x79, 0x78, 0x21 }, { vpbroadcastb xmm4,BYTE [rcx] } +testcase { 0xc4, 0xe2, 0x79, 0x78, 0x21 }, { vpbroadcastb xmm4,BYTE [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x78, 0xf4 }, { vpbroadcastb ymm6,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x78, 0x21 }, { vpbroadcastb ymm4,BYTE [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x78, 0x21 }, { vpbroadcastb ymm4,BYTE [rcx] } +testcase { 0xc4, 0xe2, 0x79, 0x18, 0xf4 }, { vbroadcastss xmm6,xmm4 } + +; b/gas/testsuite/gas/i386/x86-64-avx256int-intel.d +testcase { 0xc5, 0xfd, 0xd7, 0xcc }, { vpmovmskb ecx,ymm4 } +testcase { 0xc5, 0xfd, 0xd7, 0xcc }, { vpmovmskb ecx,ymm4 } +testcase { 0xc5, 0xed, 0x72, 0xf6, 0x07 }, { vpslld ymm2,ymm6,0x7 } +testcase { 0xc5, 0xed, 0x73, 0xfe, 0x07 }, { vpslldq ymm2,ymm6,0x7 } +testcase { 0xc5, 0xed, 0x73, 0xf6, 0x07 }, { vpsllq ymm2,ymm6,0x7 } +testcase { 0xc5, 0xed, 0x71, 0xf6, 0x07 }, { vpsllw ymm2,ymm6,0x7 } +testcase { 0xc5, 0xed, 0x72, 0xe6, 0x07 }, { vpsrad ymm2,ymm6,0x7 } +testcase { 0xc5, 0xed, 0x71, 0xe6, 0x07 }, { vpsraw ymm2,ymm6,0x7 } +testcase { 0xc5, 0xed, 0x72, 0xd6, 0x07 }, { vpsrld ymm2,ymm6,0x7 } +testcase { 0xc5, 0xed, 0x73, 0xde, 0x07 }, { vpsrldq ymm2,ymm6,0x7 } +testcase { 0xc5, 0xed, 0x73, 0xd6, 0x07 }, { vpsrlq ymm2,ymm6,0x7 } +testcase { 0xc5, 0xed, 0x71, 0xd6, 0x07 }, { vpsrlw ymm2,ymm6,0x7 } +testcase { 0xc5, 0xfd, 0x70, 0xd6, 0x07 }, { vpshufd ymm2,ymm6,0x7 } +testcase { 0xc5, 0xfd, 0x70, 0x31, 0x07 }, { vpshufd ymm6,YWORD [rcx],0x7 } +testcase { 0xc5, 0xfe, 0x70, 0xd6, 0x07 }, { vpshufhw ymm2,ymm6,0x7 } +testcase { 0xc5, 0xfe, 0x70, 0x31, 0x07 }, { vpshufhw ymm6,YWORD [rcx],0x7 } +testcase { 0xc5, 0xff, 0x70, 0xd6, 0x07 }, { vpshuflw ymm2,ymm6,0x7 } +testcase { 0xc5, 0xff, 0x70, 0x31, 0x07 }, { vpshuflw ymm6,YWORD [rcx],0x7 } +testcase { 0xc5, 0xcd, 0x6b, 0xd4 }, { vpackssdw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x6b, 0x11 }, { vpackssdw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0x63, 0xd4 }, { vpacksswb ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x63, 0x11 }, { vpacksswb ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x2b, 0xd4 }, { vpackusdw ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x2b, 0x11 }, { vpackusdw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0x67, 0xd4 }, { vpackuswb ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x67, 0x11 }, { vpackuswb ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xfc, 0xd4 }, { vpaddb ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xfc, 0x11 }, { vpaddb ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xfd, 0xd4 }, { vpaddw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xfd, 0x11 }, { vpaddw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xfe, 0xd4 }, { vpaddd ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xfe, 0x11 }, { vpaddd ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xd4, 0xd4 }, { vpaddq ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xd4, 0x11 }, { vpaddq ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xec, 0xd4 }, { vpaddsb ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xec, 0x11 }, { vpaddsb ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xed, 0xd4 }, { vpaddsw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xed, 0x11 }, { vpaddsw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xdc, 0xd4 }, { vpaddusb ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xdc, 0x11 }, { vpaddusb ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xdd, 0xd4 }, { vpaddusw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xdd, 0x11 }, { vpaddusw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xdb, 0xd4 }, { vpand ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xdb, 0x11 }, { vpand ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xdf, 0xd4 }, { vpandn ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xdf, 0x11 }, { vpandn ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xe0, 0xd4 }, { vpavgb ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xe0, 0x11 }, { vpavgb ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xe3, 0xd4 }, { vpavgw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xe3, 0x11 }, { vpavgw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0x74, 0xd4 }, { vpcmpeqb ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x74, 0x11 }, { vpcmpeqb ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0x75, 0xd4 }, { vpcmpeqw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x75, 0x11 }, { vpcmpeqw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0x76, 0xd4 }, { vpcmpeqd ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x76, 0x11 }, { vpcmpeqd ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x29, 0xd4 }, { vpcmpeqq ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x29, 0x11 }, { vpcmpeqq ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0x64, 0xd4 }, { vpcmpgtb ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x64, 0x11 }, { vpcmpgtb ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0x65, 0xd4 }, { vpcmpgtw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x65, 0x11 }, { vpcmpgtw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0x66, 0xd4 }, { vpcmpgtd ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x66, 0x11 }, { vpcmpgtd ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x37, 0xd4 }, { vpcmpgtq ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x37, 0x11 }, { vpcmpgtq ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x01, 0xd4 }, { vphaddw ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x01, 0x11 }, { vphaddw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x02, 0xd4 }, { vphaddd ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x02, 0x11 }, { vphaddd ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x03, 0xd4 }, { vphaddsw ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x03, 0x11 }, { vphaddsw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x05, 0xd4 }, { vphsubw ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x05, 0x11 }, { vphsubw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x06, 0xd4 }, { vphsubd ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x06, 0x11 }, { vphsubd ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x07, 0xd4 }, { vphsubsw ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x07, 0x11 }, { vphsubsw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xf5, 0xd4 }, { vpmaddwd ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xf5, 0x11 }, { vpmaddwd ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x04, 0xd4 }, { vpmaddubsw ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x04, 0x11 }, { vpmaddubsw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x3c, 0xd4 }, { vpmaxsb ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x3c, 0x11 }, { vpmaxsb ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xee, 0xd4 }, { vpmaxsw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xee, 0x11 }, { vpmaxsw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x3d, 0xd4 }, { vpmaxsd ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x3d, 0x11 }, { vpmaxsd ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xde, 0xd4 }, { vpmaxub ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xde, 0x11 }, { vpmaxub ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x3e, 0xd4 }, { vpmaxuw ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x3e, 0x11 }, { vpmaxuw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x3f, 0xd4 }, { vpmaxud ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x3f, 0x11 }, { vpmaxud ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x38, 0xd4 }, { vpminsb ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x38, 0x11 }, { vpminsb ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xea, 0xd4 }, { vpminsw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xea, 0x11 }, { vpminsw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x39, 0xd4 }, { vpminsd ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x39, 0x11 }, { vpminsd ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xda, 0xd4 }, { vpminub ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xda, 0x11 }, { vpminub ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x3a, 0xd4 }, { vpminuw ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x3a, 0x11 }, { vpminuw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x3b, 0xd4 }, { vpminud ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x3b, 0x11 }, { vpminud ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xe4, 0xd4 }, { vpmulhuw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xe4, 0x11 }, { vpmulhuw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x0b, 0xd4 }, { vpmulhrsw ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x0b, 0x11 }, { vpmulhrsw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xe5, 0xd4 }, { vpmulhw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xe5, 0x11 }, { vpmulhw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xd5, 0xd4 }, { vpmullw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xd5, 0x11 }, { vpmullw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x40, 0xd4 }, { vpmulld ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x40, 0x11 }, { vpmulld ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xf4, 0xd4 }, { vpmuludq ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xf4, 0x11 }, { vpmuludq ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x28, 0xd4 }, { vpmuldq ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x28, 0x11 }, { vpmuldq ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xeb, 0xd4 }, { vpor ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xeb, 0x11 }, { vpor ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xf6, 0xd4 }, { vpsadbw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xf6, 0x11 }, { vpsadbw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x00, 0xd4 }, { vpshufb ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x00, 0x11 }, { vpshufb ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x08, 0xd4 }, { vpsignb ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x08, 0x11 }, { vpsignb ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x09, 0xd4 }, { vpsignw ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x09, 0x11 }, { vpsignw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x0a, 0xd4 }, { vpsignd ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x0a, 0x11 }, { vpsignd ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xf8, 0xd4 }, { vpsubb ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xf8, 0x11 }, { vpsubb ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xf9, 0xd4 }, { vpsubw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xf9, 0x11 }, { vpsubw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xfa, 0xd4 }, { vpsubd ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xfa, 0x11 }, { vpsubd ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xfb, 0xd4 }, { vpsubq ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xfb, 0x11 }, { vpsubq ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xe8, 0xd4 }, { vpsubsb ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xe8, 0x11 }, { vpsubsb ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xe9, 0xd4 }, { vpsubsw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xe9, 0x11 }, { vpsubsw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xd8, 0xd4 }, { vpsubusb ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xd8, 0x11 }, { vpsubusb ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xd9, 0xd4 }, { vpsubusw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xd9, 0x11 }, { vpsubusw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0x68, 0xd4 }, { vpunpckhbw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x68, 0x11 }, { vpunpckhbw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0x69, 0xd4 }, { vpunpckhwd ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x69, 0x11 }, { vpunpckhwd ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0x6a, 0xd4 }, { vpunpckhdq ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x6a, 0x11 }, { vpunpckhdq ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0x6d, 0xd4 }, { vpunpckhqdq ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x6d, 0x11 }, { vpunpckhqdq ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0x60, 0xd4 }, { vpunpcklbw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x60, 0x11 }, { vpunpcklbw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0x61, 0xd4 }, { vpunpcklwd ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x61, 0x11 }, { vpunpcklwd ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0x62, 0xd4 }, { vpunpckldq ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x62, 0x11 }, { vpunpckldq ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0x6c, 0xd4 }, { vpunpcklqdq ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x6c, 0x11 }, { vpunpcklqdq ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xef, 0xd4 }, { vpxor ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xef, 0x11 }, { vpxor ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x1c, 0xf4 }, { vpabsb ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x1c, 0x21 }, { vpabsb ymm4,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x1d, 0xf4 }, { vpabsw ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x1d, 0x21 }, { vpabsw ymm4,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x1e, 0xf4 }, { vpabsd ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x1e, 0x21 }, { vpabsd ymm4,YWORD [rcx] } +testcase { 0xc4, 0xe3, 0x4d, 0x42, 0xd4, 0x07 }, { vmpsadbw ymm2,ymm6,ymm4,0x7 } +testcase { 0xc4, 0xe3, 0x4d, 0x42, 0x11, 0x07 }, { vmpsadbw ymm2,ymm6,YWORD [rcx],0x7 } +testcase { 0xc4, 0xe3, 0x4d, 0x0f, 0xd4, 0x07 }, { vpalignr ymm2,ymm6,ymm4,0x7 } +testcase { 0xc4, 0xe3, 0x4d, 0x0f, 0x11, 0x07 }, { vpalignr ymm2,ymm6,YWORD [rcx],0x7 } +testcase { 0xc4, 0xe3, 0x4d, 0x0e, 0xd4, 0x07 }, { vpblendw ymm2,ymm6,ymm4,0x7 } +testcase { 0xc4, 0xe3, 0x4d, 0x0e, 0x11, 0x07 }, { vpblendw ymm2,ymm6,YWORD [rcx],0x7 } +testcase { 0xc4, 0xe3, 0x6d, 0x4c, 0xfe, 0x40 }, { vpblendvb ymm7,ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe3, 0x6d, 0x4c, 0x39, 0x40 }, { vpblendvb ymm7,ymm2,YWORD [rcx],ymm4 } +testcase { 0xc5, 0xcd, 0xf1, 0xd4 }, { vpsllw ymm2,ymm6,xmm4 } +testcase { 0xc5, 0xcd, 0xf1, 0x11 }, { vpsllw ymm2,ymm6,OWORD [rcx] } +testcase { 0xc5, 0xcd, 0xf2, 0xd4 }, { vpslld ymm2,ymm6,xmm4 } +testcase { 0xc5, 0xcd, 0xf2, 0x11 }, { vpslld ymm2,ymm6,OWORD [rcx] } +testcase { 0xc5, 0xcd, 0xf3, 0xd4 }, { vpsllq ymm2,ymm6,xmm4 } +testcase { 0xc5, 0xcd, 0xf3, 0x11 }, { vpsllq ymm2,ymm6,OWORD [rcx] } +testcase { 0xc5, 0xcd, 0xe1, 0xd4 }, { vpsraw ymm2,ymm6,xmm4 } +testcase { 0xc5, 0xcd, 0xe1, 0x11 }, { vpsraw ymm2,ymm6,OWORD [rcx] } +testcase { 0xc5, 0xcd, 0xe2, 0xd4 }, { vpsrad ymm2,ymm6,xmm4 } +testcase { 0xc5, 0xcd, 0xe2, 0x11 }, { vpsrad ymm2,ymm6,OWORD [rcx] } +testcase { 0xc5, 0xcd, 0xd1, 0xd4 }, { vpsrlw ymm2,ymm6,xmm4 } +testcase { 0xc5, 0xcd, 0xd1, 0x11 }, { vpsrlw ymm2,ymm6,OWORD [rcx] } +testcase { 0xc5, 0xcd, 0xd2, 0xd4 }, { vpsrld ymm2,ymm6,xmm4 } +testcase { 0xc5, 0xcd, 0xd2, 0x11 }, { vpsrld ymm2,ymm6,OWORD [rcx] } +testcase { 0xc5, 0xcd, 0xd3, 0xd4 }, { vpsrlq ymm2,ymm6,xmm4 } +testcase { 0xc5, 0xcd, 0xd3, 0x11 }, { vpsrlq ymm2,ymm6,OWORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x20, 0xe4 }, { vpmovsxbw ymm4,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x20, 0x21 }, { vpmovsxbw ymm4,OWORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x23, 0xe4 }, { vpmovsxwd ymm4,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x23, 0x21 }, { vpmovsxwd ymm4,OWORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x25, 0xe4 }, { vpmovsxdq ymm4,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x25, 0x21 }, { vpmovsxdq ymm4,OWORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x30, 0xe4 }, { vpmovzxbw ymm4,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x30, 0x21 }, { vpmovzxbw ymm4,OWORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x33, 0xe4 }, { vpmovzxwd ymm4,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x33, 0x21 }, { vpmovzxwd ymm4,OWORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x35, 0xe4 }, { vpmovzxdq ymm4,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x35, 0x21 }, { vpmovzxdq ymm4,OWORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x21, 0xf4 }, { vpmovsxbd ymm6,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x21, 0x21 }, { vpmovsxbd ymm4,QWORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x24, 0xf4 }, { vpmovsxwq ymm6,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x24, 0x21 }, { vpmovsxwq ymm4,QWORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x31, 0xf4 }, { vpmovzxbd ymm6,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x31, 0x21 }, { vpmovzxbd ymm4,QWORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x34, 0xf4 }, { vpmovzxwq ymm6,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x34, 0x21 }, { vpmovzxwq ymm4,QWORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x22, 0xe4 }, { vpmovsxbq ymm4,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x22, 0x21 }, { vpmovsxbq ymm4,DWORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x32, 0xe4 }, { vpmovzxbq ymm4,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x32, 0x21 }, { vpmovzxbq ymm4,DWORD [rcx] } +testcase { 0xc5, 0xfd, 0xd7, 0xcc }, { vpmovmskb ecx,ymm4 } +testcase { 0xc5, 0xfd, 0xd7, 0xcc }, { vpmovmskb ecx,ymm4 } +testcase { 0xc5, 0xed, 0x72, 0xf6, 0x07 }, { vpslld ymm2,ymm6,0x7 } +testcase { 0xc5, 0xed, 0x73, 0xfe, 0x07 }, { vpslldq ymm2,ymm6,0x7 } +testcase { 0xc5, 0xed, 0x73, 0xf6, 0x07 }, { vpsllq ymm2,ymm6,0x7 } +testcase { 0xc5, 0xed, 0x71, 0xf6, 0x07 }, { vpsllw ymm2,ymm6,0x7 } +testcase { 0xc5, 0xed, 0x72, 0xe6, 0x07 }, { vpsrad ymm2,ymm6,0x7 } +testcase { 0xc5, 0xed, 0x71, 0xe6, 0x07 }, { vpsraw ymm2,ymm6,0x7 } +testcase { 0xc5, 0xed, 0x72, 0xd6, 0x07 }, { vpsrld ymm2,ymm6,0x7 } +testcase { 0xc5, 0xed, 0x73, 0xde, 0x07 }, { vpsrldq ymm2,ymm6,0x7 } +testcase { 0xc5, 0xed, 0x73, 0xd6, 0x07 }, { vpsrlq ymm2,ymm6,0x7 } +testcase { 0xc5, 0xed, 0x71, 0xd6, 0x07 }, { vpsrlw ymm2,ymm6,0x7 } +testcase { 0xc5, 0xfd, 0x70, 0xd6, 0x07 }, { vpshufd ymm2,ymm6,0x7 } +testcase { 0xc5, 0xfd, 0x70, 0x31, 0x07 }, { vpshufd ymm6,YWORD [rcx],0x7 } +testcase { 0xc5, 0xfd, 0x70, 0x31, 0x07 }, { vpshufd ymm6,YWORD [rcx],0x7 } +testcase { 0xc5, 0xfe, 0x70, 0xd6, 0x07 }, { vpshufhw ymm2,ymm6,0x7 } +testcase { 0xc5, 0xfe, 0x70, 0x31, 0x07 }, { vpshufhw ymm6,YWORD [rcx],0x7 } +testcase { 0xc5, 0xfe, 0x70, 0x31, 0x07 }, { vpshufhw ymm6,YWORD [rcx],0x7 } +testcase { 0xc5, 0xff, 0x70, 0xd6, 0x07 }, { vpshuflw ymm2,ymm6,0x7 } +testcase { 0xc5, 0xff, 0x70, 0x31, 0x07 }, { vpshuflw ymm6,YWORD [rcx],0x7 } +testcase { 0xc5, 0xff, 0x70, 0x31, 0x07 }, { vpshuflw ymm6,YWORD [rcx],0x7 } +testcase { 0xc5, 0xcd, 0x6b, 0xd4 }, { vpackssdw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x6b, 0x11 }, { vpackssdw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0x6b, 0x11 }, { vpackssdw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0x63, 0xd4 }, { vpacksswb ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x63, 0x11 }, { vpacksswb ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0x63, 0x11 }, { vpacksswb ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x2b, 0xd4 }, { vpackusdw ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x2b, 0x11 }, { vpackusdw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x2b, 0x11 }, { vpackusdw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0x67, 0xd4 }, { vpackuswb ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x67, 0x11 }, { vpackuswb ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0x67, 0x11 }, { vpackuswb ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xfc, 0xd4 }, { vpaddb ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xfc, 0x11 }, { vpaddb ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xfc, 0x11 }, { vpaddb ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xfd, 0xd4 }, { vpaddw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xfd, 0x11 }, { vpaddw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xfd, 0x11 }, { vpaddw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xfe, 0xd4 }, { vpaddd ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xfe, 0x11 }, { vpaddd ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xfe, 0x11 }, { vpaddd ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xd4, 0xd4 }, { vpaddq ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xd4, 0x11 }, { vpaddq ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xd4, 0x11 }, { vpaddq ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xec, 0xd4 }, { vpaddsb ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xec, 0x11 }, { vpaddsb ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xec, 0x11 }, { vpaddsb ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xed, 0xd4 }, { vpaddsw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xed, 0x11 }, { vpaddsw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xed, 0x11 }, { vpaddsw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xdc, 0xd4 }, { vpaddusb ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xdc, 0x11 }, { vpaddusb ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xdc, 0x11 }, { vpaddusb ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xdd, 0xd4 }, { vpaddusw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xdd, 0x11 }, { vpaddusw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xdd, 0x11 }, { vpaddusw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xdb, 0xd4 }, { vpand ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xdb, 0x11 }, { vpand ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xdb, 0x11 }, { vpand ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xdf, 0xd4 }, { vpandn ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xdf, 0x11 }, { vpandn ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xdf, 0x11 }, { vpandn ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xe0, 0xd4 }, { vpavgb ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xe0, 0x11 }, { vpavgb ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xe0, 0x11 }, { vpavgb ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xe3, 0xd4 }, { vpavgw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xe3, 0x11 }, { vpavgw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xe3, 0x11 }, { vpavgw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0x74, 0xd4 }, { vpcmpeqb ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x74, 0x11 }, { vpcmpeqb ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0x74, 0x11 }, { vpcmpeqb ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0x75, 0xd4 }, { vpcmpeqw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x75, 0x11 }, { vpcmpeqw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0x75, 0x11 }, { vpcmpeqw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0x76, 0xd4 }, { vpcmpeqd ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x76, 0x11 }, { vpcmpeqd ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0x76, 0x11 }, { vpcmpeqd ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x29, 0xd4 }, { vpcmpeqq ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x29, 0x11 }, { vpcmpeqq ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x29, 0x11 }, { vpcmpeqq ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0x64, 0xd4 }, { vpcmpgtb ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x64, 0x11 }, { vpcmpgtb ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0x64, 0x11 }, { vpcmpgtb ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0x65, 0xd4 }, { vpcmpgtw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x65, 0x11 }, { vpcmpgtw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0x65, 0x11 }, { vpcmpgtw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0x66, 0xd4 }, { vpcmpgtd ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x66, 0x11 }, { vpcmpgtd ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0x66, 0x11 }, { vpcmpgtd ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x37, 0xd4 }, { vpcmpgtq ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x37, 0x11 }, { vpcmpgtq ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x37, 0x11 }, { vpcmpgtq ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x01, 0xd4 }, { vphaddw ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x01, 0x11 }, { vphaddw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x01, 0x11 }, { vphaddw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x02, 0xd4 }, { vphaddd ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x02, 0x11 }, { vphaddd ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x02, 0x11 }, { vphaddd ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x03, 0xd4 }, { vphaddsw ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x03, 0x11 }, { vphaddsw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x03, 0x11 }, { vphaddsw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x05, 0xd4 }, { vphsubw ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x05, 0x11 }, { vphsubw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x05, 0x11 }, { vphsubw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x06, 0xd4 }, { vphsubd ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x06, 0x11 }, { vphsubd ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x06, 0x11 }, { vphsubd ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x07, 0xd4 }, { vphsubsw ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x07, 0x11 }, { vphsubsw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x07, 0x11 }, { vphsubsw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xf5, 0xd4 }, { vpmaddwd ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xf5, 0x11 }, { vpmaddwd ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xf5, 0x11 }, { vpmaddwd ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x04, 0xd4 }, { vpmaddubsw ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x04, 0x11 }, { vpmaddubsw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x04, 0x11 }, { vpmaddubsw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x3c, 0xd4 }, { vpmaxsb ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x3c, 0x11 }, { vpmaxsb ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x3c, 0x11 }, { vpmaxsb ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xee, 0xd4 }, { vpmaxsw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xee, 0x11 }, { vpmaxsw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xee, 0x11 }, { vpmaxsw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x3d, 0xd4 }, { vpmaxsd ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x3d, 0x11 }, { vpmaxsd ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x3d, 0x11 }, { vpmaxsd ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xde, 0xd4 }, { vpmaxub ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xde, 0x11 }, { vpmaxub ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xde, 0x11 }, { vpmaxub ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x3e, 0xd4 }, { vpmaxuw ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x3e, 0x11 }, { vpmaxuw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x3e, 0x11 }, { vpmaxuw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x3f, 0xd4 }, { vpmaxud ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x3f, 0x11 }, { vpmaxud ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x3f, 0x11 }, { vpmaxud ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x38, 0xd4 }, { vpminsb ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x38, 0x11 }, { vpminsb ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x38, 0x11 }, { vpminsb ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xea, 0xd4 }, { vpminsw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xea, 0x11 }, { vpminsw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xea, 0x11 }, { vpminsw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x39, 0xd4 }, { vpminsd ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x39, 0x11 }, { vpminsd ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x39, 0x11 }, { vpminsd ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xda, 0xd4 }, { vpminub ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xda, 0x11 }, { vpminub ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xda, 0x11 }, { vpminub ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x3a, 0xd4 }, { vpminuw ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x3a, 0x11 }, { vpminuw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x3a, 0x11 }, { vpminuw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x3b, 0xd4 }, { vpminud ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x3b, 0x11 }, { vpminud ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x3b, 0x11 }, { vpminud ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xe4, 0xd4 }, { vpmulhuw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xe4, 0x11 }, { vpmulhuw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xe4, 0x11 }, { vpmulhuw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x0b, 0xd4 }, { vpmulhrsw ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x0b, 0x11 }, { vpmulhrsw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x0b, 0x11 }, { vpmulhrsw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xe5, 0xd4 }, { vpmulhw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xe5, 0x11 }, { vpmulhw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xe5, 0x11 }, { vpmulhw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xd5, 0xd4 }, { vpmullw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xd5, 0x11 }, { vpmullw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xd5, 0x11 }, { vpmullw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x40, 0xd4 }, { vpmulld ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x40, 0x11 }, { vpmulld ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x40, 0x11 }, { vpmulld ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xf4, 0xd4 }, { vpmuludq ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xf4, 0x11 }, { vpmuludq ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xf4, 0x11 }, { vpmuludq ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x28, 0xd4 }, { vpmuldq ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x28, 0x11 }, { vpmuldq ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x28, 0x11 }, { vpmuldq ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xeb, 0xd4 }, { vpor ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xeb, 0x11 }, { vpor ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xeb, 0x11 }, { vpor ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xf6, 0xd4 }, { vpsadbw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xf6, 0x11 }, { vpsadbw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xf6, 0x11 }, { vpsadbw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x00, 0xd4 }, { vpshufb ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x00, 0x11 }, { vpshufb ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x00, 0x11 }, { vpshufb ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x08, 0xd4 }, { vpsignb ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x08, 0x11 }, { vpsignb ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x08, 0x11 }, { vpsignb ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x09, 0xd4 }, { vpsignw ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x09, 0x11 }, { vpsignw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x09, 0x11 }, { vpsignw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x0a, 0xd4 }, { vpsignd ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x4d, 0x0a, 0x11 }, { vpsignd ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x4d, 0x0a, 0x11 }, { vpsignd ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xf8, 0xd4 }, { vpsubb ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xf8, 0x11 }, { vpsubb ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xf8, 0x11 }, { vpsubb ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xf9, 0xd4 }, { vpsubw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xf9, 0x11 }, { vpsubw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xf9, 0x11 }, { vpsubw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xfa, 0xd4 }, { vpsubd ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xfa, 0x11 }, { vpsubd ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xfa, 0x11 }, { vpsubd ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xfb, 0xd4 }, { vpsubq ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xfb, 0x11 }, { vpsubq ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xfb, 0x11 }, { vpsubq ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xe8, 0xd4 }, { vpsubsb ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xe8, 0x11 }, { vpsubsb ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xe8, 0x11 }, { vpsubsb ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xe9, 0xd4 }, { vpsubsw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xe9, 0x11 }, { vpsubsw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xe9, 0x11 }, { vpsubsw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xd8, 0xd4 }, { vpsubusb ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xd8, 0x11 }, { vpsubusb ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xd8, 0x11 }, { vpsubusb ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xd9, 0xd4 }, { vpsubusw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xd9, 0x11 }, { vpsubusw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xd9, 0x11 }, { vpsubusw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0x68, 0xd4 }, { vpunpckhbw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x68, 0x11 }, { vpunpckhbw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0x68, 0x11 }, { vpunpckhbw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0x69, 0xd4 }, { vpunpckhwd ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x69, 0x11 }, { vpunpckhwd ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0x69, 0x11 }, { vpunpckhwd ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0x6a, 0xd4 }, { vpunpckhdq ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x6a, 0x11 }, { vpunpckhdq ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0x6a, 0x11 }, { vpunpckhdq ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0x6d, 0xd4 }, { vpunpckhqdq ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x6d, 0x11 }, { vpunpckhqdq ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0x6d, 0x11 }, { vpunpckhqdq ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0x60, 0xd4 }, { vpunpcklbw ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x60, 0x11 }, { vpunpcklbw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0x60, 0x11 }, { vpunpcklbw ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0x61, 0xd4 }, { vpunpcklwd ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x61, 0x11 }, { vpunpcklwd ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0x61, 0x11 }, { vpunpcklwd ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0x62, 0xd4 }, { vpunpckldq ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x62, 0x11 }, { vpunpckldq ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0x62, 0x11 }, { vpunpckldq ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0x6c, 0xd4 }, { vpunpcklqdq ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0x6c, 0x11 }, { vpunpcklqdq ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0x6c, 0x11 }, { vpunpcklqdq ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xef, 0xd4 }, { vpxor ymm2,ymm6,ymm4 } +testcase { 0xc5, 0xcd, 0xef, 0x11 }, { vpxor ymm2,ymm6,YWORD [rcx] } +testcase { 0xc5, 0xcd, 0xef, 0x11 }, { vpxor ymm2,ymm6,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x1c, 0xf4 }, { vpabsb ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x1c, 0x21 }, { vpabsb ymm4,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x1c, 0x21 }, { vpabsb ymm4,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x1d, 0xf4 }, { vpabsw ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x1d, 0x21 }, { vpabsw ymm4,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x1d, 0x21 }, { vpabsw ymm4,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x1e, 0xf4 }, { vpabsd ymm6,ymm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x1e, 0x21 }, { vpabsd ymm4,YWORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x1e, 0x21 }, { vpabsd ymm4,YWORD [rcx] } +testcase { 0xc4, 0xe3, 0x4d, 0x42, 0xd4, 0x07 }, { vmpsadbw ymm2,ymm6,ymm4,0x7 } +testcase { 0xc4, 0xe3, 0x4d, 0x42, 0x11, 0x07 }, { vmpsadbw ymm2,ymm6,YWORD [rcx],0x7 } +testcase { 0xc4, 0xe3, 0x4d, 0x42, 0x11, 0x07 }, { vmpsadbw ymm2,ymm6,YWORD [rcx],0x7 } +testcase { 0xc4, 0xe3, 0x4d, 0x0f, 0xd4, 0x07 }, { vpalignr ymm2,ymm6,ymm4,0x7 } +testcase { 0xc4, 0xe3, 0x4d, 0x0f, 0x11, 0x07 }, { vpalignr ymm2,ymm6,YWORD [rcx],0x7 } +testcase { 0xc4, 0xe3, 0x4d, 0x0f, 0x11, 0x07 }, { vpalignr ymm2,ymm6,YWORD [rcx],0x7 } +testcase { 0xc4, 0xe3, 0x4d, 0x0e, 0xd4, 0x07 }, { vpblendw ymm2,ymm6,ymm4,0x7 } +testcase { 0xc4, 0xe3, 0x4d, 0x0e, 0x11, 0x07 }, { vpblendw ymm2,ymm6,YWORD [rcx],0x7 } +testcase { 0xc4, 0xe3, 0x4d, 0x0e, 0x11, 0x07 }, { vpblendw ymm2,ymm6,YWORD [rcx],0x7 } +testcase { 0xc4, 0xe3, 0x6d, 0x4c, 0xfe, 0x40 }, { vpblendvb ymm7,ymm2,ymm6,ymm4 } +testcase { 0xc4, 0xe3, 0x6d, 0x4c, 0x39, 0x40 }, { vpblendvb ymm7,ymm2,YWORD [rcx],ymm4 } +testcase { 0xc4, 0xe3, 0x6d, 0x4c, 0x39, 0x40 }, { vpblendvb ymm7,ymm2,YWORD [rcx],ymm4 } +testcase { 0xc5, 0xcd, 0xf1, 0xd4 }, { vpsllw ymm2,ymm6,xmm4 } +testcase { 0xc5, 0xcd, 0xf1, 0x11 }, { vpsllw ymm2,ymm6,OWORD [rcx] } +testcase { 0xc5, 0xcd, 0xf1, 0x11 }, { vpsllw ymm2,ymm6,OWORD [rcx] } +testcase { 0xc5, 0xcd, 0xf2, 0xd4 }, { vpslld ymm2,ymm6,xmm4 } +testcase { 0xc5, 0xcd, 0xf2, 0x11 }, { vpslld ymm2,ymm6,OWORD [rcx] } +testcase { 0xc5, 0xcd, 0xf2, 0x11 }, { vpslld ymm2,ymm6,OWORD [rcx] } +testcase { 0xc5, 0xcd, 0xf3, 0xd4 }, { vpsllq ymm2,ymm6,xmm4 } +testcase { 0xc5, 0xcd, 0xf3, 0x11 }, { vpsllq ymm2,ymm6,OWORD [rcx] } +testcase { 0xc5, 0xcd, 0xf3, 0x11 }, { vpsllq ymm2,ymm6,OWORD [rcx] } +testcase { 0xc5, 0xcd, 0xe1, 0xd4 }, { vpsraw ymm2,ymm6,xmm4 } +testcase { 0xc5, 0xcd, 0xe1, 0x11 }, { vpsraw ymm2,ymm6,OWORD [rcx] } +testcase { 0xc5, 0xcd, 0xe1, 0x11 }, { vpsraw ymm2,ymm6,OWORD [rcx] } +testcase { 0xc5, 0xcd, 0xe2, 0xd4 }, { vpsrad ymm2,ymm6,xmm4 } +testcase { 0xc5, 0xcd, 0xe2, 0x11 }, { vpsrad ymm2,ymm6,OWORD [rcx] } +testcase { 0xc5, 0xcd, 0xe2, 0x11 }, { vpsrad ymm2,ymm6,OWORD [rcx] } +testcase { 0xc5, 0xcd, 0xd1, 0xd4 }, { vpsrlw ymm2,ymm6,xmm4 } +testcase { 0xc5, 0xcd, 0xd1, 0x11 }, { vpsrlw ymm2,ymm6,OWORD [rcx] } +testcase { 0xc5, 0xcd, 0xd1, 0x11 }, { vpsrlw ymm2,ymm6,OWORD [rcx] } +testcase { 0xc5, 0xcd, 0xd2, 0xd4 }, { vpsrld ymm2,ymm6,xmm4 } +testcase { 0xc5, 0xcd, 0xd2, 0x11 }, { vpsrld ymm2,ymm6,OWORD [rcx] } +testcase { 0xc5, 0xcd, 0xd2, 0x11 }, { vpsrld ymm2,ymm6,OWORD [rcx] } +testcase { 0xc5, 0xcd, 0xd3, 0xd4 }, { vpsrlq ymm2,ymm6,xmm4 } +testcase { 0xc5, 0xcd, 0xd3, 0x11 }, { vpsrlq ymm2,ymm6,OWORD [rcx] } +testcase { 0xc5, 0xcd, 0xd3, 0x11 }, { vpsrlq ymm2,ymm6,OWORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x20, 0xe4 }, { vpmovsxbw ymm4,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x20, 0x21 }, { vpmovsxbw ymm4,OWORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x20, 0x21 }, { vpmovsxbw ymm4,OWORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x23, 0xe4 }, { vpmovsxwd ymm4,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x23, 0x21 }, { vpmovsxwd ymm4,OWORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x23, 0x21 }, { vpmovsxwd ymm4,OWORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x25, 0xe4 }, { vpmovsxdq ymm4,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x25, 0x21 }, { vpmovsxdq ymm4,OWORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x25, 0x21 }, { vpmovsxdq ymm4,OWORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x30, 0xe4 }, { vpmovzxbw ymm4,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x30, 0x21 }, { vpmovzxbw ymm4,OWORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x30, 0x21 }, { vpmovzxbw ymm4,OWORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x33, 0xe4 }, { vpmovzxwd ymm4,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x33, 0x21 }, { vpmovzxwd ymm4,OWORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x33, 0x21 }, { vpmovzxwd ymm4,OWORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x35, 0xe4 }, { vpmovzxdq ymm4,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x35, 0x21 }, { vpmovzxdq ymm4,OWORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x35, 0x21 }, { vpmovzxdq ymm4,OWORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x21, 0xf4 }, { vpmovsxbd ymm6,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x21, 0x21 }, { vpmovsxbd ymm4,QWORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x21, 0x21 }, { vpmovsxbd ymm4,QWORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x24, 0xf4 }, { vpmovsxwq ymm6,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x24, 0x21 }, { vpmovsxwq ymm4,QWORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x24, 0x21 }, { vpmovsxwq ymm4,QWORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x31, 0xf4 }, { vpmovzxbd ymm6,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x31, 0x21 }, { vpmovzxbd ymm4,QWORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x31, 0x21 }, { vpmovzxbd ymm4,QWORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x34, 0xf4 }, { vpmovzxwq ymm6,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x34, 0x21 }, { vpmovzxwq ymm4,QWORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x34, 0x21 }, { vpmovzxwq ymm4,QWORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x22, 0xe4 }, { vpmovsxbq ymm4,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x22, 0x21 }, { vpmovsxbq ymm4,DWORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x22, 0x21 }, { vpmovsxbq ymm4,DWORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x32, 0xe4 }, { vpmovzxbq ymm4,xmm4 } +testcase { 0xc4, 0xe2, 0x7d, 0x32, 0x21 }, { vpmovzxbq ymm4,DWORD [rcx] } +testcase { 0xc4, 0xe2, 0x7d, 0x32, 0x21 }, { vpmovzxbq ymm4,DWORD [rcx] } + +; EOF diff --git a/travis/test/avx2.bin.t b/travis/test/avx2.bin.t new file mode 100644 index 0000000000000000000000000000000000000000..60977f369570fefa9154eda958ccb0522682f32d GIT binary patch literal 7970 zcmeI0%}-NV7{*Ke05#FDF_KJ;s3bbG5rvWZNlbt=u?u%N856%1$0mwm?4tj{WP-RE z7Hs%i+6BpUp%zC}P%qS2wHmc0_|Y=YbI!fzzV}o}Cd_Km1?TzQ_ne+{-}~PCgmcnP zVdQu!ly(Ytl@#?=QD04tbhI^vLg*$fEG{l;LdcE%8Fnde#^uepycw6*;|BEX1A6v^ zzDnq;6J{-vo`a<4An7?k?ph=>&RvT!cdcQS(7+uf34N8&S0{$Oyh!dGAa^a0yVkH- z3uMN5Yayn`74+-{J$q4K74_AmS&O9SAi2-Rtc95O49!}MnQ`t~r+#lwJMlkS)6O(0 z3!1GoJZxm!&Niet1a{&-=h!r(*-Y9@>Lc}mvZO32-pg1osfX0VUQ(8n`VotzT1sfP zl+v^Da1P7F!_91a759=)b(K`hg;T%aCo#?+>x-tH3DN{9#+72dB+eh}VJ~TdbdniO zp_xrZUt+RUv=x)ZnCt}ejH#t#T-r&VEV1FOky48K=Rp04CHvW{C`n3k94SRg-e&AJ zW26)*iQF9j;re7A^HLAoe(Wd#pMiMzRt17(uxeo!Bv=)zG@?Gs6se|ED0Q%4D4r>s zRXeMIb`^uAwCd>>)l{~oyt2rq(lzBq>4QbLD<3Ss{SE|Q1nX_EUJ2{H@LrBg`q8=q=vKZr;gmM9w2}9(ncXhk z81BdsT`$M^+|Ux0pweujR5et~|4euch*zJeB@1?VH_ zBj^-#3VIoO89D$RfL?)KfhM2{=xOL_=o#o4=vnAl=vC-d=zHjU+)?U>5*vD9gcKod zC2fV{#*Zn3KSsZZZ&JKT@kYfP$%*6DZnn|xO!fn2{eam&LO()3K|euXKwm%|r~|zR zy$8Jyy$^i=eZaffMhD-C671nCRX z8>Bx-kB~kgy+Znh?-@bgKswSqq=EP*Qez~Rn^=}&`HE#OmcvM!!Oi$yQ{y+%bTHC) zo}l}n%eSB!8?wAe8WMi!yHe1Z(B<1xjYUbH!bsn&f`)}I=~}*X1>Fn7dX8X_m2B?j|h`b4s6+UMKxddY<$>>3!1wqz6hLlwK(PPDMd^*wAEih7K3U_H zmSF~5^E=jAYoIkY8n?_eZCR?cRcWo#UZurKo0V4U+ii{ITE1(UujRm&4O?Dp8M5Wd zmNi@cY?-ulYGv2htuDQ34UdleIuuHWNAD^b(^q5aN^N7!M%CMlnN21)xq3qf@-|~; zlgXI78S^%oT-l5(>vfmeActFYCM`Ozh`x&GytqBq zd6C?Ws>zEnJwLa{W}LU7HF>dD-!I6`i=^+Dr0 Date: Mon, 24 Aug 2020 18:03:32 +0300 Subject: [PATCH 06/34] travis: add xpaste test Signed-off-by: Cyrill Gorcunov --- travis/test/xpaste.asm | 6 ++++++ travis/test/xpaste.bin.t | 1 + travis/test/xpaste.json | 11 +++++++++++ 3 files changed, 18 insertions(+) create mode 100644 travis/test/xpaste.asm create mode 100644 travis/test/xpaste.bin.t create mode 100644 travis/test/xpaste.json diff --git a/travis/test/xpaste.asm b/travis/test/xpaste.asm new file mode 100644 index 00000000..cb994588 --- /dev/null +++ b/travis/test/xpaste.asm @@ -0,0 +1,6 @@ +%iassign OWORD_size 16 ; octo-word +%idefine sizeof(_x_) _x_%+_size + +%define ptr eax+sizeof(oword) + +movdqa [ptr], xmm1 diff --git a/travis/test/xpaste.bin.t b/travis/test/xpaste.bin.t new file mode 100644 index 00000000..59bb2f04 --- /dev/null +++ b/travis/test/xpaste.bin.t @@ -0,0 +1 @@ +gfH \ No newline at end of file diff --git a/travis/test/xpaste.json b/travis/test/xpaste.json new file mode 100644 index 00000000..31721c15 --- /dev/null +++ b/travis/test/xpaste.json @@ -0,0 +1,11 @@ +[ + { + "description": "Test preproc xdefine", + "id": "xpaste", + "source": "xpaste.asm", + "option": "-f bin -Ox", + "target": [ + { "output": "xpaste.bin" } + ] + } +] From 63ccbf4f5fed724037c48de1a767cfa7290fdf19 Mon Sep 17 00:00:00 2001 From: Cyrill Gorcunov Date: Mon, 24 Aug 2020 18:22:48 +0300 Subject: [PATCH 07/34] travis: nasm-t -- add ability to generate new tests Just to not fill descriptor by hands every time. Signed-off-by: Cyrill Gorcunov --- travis/nasm-t.py | 118 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 118 insertions(+) diff --git a/travis/nasm-t.py b/travis/nasm-t.py index 8a2ddb49..7a1e5506 100755 --- a/travis/nasm-t.py +++ b/travis/nasm-t.py @@ -34,6 +34,46 @@ for cmd in ['run']: help = 'Run the selected test only', required = False) +for cmd in ['new']: + spp = sp.add_parser(cmd, help = 'Add a new test case') + spp.add_argument('--description', + dest = 'description', default = "Description of a test", + help = 'Description of a test', + required = False) + spp.add_argument('--id', + dest = 'id', + help = 'Test identifier/name', + required = True) + spp.add_argument('--format', + dest = 'format', default = 'bin', + help = 'Output format', + required = False) + spp.add_argument('--source', + dest = 'source', + help = 'Source file', + required = False) + spp.add_argument('--option', + dest = 'option', + default = '-Ox', + help = 'NASM options', + required = False) + spp.add_argument('--ref', + dest = 'ref', + help = 'Test reference', + required = False) + spp.add_argument('--output', + dest = 'output', default = 'y', + help = 'Output (compiled) file name (or "y")', + required = False) + spp.add_argument('--stdout', + dest = 'stdout', default = 'y', + help = 'Filename of stdout file (or "y")', + required = False) + spp.add_argument('--stderr', + dest = 'stderr', default = 'y', + help = 'Filename of stderr file (or "y")', + required = False) + for cmd in ['list']: spp = sp.add_parser(cmd, help = 'List test cases') @@ -44,6 +84,27 @@ for cmd in ['update']: help = 'Update the selected test only', required = False) +map_fmt_ext = { + 'bin': '.bin', + 'elf': '.o', + 'elf64': '.o', + 'elf32': '.o', + 'elfx32': '.o', + 'ith': '.ith', + 'srec': '.srec', + 'obj': '.obj', + 'win32': '.obj', + 'win64': '.obj', + 'coff': '.obj', + 'macho': '.o', + 'macho32': '.o', + 'macho64': '.o', + 'aout': '.out', + 'aoutb': '.out', + 'as86': '.o', + 'rdf': '.rdf', +} + args = parser.parse_args() if args.cmd == None: @@ -395,6 +456,63 @@ def test_update(desc): return test_updated(desc['_test-name']) +# +# Create a new empty test case +if args.cmd == 'new': + # + # If no source provided create one + # from (ID which is required) + if not args.source: + args.source = args.id + ".asm" + + # + # Emulate "touch" on source file + path_asm = args.dir + os.sep + args.source + print("\tCreating %s" % (path_asm)) + open(path_asm, 'a').close() + + # + # Fill the test descriptor + # + # FIXME: We should probably use Jinja + path_json = args.dir + os.sep + args.id + ".json" + print("\tFilling descriptor %s" % (path_json)) + with open(path_json, 'wb') as f: + f.write("[\n\t{\n".encode("utf-8")) + acc = [] + if args.description: + acc.append("\t\t\"description\": \"{}\"".format(args.description)) + acc.append("\t\t\"id\": \"{}\"".format(args.id)) + if args.format: + acc.append("\t\t\"format\": \"{}\"".format(args.format)) + acc.append("\t\t\"source\": \"{}\"".format(args.source)) + if args.option: + acc.append("\t\t\"option\": \"{}\"".format(args.option)) + if args.ref: + acc.append("\t\t\"ref\": \"{}\"".format(args.ref)) + f.write(",\n".join(acc).encode("utf-8")) + if args.output or args.stdout or args.stderr: + acc = [] + if args.output: + if args.output == 'y': + if args.format in map_fmt_ext: + args.output = args.id + map_fmt_ext[args.format] + acc.append("\t\t\t{{ \"output\": \"{}\" }}".format(args.output)) + if args.stdout: + if args.stdout == 'y': + args.stdout = args.id + '.stdout' + acc.append("\t\t\t{{ \"stdout\": \"{}\" }}".format(args.stdout)) + if args.stderr: + if args.stderr == 'y': + args.stderr = args.id + '.stderr' + acc.append("\t\t\t{{ \"stderr\": \"{}\" }}".format(args.stderr)) + f.write(",\n".encode("utf-8")) + f.write("\t\t\"target\": [\n".encode("utf-8")) + f.write(",\n".join(acc).encode("utf-8")) + f.write("\n\t\t]".encode("utf-8")) + f.write("\n\t}\n]\n".encode("utf-8")) + f.close() + if args.cmd == 'run': desc_array = [] if args.test == None: From 7f3cfafbd991176012f21d6446dbf96e93bbbfd7 Mon Sep 17 00:00:00 2001 From: Cyrill Gorcunov Date: Tue, 25 Aug 2020 14:40:10 +0300 Subject: [PATCH 08/34] travis: add br3392275 Signed-off-by: Cyrill Gorcunov --- travis/test/br3392275.asm | 10 ++++++++++ travis/test/br3392275.bin.t | 1 + travis/test/br3392275.json | 12 ++++++++++++ 3 files changed, 23 insertions(+) create mode 100644 travis/test/br3392275.asm create mode 100644 travis/test/br3392275.bin.t create mode 100644 travis/test/br3392275.json diff --git a/travis/test/br3392275.asm b/travis/test/br3392275.asm new file mode 100644 index 00000000..c37343d4 --- /dev/null +++ b/travis/test/br3392275.asm @@ -0,0 +1,10 @@ + bits 32 + + blendvpd xmm2,xmm1,xmm0 + blendvpd xmm2,xmm1 + blendvps xmm2,xmm1,xmm0 + blendvps xmm2,xmm1 + pblendvb xmm2,xmm1,xmm0 + pblendvb xmm2,xmm1 + sha256rnds2 xmm2,xmm1,xmm0 + sha256rnds2 xmm2,xmm1 diff --git a/travis/test/br3392275.bin.t b/travis/test/br3392275.bin.t new file mode 100644 index 00000000..9f704492 --- /dev/null +++ b/travis/test/br3392275.bin.t @@ -0,0 +1 @@ +f8Ñf8Ñf8Ñf8Ñf8Ñf8Ñ8ËÑ8ËÑ \ No newline at end of file diff --git a/travis/test/br3392275.json b/travis/test/br3392275.json new file mode 100644 index 00000000..3d48812d --- /dev/null +++ b/travis/test/br3392275.json @@ -0,0 +1,12 @@ +[ + { + "id": "br3392275", + "description": "Do not require xmm0 to be explicitly declared when implicit", + "format": "bin", + "source": "br3392275.asm", + "option": "-Ox", + "target": [ + { "output": "br3392275.bin" } + ] + } +] From d9eed2bec786aa7e90d7ee005baed8ca4a3dbadd Mon Sep 17 00:00:00 2001 From: Cyrill Gorcunov Date: Tue, 25 Aug 2020 14:45:48 +0300 Subject: [PATCH 09/34] travis: add xdefine test Signed-off-by: Cyrill Gorcunov --- travis/test/xdefine.asm | 15 +++++++++++++++ travis/test/xdefine.bin.t | 1 + travis/test/xdefine.json | 12 ++++++++++++ 3 files changed, 28 insertions(+) create mode 100644 travis/test/xdefine.asm create mode 100644 travis/test/xdefine.bin.t create mode 100644 travis/test/xdefine.json diff --git a/travis/test/xdefine.asm b/travis/test/xdefine.asm new file mode 100644 index 00000000..5c510cd6 --- /dev/null +++ b/travis/test/xdefine.asm @@ -0,0 +1,15 @@ +%idefine d dword +%define _1digits_nocheck(d) (((d)% 10)+'0') +%xdefine _1digits(d) (!!(d/10)*(1<<32)+ _1digits_nocheck(d)) + + db _1digits(8) ; Should be 0x38 + +%define n 0x21 +%xdefine ctr n +%define n 0x22 + + db ctr, n ; Should be 0x21, 0x22 + +%define MNSUFFIX +%define MNCURRENT TEST%[MNSUFFIX] +%xdefine var MNCURRENT diff --git a/travis/test/xdefine.bin.t b/travis/test/xdefine.bin.t new file mode 100644 index 00000000..6ad8beef --- /dev/null +++ b/travis/test/xdefine.bin.t @@ -0,0 +1 @@ +8!" \ No newline at end of file diff --git a/travis/test/xdefine.json b/travis/test/xdefine.json new file mode 100644 index 00000000..39479ec0 --- /dev/null +++ b/travis/test/xdefine.json @@ -0,0 +1,12 @@ +[ + { + "description": "Test weird defines", + "id": "xdefine", + "format": "bin", + "source": "xdefine.asm", + "option": "-Ox", + "target": [ + { "output": "xdefine.bin" } + ] + } +] From 4b3ac4eefd74ee7ee0b7c3bd837b78d37f12028c Mon Sep 17 00:00:00 2001 From: Cyrill Gorcunov Date: Tue, 25 Aug 2020 15:31:24 +0300 Subject: [PATCH 10/34] travis: nasm-t -- add ability to disable test Signed-off-by: Cyrill Gorcunov --- travis/nasm-t.py | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/travis/nasm-t.py b/travis/nasm-t.py index 7a1e5506..8907692e 100755 --- a/travis/nasm-t.py +++ b/travis/nasm-t.py @@ -378,6 +378,9 @@ def exec_nasm(desc): def test_run(desc): print("=== Running %s ===" % (desc['_test-name'])) + if 'disable' in desc: + return test_skip(desc['_test-name'], desc["disable"]) + pnasm, stdout, stderr = exec_nasm(desc) if pnasm == None: return False @@ -430,6 +433,8 @@ def test_update(desc): if 'update' in desc and desc['update'] == 'false': return test_skip(desc['_test-name'], "No output provided") + if 'disable' in desc: + return test_skip(desc['_test-name'], desc["disable"]) pnasm, stdout, stderr = exec_nasm(desc) if pnasm == None: From 8142ab699d9ec866c2f7ecb28cb35c41e1f14230 Mon Sep 17 00:00:00 2001 From: Cyrill Gorcunov Date: Tue, 25 Aug 2020 15:27:54 +0300 Subject: [PATCH 11/34] travis: add winalign It is disabled by now -- we need to teach nasm-t to skip some parts of output (due to format specifics). Signed-off-by: Cyrill Gorcunov --- travis/test/winalign.asm | 45 +++++++++++++++++++++++++++++++++++++ travis/test/winalign.json | 14 ++++++++++++ travis/test/winalign.obj.t | Bin 0 -> 642 bytes 3 files changed, 59 insertions(+) create mode 100644 travis/test/winalign.asm create mode 100644 travis/test/winalign.json create mode 100644 travis/test/winalign.obj.t diff --git a/travis/test/winalign.asm b/travis/test/winalign.asm new file mode 100644 index 00000000..cad0a376 --- /dev/null +++ b/travis/test/winalign.asm @@ -0,0 +1,45 @@ + section .pdata rdata align=2 + dd 1 + dd 2 + dd 3 + + section .rdata align=16 + dd 4 + dd 5 + dd 6 + + section ultra + dd 10 + dd 11 + dd 12 + + section infra rdata + dd 20 + dd 21 + dd 22 + + section omega rdata align=1 + dd 90 + dd 91 + dd 92 + + section .xdata + dd 7 + dd 8 + dd 9 + + section ultra align=8 + dd 13 + dd 14 + dd 15 + + section infra rdata align=1 + dd 23 + dd 24 + dd 25 + + section omega rdata + sectalign 2 + dd 93 + dd 94 + dd 95 diff --git a/travis/test/winalign.json b/travis/test/winalign.json new file mode 100644 index 00000000..97ac1a83 --- /dev/null +++ b/travis/test/winalign.json @@ -0,0 +1,14 @@ +[ + { + "description": "COFF alignment based on BR3392692", + "id": "winalign", + "format": "win64", + "source": "winalign.asm", + "error": "over", + "disable": "Unable to compare coff output", + "option": "-Ox", + "target": [ + { "output": "winalign.obj" } + ] + } +] diff --git a/travis/test/winalign.obj.t b/travis/test/winalign.obj.t new file mode 100644 index 0000000000000000000000000000000000000000..b47b6dc2563ac7c3fc01158189596f60085fb22a GIT binary patch literal 642 zcmZvY%}&BV6oqdsARsCW0Zm-+1ZCp`+=WXQuKmLyEo74N6FQ(z;Kp~ho&z?S+TP^L zWYVvbb5H!$lJER}x(P%sLx@|+xJ9i5MCM}QOId`vf{Jz;uo#S`S?rJleS+-7hjtO$?9v<5M1=oK$ A4gdfE literal 0 HcmV?d00001 From e2917fd7758f5c45eb416d9c30320c4c2c9432c0 Mon Sep 17 00:00:00 2001 From: Cyrill Gorcunov Date: Tue, 25 Aug 2020 15:35:49 +0300 Subject: [PATCH 12/34] travis: add vpcmp Signed-off-by: Cyrill Gorcunov --- travis/test/vpcmp.asm | 28 ++++++++++++++++++++++++++++ travis/test/vpcmp.bin.t | Bin 0 -> 160 bytes travis/test/vpcmp.json | 12 ++++++++++++ 3 files changed, 40 insertions(+) create mode 100644 travis/test/vpcmp.asm create mode 100644 travis/test/vpcmp.bin.t create mode 100644 travis/test/vpcmp.json diff --git a/travis/test/vpcmp.asm b/travis/test/vpcmp.asm new file mode 100644 index 00000000..acc8ef37 --- /dev/null +++ b/travis/test/vpcmp.asm @@ -0,0 +1,28 @@ + bits 64 + + vpcmpeqb k2{k2},zmm0,zmm1 + vpcmpgtb k2{k2},zmm0,zmm1 + vpcmpeqw k2{k2},zmm0,zmm1 + vpcmpgtw k2{k2},zmm0,zmm1 + vpcmpeqd k2{k2},zmm0,zmm1 + vpcmpgtd k2{k2},zmm0,zmm1 + vpcmpeqq k2{k2},zmm0,zmm1 + vpcmpgtq k2{k2},zmm0,zmm1 + + vpcmpb k2{k2},zmm0,zmm1,0 + vpcmpb k2{k2},zmm0,zmm1,6 + vpcmpw k2{k2},zmm0,zmm1,0 + vpcmpw k2{k2},zmm0,zmm1,6 + vpcmpd k2{k2},zmm0,zmm1,0 + vpcmpd k2{k2},zmm0,zmm1,6 + vpcmpq k2{k2},zmm0,zmm1,0 + vpcmpq k2{k2},zmm0,zmm1,6 + + vpcmpneqb k2{k2},zmm0,zmm1 + vpcmpleb k2{k2},zmm0,zmm1 + vpcmpneqw k2{k2},zmm0,zmm1 + vpcmplew k2{k2},zmm0,zmm1 + vpcmpneqd k2{k2},zmm0,zmm1 + vpcmpled k2{k2},zmm0,zmm1 + vpcmpneqq k2{k2},zmm0,zmm1 + vpcmpleq k2{k2},zmm0,zmm1 diff --git a/travis/test/vpcmp.bin.t b/travis/test/vpcmp.bin.t new file mode 100644 index 0000000000000000000000000000000000000000..0ac4dfe04c75fb1db8bba15661253c776c4be078 GIT binary patch literal 160 zcmXAgu?>JQ3Qm0DeWYQ+OiF$QHqtQssxR5i*@dACL&vYc5bz880eosvIRF3v literal 0 HcmV?d00001 diff --git a/travis/test/vpcmp.json b/travis/test/vpcmp.json new file mode 100644 index 00000000..c98da198 --- /dev/null +++ b/travis/test/vpcmp.json @@ -0,0 +1,12 @@ +[ + { + "description": "Test vpcmp instruction", + "id": "vpcmp", + "format": "bin", + "source": "vpcmp.asm", + "option": "-Ox", + "target": [ + { "output": "vpcmp.bin" } + ] + } +] From 186c28395fac245c552608ec98fd233389595993 Mon Sep 17 00:00:00 2001 From: Cyrill Gorcunov Date: Tue, 25 Aug 2020 15:39:44 +0300 Subject: [PATCH 13/34] travis: add warnstack Signed-off-by: Cyrill Gorcunov --- travis/test/warnstack.asm | 10 ++++++++++ travis/test/warnstack.json | 12 ++++++++++++ travis/test/warnstack.stderr | 5 +++++ travis/test/warnstack.stdout | 9 +++++++++ 4 files changed, 36 insertions(+) create mode 100644 travis/test/warnstack.asm create mode 100644 travis/test/warnstack.json create mode 100644 travis/test/warnstack.stderr create mode 100644 travis/test/warnstack.stdout diff --git a/travis/test/warnstack.asm b/travis/test/warnstack.asm new file mode 100644 index 00000000..6e762904 --- /dev/null +++ b/travis/test/warnstack.asm @@ -0,0 +1,10 @@ +%warning "Good warning" + [warning push] + [warning -user] +%warning "Bad warning" + [warning pop] +%warning "Good warning" + [warning -user] +%warning "Bad warning" + [warning pop] ; should warn but reset all +%warning "Good warning" diff --git a/travis/test/warnstack.json b/travis/test/warnstack.json new file mode 100644 index 00000000..18f27fc6 --- /dev/null +++ b/travis/test/warnstack.json @@ -0,0 +1,12 @@ +[ + { + "description": "Test warning stack", + "id": "warnstack", + "source": "warnstack.asm", + "option": "-E", + "target": [ + { "stdout": "warnstack.stdout" }, + { "stderr": "warnstack.stderr" } + ] + } +] diff --git a/travis/test/warnstack.stderr b/travis/test/warnstack.stderr new file mode 100644 index 00000000..91fbf65f --- /dev/null +++ b/travis/test/warnstack.stderr @@ -0,0 +1,5 @@ +./travis/test/warnstack.asm:1: warning: Good warning [-w+user] +./travis/test/warnstack.asm:4: warning: Bad warning [-w+user] +./travis/test/warnstack.asm:6: warning: Good warning [-w+user] +./travis/test/warnstack.asm:8: warning: Bad warning [-w+user] +./travis/test/warnstack.asm:10: warning: Good warning [-w+user] \ No newline at end of file diff --git a/travis/test/warnstack.stdout b/travis/test/warnstack.stdout new file mode 100644 index 00000000..51db543c --- /dev/null +++ b/travis/test/warnstack.stdout @@ -0,0 +1,9 @@ +%line 2+1 ./travis/test/warnstack.asm + [warning push] + [warning -user] + + [warning pop] + + [warning -user] + + [warning pop] \ No newline at end of file From 70eb4a0885da2db265c6505517873a2d5dba694a Mon Sep 17 00:00:00 2001 From: Cyrill Gorcunov Date: Tue, 25 Aug 2020 16:23:22 +0300 Subject: [PATCH 14/34] travis: add vgather Signed-off-by: Cyrill Gorcunov --- travis/test/vgather.asm | 76 ++++++++++++++++++++++++++++++++++++++ travis/test/vgather.bin.t | Bin 0 -> 440 bytes travis/test/vgather.json | 12 ++++++ 3 files changed, 88 insertions(+) create mode 100644 travis/test/vgather.asm create mode 100644 travis/test/vgather.bin.t create mode 100644 travis/test/vgather.json diff --git a/travis/test/vgather.asm b/travis/test/vgather.asm new file mode 100644 index 00000000..4012bf28 --- /dev/null +++ b/travis/test/vgather.asm @@ -0,0 +1,76 @@ + bits 64 + + vgatherdpd xmm0,[rcx+xmm2],xmm3 + vgatherqpd xmm0,[rcx+xmm2],xmm3 + vgatherdpd ymm0,[rcx+xmm2],ymm3 + vgatherqpd ymm0,[rcx+ymm2],ymm3 + + vgatherdpd xmm0,[rcx+xmm2*1],xmm3 + vgatherqpd xmm0,[rcx+xmm2*1],xmm3 + vgatherdpd ymm0,[rcx+xmm2*1],ymm3 + vgatherqpd ymm0,[rcx+ymm2*1],ymm3 + + vgatherdpd xmm0,[rcx+xmm2*2],xmm3 + vgatherqpd xmm0,[rcx+xmm2*2],xmm3 + vgatherdpd ymm0,[rcx+xmm2*2],ymm3 + vgatherqpd ymm0,[rcx+ymm2*2],ymm3 + + vgatherdpd xmm0,[rcx+xmm2*4],xmm3 + vgatherqpd xmm0,[rcx+xmm2*4],xmm3 + vgatherdpd ymm0,[rcx+xmm2*4],ymm3 + vgatherqpd ymm0,[rcx+ymm2*4],ymm3 + + vgatherdpd xmm0,[rcx+xmm2*8],xmm3 + vgatherqpd xmm0,[rcx+xmm2*8],xmm3 + vgatherdpd ymm0,[rcx+xmm2*8],ymm3 + vgatherqpd ymm0,[rcx+ymm2*8],ymm3 + + vgatherdpd xmm0,[xmm2],xmm3 + vgatherqpd xmm0,[xmm2],xmm3 + vgatherdpd ymm0,[xmm2],ymm3 + vgatherqpd ymm0,[ymm2],ymm3 + + vgatherdpd xmm0,[xmm2*1],xmm3 + vgatherqpd xmm0,[xmm2*1],xmm3 + vgatherdpd ymm0,[xmm2*1],ymm3 + vgatherqpd ymm0,[ymm2*1],ymm3 + + vgatherdpd xmm0,[xmm2*2],xmm3 + vgatherqpd xmm0,[xmm2*2],xmm3 + vgatherdpd ymm0,[xmm2*2],ymm3 + vgatherqpd ymm0,[ymm2*2],ymm3 + + vgatherdpd xmm0,[xmm2*4],xmm3 + vgatherqpd xmm0,[xmm2*4],xmm3 + vgatherdpd ymm0,[xmm2*4],ymm3 + vgatherqpd ymm0,[ymm2*4],ymm3 + + vgatherdpd xmm0,[xmm2*8],xmm3 + vgatherqpd xmm0,[xmm2*8],xmm3 + vgatherdpd ymm0,[xmm2*8],ymm3 + vgatherqpd ymm0,[ymm2*8],ymm3 + + vgatherdpd xmm0,[xmm2+rcx],xmm3 + vgatherqpd xmm0,[xmm2+rcx],xmm3 + vgatherdpd ymm0,[xmm2+rcx],ymm3 + vgatherqpd ymm0,[ymm2+rcx],ymm3 + + vgatherdpd xmm0,[xmm2*1+rcx],xmm3 + vgatherqpd xmm0,[xmm2*1+rcx],xmm3 + vgatherdpd ymm0,[xmm2*1+rcx],ymm3 + vgatherqpd ymm0,[ymm2*1+rcx],ymm3 + + vgatherdpd xmm0,[xmm2*2+rcx],xmm3 + vgatherqpd xmm0,[xmm2*2+rcx],xmm3 + vgatherdpd ymm0,[xmm2*2+rcx],ymm3 + vgatherqpd ymm0,[ymm2*2+rcx],ymm3 + + vgatherdpd xmm0,[xmm2*4+rcx],xmm3 + vgatherqpd xmm0,[xmm2*4+rcx],xmm3 + vgatherdpd ymm0,[xmm2*4+rcx],ymm3 + vgatherqpd ymm0,[ymm2*4+rcx],ymm3 + + vgatherdpd xmm0,[xmm2*8+rcx],xmm3 + vgatherqpd xmm0,[xmm2*8+rcx],xmm3 + vgatherdpd ymm0,[xmm2*8+rcx],ymm3 + vgatherqpd ymm0,[ymm2*8+rcx],ymm3 diff --git a/travis/test/vgather.bin.t b/travis/test/vgather.bin.t new file mode 100644 index 0000000000000000000000000000000000000000..4fd450d1cd5cc2e8c2d1a5103a85c06e825fabb3 GIT binary patch literal 440 zcmchTu?>JQ3)135o<&fNIN^&}tLvp7n$!VGRbnC`F%);3H+S|rnH}=9TjJ;#@y3q@>FnZVM Sb)y$%Vf1Fb0djZ#@c$kGf6=c1 literal 0 HcmV?d00001 diff --git a/travis/test/vgather.json b/travis/test/vgather.json new file mode 100644 index 00000000..838537b8 --- /dev/null +++ b/travis/test/vgather.json @@ -0,0 +1,12 @@ +[ + { + "description": "Test vgather instruction", + "id": "vgather", + "format": "bin", + "source": "vgather.asm", + "option": "-Ox", + "target": [ + { "output": "vgather.bin" } + ] + } +] From 852e80b01153a1a56b7408b7808d04307388b535 Mon Sep 17 00:00:00 2001 From: Cyrill Gorcunov Date: Tue, 25 Aug 2020 16:32:25 +0300 Subject: [PATCH 15/34] travis: add vex Signed-off-by: Cyrill Gorcunov --- travis/test/vex.asm | 9 +++++++++ travis/test/vex.bin.t | 1 + travis/test/vex.json | 21 +++++++++++++++++++++ travis/test/vex.stderr | 1 + 4 files changed, 32 insertions(+) create mode 100644 travis/test/vex.asm create mode 100644 travis/test/vex.bin.t create mode 100644 travis/test/vex.json create mode 100644 travis/test/vex.stderr diff --git a/travis/test/vex.asm b/travis/test/vex.asm new file mode 100644 index 00000000..6772c7ce --- /dev/null +++ b/travis/test/vex.asm @@ -0,0 +1,9 @@ + bits 64 + vcomisd xmm0,xmm31 + vcomisd xmm0,xmm1 + {vex2} vcomisd xmm0,xmm1 + {vex3} vcomisd xmm0,xmm1 + {evex} vcomisd xmm0,xmm1 +%ifdef ERROR + {vex3} add eax,edx +%endif diff --git a/travis/test/vex.bin.t b/travis/test/vex.bin.t new file mode 100644 index 00000000..2145d4cf --- /dev/null +++ b/travis/test/vex.bin.t @@ -0,0 +1 @@ +b‘ý/ÇÅù/ÁÅù/ÁÄáy/Ábñý/Á \ No newline at end of file diff --git a/travis/test/vex.json b/travis/test/vex.json new file mode 100644 index 00000000..e1db1923 --- /dev/null +++ b/travis/test/vex.json @@ -0,0 +1,21 @@ +[ + { + "description": "Test VEX2/VEX3/EVEX prefix", + "id": "vex", + "format": "bin", + "source": "vex.asm", + "option": "-Ox", + "target": [ + { "output": "vex.bin" } + ] + }, + { + "description": "Test VEX3 prefix error", + "ref": "vex", + "option": "-Ox -DERROR -o vex.bin.err", + "target": [ + { "stderr": "vex.stderr" } + ], + "error": "expected" + } +] diff --git a/travis/test/vex.stderr b/travis/test/vex.stderr new file mode 100644 index 00000000..2d8858bc --- /dev/null +++ b/travis/test/vex.stderr @@ -0,0 +1 @@ +./travis/test/vex.asm:8: error: specific encoding scheme not available \ No newline at end of file From f2854471acedd4e05d659acf0694ba69cca22e12 Mon Sep 17 00:00:00 2001 From: Cyrill Gorcunov Date: Tue, 25 Aug 2020 16:35:54 +0300 Subject: [PATCH 16/34] travis: add vaesenc Signed-off-by: Cyrill Gorcunov --- travis/test/vaesenc.asm | 20 ++++++++++++++++++++ travis/test/vaesenc.bin.t | Bin 0 -> 93 bytes travis/test/vaesenc.json | 12 ++++++++++++ 3 files changed, 32 insertions(+) create mode 100644 travis/test/vaesenc.asm create mode 100644 travis/test/vaesenc.bin.t create mode 100644 travis/test/vaesenc.json diff --git a/travis/test/vaesenc.asm b/travis/test/vaesenc.asm new file mode 100644 index 00000000..38e19364 --- /dev/null +++ b/travis/test/vaesenc.asm @@ -0,0 +1,20 @@ + bits 64 + aesenc xmm0,xmm4 + vaesenc zmm0,zmm0,zmm4 + vpclmullqlqdq zmm1,zmm1,zmm5 + vpclmulqdq zmm0, zmm1, zmm2, 0 + vaesenclast zmm0, zmm1, zmm2 + + bits 32 + aesenc xmm0,xmm4 + vaesenc zmm0,zmm0,zmm4 + vpclmullqlqdq zmm1,zmm1,zmm5 + vpclmulqdq zmm0, zmm1, zmm2, 0 + vaesenclast zmm0, zmm1, zmm2 + + bits 16 + aesenc xmm0,xmm4 + vaesenc zmm0,zmm0,zmm4 + vpclmullqlqdq zmm1,zmm1,zmm5 + vpclmulqdq zmm0, zmm1, zmm2, 0 + vaesenclast zmm0, zmm1, zmm2 diff --git a/travis/test/vaesenc.bin.t b/travis/test/vaesenc.bin.t new file mode 100644 index 0000000000000000000000000000000000000000..b312920d3b3beadbab49ca4f682fcb192b73065b GIT binary patch literal 93 lcmYe}x43g8=~Jx-ko;Wg;c}J%OdVoK`c&$1_fQ%|(g41nFVp}4 literal 0 HcmV?d00001 diff --git a/travis/test/vaesenc.json b/travis/test/vaesenc.json new file mode 100644 index 00000000..479c73b3 --- /dev/null +++ b/travis/test/vaesenc.json @@ -0,0 +1,12 @@ +[ + { + "description": "Test AES inctructions (BR 3392454, 3392460)", + "id": "vaesenc", + "format": "bin", + "source": "vaesenc.asm", + "option": "-Ox", + "target": [ + { "output": "vaesenc.bin" } + ] + } +] From 91d0980bfabeacb80269c88a097d078d9aadfcd2 Mon Sep 17 00:00:00 2001 From: Cyrill Gorcunov Date: Tue, 25 Aug 2020 18:05:33 +0300 Subject: [PATCH 17/34] travis: add ret Signed-off-by: Cyrill Gorcunov --- travis/test/ret-16.stderr | 1 + travis/test/ret-32.stderr | 1 + travis/test/ret-64.stderr | 1 + travis/test/ret.asm | 61 +++++++++++++++++++++++++++++++++++++++ travis/test/ret.bin.t | 1 + travis/test/ret.json | 39 +++++++++++++++++++++++++ 6 files changed, 104 insertions(+) create mode 100644 travis/test/ret-16.stderr create mode 100644 travis/test/ret-32.stderr create mode 100644 travis/test/ret-64.stderr create mode 100644 travis/test/ret.asm create mode 100644 travis/test/ret.bin.t create mode 100644 travis/test/ret.json diff --git a/travis/test/ret-16.stderr b/travis/test/ret-16.stderr new file mode 100644 index 00000000..1994fe9d --- /dev/null +++ b/travis/test/ret-16.stderr @@ -0,0 +1 @@ +./travis/test/ret.asm:18: error: expression syntax error \ No newline at end of file diff --git a/travis/test/ret-32.stderr b/travis/test/ret-32.stderr new file mode 100644 index 00000000..b971af0e --- /dev/null +++ b/travis/test/ret-32.stderr @@ -0,0 +1 @@ +./travis/test/ret.asm:37: error: expression syntax error \ No newline at end of file diff --git a/travis/test/ret-64.stderr b/travis/test/ret-64.stderr new file mode 100644 index 00000000..f06987b3 --- /dev/null +++ b/travis/test/ret-64.stderr @@ -0,0 +1 @@ +./travis/test/ret.asm:53: error: expression syntax error \ No newline at end of file diff --git a/travis/test/ret.asm b/travis/test/ret.asm new file mode 100644 index 00000000..0606257e --- /dev/null +++ b/travis/test/ret.asm @@ -0,0 +1,61 @@ +;; All the flavors of RET +%ifndef ERROR + %define ERROR 0 +%endif + +%ifdef TEST_BITS_16 + bits 16 + + ret + retn + retf + retw + retnw + retfw + retd + retnd + retfd +%if ERROR + retq + retnq + retfq +%endif +%endif + +%ifdef TEST_BITS_32 + bits 32 + + ret + retn + retf + retw + retnw + retfw + retd + retnd + retfd +%if ERROR + retq + retnq + retfq +%endif +%endif + +%ifdef TEST_BITS_64 + bits 64 + + ret + retn + retf ; Probably should have been RETFQ, but: legacy... + retw + retnw + retfw +%if ERROR + retd + retnd +%endif +%endif + retfd + retq + retnq + retfq diff --git a/travis/test/ret.bin.t b/travis/test/ret.bin.t new file mode 100644 index 00000000..246929c8 --- /dev/null +++ b/travis/test/ret.bin.t @@ -0,0 +1 @@ +ÃÃËÃÃËfÃfÃfËÃÃËfÃfÃfËÃÃËÃÃËfÃfÃfËËÃÃHË \ No newline at end of file diff --git a/travis/test/ret.json b/travis/test/ret.json new file mode 100644 index 00000000..ce1d2ca5 --- /dev/null +++ b/travis/test/ret.json @@ -0,0 +1,39 @@ +[ + { + "description": "Test all the flavors of RET", + "id": "ret", + "format": "bin", + "source": "ret.asm", + "option": "-Ox -DTEST_BITS_16 -DTEST_BITS_32 -DTEST_BITS_64", + "target": [ + { "output": "ret.bin" } + ] + }, + { + "description": "Test all the flavors of RET (err 16 bit)", + "ref": "ret", + "option": "-DERROR -DTEST_BITS_16 -o ret.bin", + "target": [ + { "stderr": "ret-16.stderr" } + ], + "error": "expected" + }, + { + "description": "Test all the flavors of RET (err 32 bit)", + "ref": "ret", + "option": "-DERROR -DTEST_BITS_32 -o ret.bin", + "target": [ + { "stderr": "ret-32.stderr" } + ], + "error": "expected" + }, + { + "description": "Test all the flavors of RET (err 64 bit)", + "ref": "ret", + "option": "-DERROR -DTEST_BITS_64 -o ret.bin", + "target": [ + { "stderr": "ret-64.stderr" } + ], + "error": "expected" + } +] From 40650a357a92d9edd858a72aabce06d491799df8 Mon Sep 17 00:00:00 2001 From: Cyrill Gorcunov Date: Tue, 25 Aug 2020 18:08:33 +0300 Subject: [PATCH 18/34] travis: add sreg Signed-off-by: Cyrill Gorcunov --- travis/test/sreg.asm | 65 ++++++++++++++++++++++++++++++++++++++++++ travis/test/sreg.bin.t | 1 + travis/test/sreg.json | 12 ++++++++ 3 files changed, 78 insertions(+) create mode 100644 travis/test/sreg.asm create mode 100644 travis/test/sreg.bin.t create mode 100644 travis/test/sreg.json diff --git a/travis/test/sreg.asm b/travis/test/sreg.asm new file mode 100644 index 00000000..11449a50 --- /dev/null +++ b/travis/test/sreg.asm @@ -0,0 +1,65 @@ + bits 64 + mov es,rax + mov ss,rax + mov ds,rax + mov fs,rax + mov gs,rax + mov es,eax + mov ss,eax + mov ds,eax + mov fs,eax + mov gs,eax + mov es,ax + mov ss,ax + mov ds,ax + mov fs,ax + mov gs,ax + mov es,[rsi] + mov ss,[rsi] + mov ds,[rsi] + mov fs,[rsi] + mov gs,[rsi] + mov es,word [rsi] + mov ss,word [rsi] + mov ds,word [rsi] + mov fs,word [rsi] + mov gs,word [rsi] + mov es,qword [rsi] + mov ss,qword [rsi] + mov ds,qword [rsi] + mov fs,qword [rsi] + mov gs,qword [rsi] + mov rax,es + mov rax,cs + mov rax,ss + mov rax,ds + mov rax,fs + mov rax,gs + mov eax,es + mov eax,ss + mov eax,ds + mov eax,fs + mov eax,fs + mov ax,es + mov ax,ss + mov ax,ds + mov ax,fs + mov ax,gs + mov [rdi],es + mov [rdi],cs + mov [rdi],ss + mov [rdi],ds + mov [rdi],fs + mov [rdi],gs + mov word [rdi],es + mov word [rdi],cs + mov word [rdi],ss + mov word [rdi],ds + mov word [rdi],fs + mov word [rdi],gs + mov qword [rdi],es + mov qword [rdi],cs + mov qword [rdi],ss + mov qword [rdi],ds + mov qword [rdi],fs + mov qword [rdi],gs diff --git a/travis/test/sreg.bin.t b/travis/test/sreg.bin.t new file mode 100644 index 00000000..70f8319c --- /dev/null +++ b/travis/test/sreg.bin.t @@ -0,0 +1 @@ +ŽÀŽÐŽØŽàŽèŽÀŽÐŽØŽàŽèŽÀŽÐŽØŽàŽèŽŽŽŽ&Ž.ŽŽŽŽ&Ž.HŽHŽHŽHŽ&HŽ.ŒÀŒÈŒÐŒØŒàŒèŒÀŒÐŒØŒàŒàfŒÀfŒÐfŒØfŒàfŒèŒŒŒŒŒ'Œ/ŒŒŒŒŒ'Œ/HŒHŒHŒHŒHŒ'HŒ/ \ No newline at end of file diff --git a/travis/test/sreg.json b/travis/test/sreg.json new file mode 100644 index 00000000..703d4826 --- /dev/null +++ b/travis/test/sreg.json @@ -0,0 +1,12 @@ +[ + { + "description": "Test segment registers in 64 bit mode", + "id": "sreg", + "format": "bin", + "source": "sreg.asm", + "option": "-Ox", + "target": [ + { "output": "sreg.bin" } + ] + } +] From 6691653710828d98d715d0333f6f88aa6f7ca74d Mon Sep 17 00:00:00 2001 From: Cyrill Gorcunov Date: Tue, 25 Aug 2020 18:12:09 +0300 Subject: [PATCH 19/34] travis: add v4 Signed-off-by: Cyrill Gorcunov --- travis/test/v4.asm | 16 ++++++++++++++++ travis/test/v4.bin.t | Bin 0 -> 42 bytes travis/test/v4.json | 21 +++++++++++++++++++++ travis/test/v4.stderr | 3 +++ 4 files changed, 40 insertions(+) create mode 100644 travis/test/v4.asm create mode 100644 travis/test/v4.bin.t create mode 100644 travis/test/v4.json create mode 100644 travis/test/v4.stderr diff --git a/travis/test/v4.asm b/travis/test/v4.asm new file mode 100644 index 00000000..bf88fd86 --- /dev/null +++ b/travis/test/v4.asm @@ -0,0 +1,16 @@ + bits 64 + + v4fmaddps zmm0,zmm1+3,[rax] + v4fnmaddps zmm2,zmm3,[rax] + v4fmaddss zmm4,zmm5+3,[rax] + v4fnmaddss zmm6,zmm7+3,[rax] + + v4dpwssds zmm8,zmm9,[rax] + v4dpwssd zmm10,zmm11+3,[rax] + v4dpwssd zmm10+0,zmm11+3,[rax] + +%ifdef ERROR + v4dpwssd zmm10+1,zmm11+3,[rax] + v4dpwssd zmm10,zmm11+4,[rax] + v4dpwssd zmm10,zmm11+7,[rax] +%endif diff --git a/travis/test/v4.bin.t b/travis/test/v4.bin.t new file mode 100644 index 0000000000000000000000000000000000000000..fc94d4072a9e98d03d71453afe5eeb62e909cb69 GIT binary patch literal 42 tcmYfLRPHg0A?Z`P$0~uOPvIQ16_P%=bF4N Date: Tue, 25 Aug 2020 18:59:06 +0300 Subject: [PATCH 20/34] travis: add br3392392 Signed-off-by: Cyrill Gorcunov --- travis/test/br3392392.asm | 15 +++++++++++++++ travis/test/br3392392.bin.t | Bin 0 -> 48 bytes travis/test/br3392392.json | 21 +++++++++++++++++++++ travis/test/br3392392.stderr | 1 + 4 files changed, 37 insertions(+) create mode 100644 travis/test/br3392392.asm create mode 100644 travis/test/br3392392.bin.t create mode 100644 travis/test/br3392392.json create mode 100644 travis/test/br3392392.stderr diff --git a/travis/test/br3392392.asm b/travis/test/br3392392.asm new file mode 100644 index 00000000..8a52da67 --- /dev/null +++ b/travis/test/br3392392.asm @@ -0,0 +1,15 @@ + bits 64 + vpaddd zmm0, zmm0, [rax]{1to16} + vpaddd zmm2{k3}, zmm0, zmm1 + vpaddd zmm2 {k3}, zmm0, zmm1 + vpaddd zmm0{k1}, zmm0, [rax]{1to16} + vmovdqa32 [rsi]{k1}, zmm1 + vmovdqa32 [rsi]{z}, zmm1 + vmovdqa32 [rsi]{k1}{z}, zmm1 + vmovdqa32 [rsi]{z}{k1}, zmm1 +%ifdef ERROR + vmovdqa32 [rsi]{z}{1to16}, zmm1 + vmovdqa32 [rsi]{z}{k1}{1to16}, zmm1 + vpaddd zmm0, zmm0, [rax]{k1} + vpaddd zmm0, zmm1, zmm2{1to16} +%endif diff --git a/travis/test/br3392392.bin.t b/travis/test/br3392392.bin.t new file mode 100644 index 0000000000000000000000000000000000000000..f0b476db63487f2a219fb7b165b99b5701ca0fca GIT binary patch literal 48 icmYfLSR3(=A?ahS_rHs9G7>D}S Date: Tue, 25 Aug 2020 19:01:17 +0300 Subject: [PATCH 21/34] travis: add br3392396 Signed-off-by: Cyrill Gorcunov --- travis/test/br3392396.asm | 5 +++++ travis/test/br3392396.bin.t | 1 + travis/test/br3392396.json | 12 ++++++++++++ 3 files changed, 18 insertions(+) create mode 100644 travis/test/br3392396.asm create mode 100644 travis/test/br3392396.bin.t create mode 100644 travis/test/br3392396.json diff --git a/travis/test/br3392396.asm b/travis/test/br3392396.asm new file mode 100644 index 00000000..beb71cf1 --- /dev/null +++ b/travis/test/br3392396.asm @@ -0,0 +1,5 @@ + bits 64 + vmovdqa32 [rdi],zmm16 + vmovdqa32 [rdi+64],zmm17 + vmovdqa32 [rdi+128],zmm18 + vmovdqa32 [rdi+192],zmm19 diff --git a/travis/test/br3392396.bin.t b/travis/test/br3392396.bin.t new file mode 100644 index 00000000..43c24a13 --- /dev/null +++ b/travis/test/br3392396.bin.t @@ -0,0 +1 @@ +bá}Hbá}HObá}HWbá}H_ \ No newline at end of file diff --git a/travis/test/br3392396.json b/travis/test/br3392396.json new file mode 100644 index 00000000..a06f4ca9 --- /dev/null +++ b/travis/test/br3392396.json @@ -0,0 +1,12 @@ +[ + { + "description": "Test br3392396", + "id": "br3392396", + "format": "bin", + "source": "br3392396.asm", + "option": "-Ox", + "target": [ + { "output": "br3392396.bin" } + ] + } +] From 09f819dc6f62b59ca7404b6745ed429c8ebcb1a5 Mon Sep 17 00:00:00 2001 From: Cyrill Gorcunov Date: Tue, 25 Aug 2020 19:02:55 +0300 Subject: [PATCH 22/34] travis: add br3392363 Signed-off-by: Cyrill Gorcunov --- travis/test/br3392363.asm | 5 +++++ travis/test/br3392363.bin.t | 1 + travis/test/br3392363.json | 12 ++++++++++++ 3 files changed, 18 insertions(+) create mode 100644 travis/test/br3392363.asm create mode 100644 travis/test/br3392363.bin.t create mode 100644 travis/test/br3392363.json diff --git a/travis/test/br3392363.asm b/travis/test/br3392363.asm new file mode 100644 index 00000000..e098bdd2 --- /dev/null +++ b/travis/test/br3392363.asm @@ -0,0 +1,5 @@ + bits 64 + vaddps zmm0 {k1}, zmm0, zmm0 + rep + vaddps zmm0 {k1}, zmm0, zmm0 + rep movsd diff --git a/travis/test/br3392363.bin.t b/travis/test/br3392363.bin.t new file mode 100644 index 00000000..ddee9535 --- /dev/null +++ b/travis/test/br3392363.bin.t @@ -0,0 +1 @@ +bñ|IXÀóbñ|IXÀó¥ \ No newline at end of file diff --git a/travis/test/br3392363.json b/travis/test/br3392363.json new file mode 100644 index 00000000..021bfbb5 --- /dev/null +++ b/travis/test/br3392363.json @@ -0,0 +1,12 @@ +[ + { + "description": "Test br3392363", + "id": "br3392363", + "format": "bin", + "source": "br3392363.asm", + "option": "-Ox", + "target": [ + { "output": "br3392363.bin" } + ] + } +] From 512c93dc42ebba2f1ebcb74f35f24e9792bd1ad6 Mon Sep 17 00:00:00 2001 From: Cyrill Gorcunov Date: Tue, 25 Aug 2020 19:11:52 +0300 Subject: [PATCH 23/34] travis: nasm-t -- add ability to specify error Signed-off-by: Cyrill Gorcunov --- travis/nasm-t.py | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/travis/nasm-t.py b/travis/nasm-t.py index 8907692e..02b145db 100755 --- a/travis/nasm-t.py +++ b/travis/nasm-t.py @@ -61,6 +61,10 @@ for cmd in ['new']: dest = 'ref', help = 'Test reference', required = False) + spp.add_argument('--error', + dest = 'error', + help = 'Set to "y" if test is supposed to fail', + required = False) spp.add_argument('--output', dest = 'output', default = 'y', help = 'Output (compiled) file name (or "y")', @@ -495,6 +499,8 @@ if args.cmd == 'new': acc.append("\t\t\"option\": \"{}\"".format(args.option)) if args.ref: acc.append("\t\t\"ref\": \"{}\"".format(args.ref)) + if args.error == 'y': + acc.append("\t\t\"error\": \"true\"") f.write(",\n".join(acc).encode("utf-8")) if args.output or args.stdout or args.stderr: acc = [] From 523b96dd6f0504f55508b4e54c147d310a85907a Mon Sep 17 00:00:00 2001 From: Cyrill Gorcunov Date: Tue, 25 Aug 2020 19:18:50 +0300 Subject: [PATCH 24/34] output/outcoff.c: zap timestamp when running tests When we're running tests we must not fail due to time stamp difference in a header. Lets zap it if test run is detected. Signed-off-by: Cyrill Gorcunov --- output/outcoff.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/output/outcoff.c b/output/outcoff.c index 2ecb97fc..6568ac23 100644 --- a/output/outcoff.c +++ b/output/outcoff.c @@ -40,6 +40,7 @@ #include "nctype.h" #include +#include "ver.h" #include "nasm.h" #include "nasmlib.h" @@ -935,7 +936,16 @@ static void coff_write(void) i = IMAGE_FILE_MACHINE_I386; fwriteint16_t(i, ofile); /* machine type */ fwriteint16_t(coff_nsects, ofile); /* number of sections */ - fwriteint32_t(time(NULL), ofile); /* time stamp */ + + /* + * When running tests we'are comparing binary output + * so time should be zapped. + */ + if (nasm_test_run()) + fwriteint32_t(0, ofile); /* time stamp */ + else + fwriteint32_t(time(NULL), ofile); /* time stamp */ + fwriteint32_t(sympos, ofile); fwriteint32_t(coff_nsyms + initsym, ofile); fwriteint16_t(0, ofile); /* no optional header */ From 4debfe8c8f1af75ea1b2b1280a738dc5a7f86710 Mon Sep 17 00:00:00 2001 From: Cyrill Gorcunov Date: Tue, 25 Aug 2020 19:19:33 +0300 Subject: [PATCH 25/34] travis: add br3392411 Signed-off-by: Cyrill Gorcunov --- travis/test/br3392411.asm | 22 ++++++++++++++++++++++ travis/test/br3392411.json | 12 ++++++++++++ travis/test/br3392411.out.t | Bin 0 -> 355 bytes 3 files changed, 34 insertions(+) create mode 100644 travis/test/br3392411.asm create mode 100644 travis/test/br3392411.json create mode 100644 travis/test/br3392411.out.t diff --git a/travis/test/br3392411.asm b/travis/test/br3392411.asm new file mode 100644 index 00000000..56b9706b --- /dev/null +++ b/travis/test/br3392411.asm @@ -0,0 +1,22 @@ +bits 64 +default rel + +%use smartalign + +section .text code align=32 + +align 32 + +nop +jz LDone + +%rep 10 + nop +%endrep + +align 16 +%rep 115 + nop +%endrep + +LDone: diff --git a/travis/test/br3392411.json b/travis/test/br3392411.json new file mode 100644 index 00000000..27264e6b --- /dev/null +++ b/travis/test/br3392411.json @@ -0,0 +1,12 @@ +[ + { + "description": "Description of a test", + "id": "br3392411", + "format": "win64", + "source": "br3392411.asm", + "option": "-Ox", + "target": [ + { "output": "br3392411.out" } + ] + } +] diff --git a/travis/test/br3392411.out.t b/travis/test/br3392411.out.t new file mode 100644 index 0000000000000000000000000000000000000000..6fa66e825f349e95999f8c9bce10bf61e3eceb7c GIT binary patch literal 355 zcmYdkV`Kn<^FYi2W-&16m84dbK-nN_G7#GUF-Q#zC@>@>OyF4f%PtU?Z?*sc literal 0 HcmV?d00001 From 312b7c667cdc7feded4b8e3006d0d17d45f848f3 Mon Sep 17 00:00:00 2001 From: Cyrill Gorcunov Date: Tue, 25 Aug 2020 19:21:17 +0300 Subject: [PATCH 26/34] travis: enable winalign test Signed-off-by: Cyrill Gorcunov --- travis/test/winalign.json | 1 - travis/test/winalign.obj.t | Bin 642 -> 642 bytes 2 files changed, 1 deletion(-) diff --git a/travis/test/winalign.json b/travis/test/winalign.json index 97ac1a83..6ada1c89 100644 --- a/travis/test/winalign.json +++ b/travis/test/winalign.json @@ -5,7 +5,6 @@ "format": "win64", "source": "winalign.asm", "error": "over", - "disable": "Unable to compare coff output", "option": "-Ox", "target": [ { "output": "winalign.obj" } diff --git a/travis/test/winalign.obj.t b/travis/test/winalign.obj.t index b47b6dc2563ac7c3fc01158189596f60085fb22a..f32ec00abbe4c518516aeeb382b728ebb28a7223 100644 GIT binary patch delta 40 tcmZo-ZDQp}X=7smfsGthj6!<)B}Iv4nZ^1gsl_Gw<(YYjlczAg0|3cg3?={o delta 40 vcmZo-ZDQp}X=7vP{_hgMk)w)HsH7;dEVEd@B(=CizdSQ9F(-5K6vlS|6U`3G From 2cc71a59b1e627e99ede6076746fde84cc5c7b39 Mon Sep 17 00:00:00 2001 From: Cyrill Gorcunov Date: Tue, 25 Aug 2020 19:42:29 +0300 Subject: [PATCH 27/34] travis: add lwp Signed-off-by: Cyrill Gorcunov --- travis/test/lwp.asm | 213 ++++++++++++++++++++++++++++++++++++++++++ travis/test/lwp.bin.t | Bin 0 -> 1810 bytes travis/test/lwp.json | 12 +++ 3 files changed, 225 insertions(+) create mode 100644 travis/test/lwp.asm create mode 100644 travis/test/lwp.bin.t create mode 100644 travis/test/lwp.json diff --git a/travis/test/lwp.asm b/travis/test/lwp.asm new file mode 100644 index 00000000..4b2bdc9b --- /dev/null +++ b/travis/test/lwp.asm @@ -0,0 +1,213 @@ +; LWP testcases from 2010/03/22 binutils change: no more 16-bit variants +;------------------------------------------------------------------------ + +%define testcase3(x) x +%define testcase3(x,y) y,x +%define testcase3(x,y,z) z,y,x + +%macro testcase 3.nolist ; uncomment one of the two, and compare the -f bin and -l output between them +%ifdef BIN + db %1 +%endif +%ifdef SRC + %2 testcase3(%3) +%endif +%endmacro + +bits 32 + +testcase { 0x8f, 0xe9, 0x78, 0x12, 0xc0 }, { llwpcb }, { eax } +testcase { 0x8f, 0xe9, 0x78, 0x12, 0xc1 }, { llwpcb }, { ecx } +testcase { 0x8f, 0xe9, 0x78, 0x12, 0xc2 }, { llwpcb }, { edx } +testcase { 0x8f, 0xe9, 0x78, 0x12, 0xc3 }, { llwpcb }, { ebx } +testcase { 0x8f, 0xe9, 0x78, 0x12, 0xc4 }, { llwpcb }, { esp } +testcase { 0x8f, 0xe9, 0x78, 0x12, 0xc5 }, { llwpcb }, { ebp } +testcase { 0x8f, 0xe9, 0x78, 0x12, 0xc6 }, { llwpcb }, { esi } +testcase { 0x8f, 0xe9, 0x78, 0x12, 0xc7 }, { llwpcb }, { edi } +testcase { 0x8f, 0xe9, 0x78, 0x12, 0xcf }, { slwpcb }, { edi } +testcase { 0x8f, 0xe9, 0x78, 0x12, 0xce }, { slwpcb }, { esi } +testcase { 0x8f, 0xe9, 0x78, 0x12, 0xcd }, { slwpcb }, { ebp } +testcase { 0x8f, 0xe9, 0x78, 0x12, 0xcc }, { slwpcb }, { esp } +testcase { 0x8f, 0xe9, 0x78, 0x12, 0xcb }, { slwpcb }, { ebx } +testcase { 0x8f, 0xe9, 0x78, 0x12, 0xca }, { slwpcb }, { edx } +testcase { 0x8f, 0xe9, 0x78, 0x12, 0xc9 }, { slwpcb }, { ecx } +testcase { 0x8f, 0xe9, 0x78, 0x12, 0xc8 }, { slwpcb }, { eax } +testcase { 0x8f, 0xea, 0x78, 0x12, 0xc7, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,edi,eax } +testcase { 0x8f, 0xea, 0x70, 0x12, 0xc6, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,esi,ecx } +testcase { 0x8f, 0xea, 0x68, 0x12, 0xc5, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,ebp,edx } +testcase { 0x8f, 0xea, 0x60, 0x12, 0xc4, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,esp,ebx } +testcase { 0x8f, 0xea, 0x58, 0x12, 0xc3, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,ebx,esp } +testcase { 0x8f, 0xea, 0x50, 0x12, 0xc2, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,edx,ebp } +testcase { 0x8f, 0xea, 0x48, 0x12, 0xc1, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,ecx,esi } +testcase { 0x8f, 0xea, 0x40, 0x12, 0xc0, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,eax,edi } +testcase { 0x8f, 0xea, 0x78, 0x12, 0xcf, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,edi,eax } +testcase { 0x8f, 0xea, 0x70, 0x12, 0xce, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,esi,ecx } +testcase { 0x8f, 0xea, 0x68, 0x12, 0xcd, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,ebp,edx } +testcase { 0x8f, 0xea, 0x60, 0x12, 0xcc, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,esp,ebx } +testcase { 0x8f, 0xea, 0x58, 0x12, 0xcb, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,ebx,esp } +testcase { 0x8f, 0xea, 0x50, 0x12, 0xca, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,edx,ebp } +testcase { 0x8f, 0xea, 0x48, 0x12, 0xc9, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,ecx,esi } +testcase { 0x8f, 0xea, 0x40, 0x12, 0xc8, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,eax,edi } +testcase { 0x8f, 0xea, 0x78, 0x12, 0x07, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[edi],eax } +testcase { 0x8f, 0xea, 0x70, 0x12, 0x06, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[esi],ecx } +testcase { 0x8f, 0xea, 0x68, 0x12, 0x45, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[ebp],edx } +testcase { 0x8f, 0xea, 0x60, 0x12, 0x04, 0x24, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[esp],ebx } +testcase { 0x8f, 0xea, 0x58, 0x12, 0x03, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[ebx],esp } +testcase { 0x8f, 0xea, 0x50, 0x12, 0x02, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[edx],ebp } +testcase { 0x8f, 0xea, 0x48, 0x12, 0x01, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[ecx],esi } +testcase { 0x8f, 0xea, 0x40, 0x12, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[eax],edi } +testcase { 0x8f, 0xea, 0x78, 0x12, 0x0f, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[edi],eax } +testcase { 0x8f, 0xea, 0x70, 0x12, 0x0e, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[esi],ecx } +testcase { 0x8f, 0xea, 0x68, 0x12, 0x4d, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[ebp],edx } +testcase { 0x8f, 0xea, 0x60, 0x12, 0x0c, 0x24, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[esp],ebx } +testcase { 0x8f, 0xea, 0x58, 0x12, 0x0b, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[ebx],esp } +testcase { 0x8f, 0xea, 0x50, 0x12, 0x0a, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[edx],ebp } +testcase { 0x8f, 0xea, 0x48, 0x12, 0x09, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[ecx],esi } +testcase { 0x8f, 0xea, 0x40, 0x12, 0x08, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[eax],edi } +testcase { 0x8f, 0xea, 0x78, 0x12, 0x87, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[0xcafe+edi],eax } +testcase { 0x8f, 0xea, 0x70, 0x12, 0x86, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[0xcafe+esi],ecx } +testcase { 0x8f, 0xea, 0x68, 0x12, 0x85, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[0xcafe+ebp],edx } +testcase { 0x8f, 0xea, 0x60, 0x12, 0x84, 0x24, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[0xcafe+esp],ebx } +testcase { 0x8f, 0xea, 0x58, 0x12, 0x83, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[0xcafe+ebx],esp } +testcase { 0x8f, 0xea, 0x50, 0x12, 0x82, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[0xcafe+edx],ebp } +testcase { 0x8f, 0xea, 0x48, 0x12, 0x81, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[0xcafe+ecx],esi } +testcase { 0x8f, 0xea, 0x40, 0x12, 0x80, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[0xcafe+eax],edi } +testcase { 0x8f, 0xea, 0x78, 0x12, 0x8f, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[0xcafe+edi],eax } +testcase { 0x8f, 0xea, 0x70, 0x12, 0x8e, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[0xcafe+esi],ecx } +testcase { 0x8f, 0xea, 0x68, 0x12, 0x8d, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[0xcafe+ebp],edx } +testcase { 0x8f, 0xea, 0x60, 0x12, 0x8c, 0x24, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[0xcafe+esp],ebx } +testcase { 0x8f, 0xea, 0x58, 0x12, 0x8b, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[0xcafe+ebx],esp } +testcase { 0x8f, 0xea, 0x50, 0x12, 0x8a, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[0xcafe+edx],ebp } +testcase { 0x8f, 0xea, 0x48, 0x12, 0x89, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[0xcafe+ecx],esi } +testcase { 0x8f, 0xea, 0x40, 0x12, 0x88, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[0xcafe+eax],edi } + +bits 64 + +testcase { 0x8f, 0xe9, 0x78, 0x12, 0xc0 }, { llwpcb }, { eax } +testcase { 0x8f, 0xe9, 0x78, 0x12, 0xc1 }, { llwpcb }, { ecx } +testcase { 0x8f, 0xe9, 0x78, 0x12, 0xc2 }, { llwpcb }, { edx } +testcase { 0x8f, 0xe9, 0x78, 0x12, 0xc3 }, { llwpcb }, { ebx } +testcase { 0x8f, 0xe9, 0x78, 0x12, 0xc4 }, { llwpcb }, { esp } +testcase { 0x8f, 0xe9, 0x78, 0x12, 0xc5 }, { llwpcb }, { ebp } +testcase { 0x8f, 0xe9, 0x78, 0x12, 0xc6 }, { llwpcb }, { esi } +testcase { 0x8f, 0xe9, 0x78, 0x12, 0xc7 }, { llwpcb }, { edi } +testcase { 0x8f, 0xc9, 0x78, 0x12, 0xc0 }, { llwpcb }, { r8d } +testcase { 0x8f, 0xc9, 0x78, 0x12, 0xc1 }, { llwpcb }, { r9d } +testcase { 0x8f, 0xc9, 0x78, 0x12, 0xc2 }, { llwpcb }, { r10d } +testcase { 0x8f, 0xc9, 0x78, 0x12, 0xc3 }, { llwpcb }, { r11d } +testcase { 0x8f, 0xc9, 0x78, 0x12, 0xc4 }, { llwpcb }, { r12d } +testcase { 0x8f, 0xc9, 0x78, 0x12, 0xc5 }, { llwpcb }, { r13d } +testcase { 0x8f, 0xc9, 0x78, 0x12, 0xc6 }, { llwpcb }, { r14d } +testcase { 0x8f, 0xc9, 0x78, 0x12, 0xc7 }, { llwpcb }, { r15d } +testcase { 0x8f, 0xc9, 0x78, 0x12, 0xcf }, { slwpcb }, { r15d } +testcase { 0x8f, 0xc9, 0x78, 0x12, 0xce }, { slwpcb }, { r14d } +testcase { 0x8f, 0xc9, 0x78, 0x12, 0xcd }, { slwpcb }, { r13d } +testcase { 0x8f, 0xc9, 0x78, 0x12, 0xcc }, { slwpcb }, { r12d } +testcase { 0x8f, 0xc9, 0x78, 0x12, 0xcb }, { slwpcb }, { r11d } +testcase { 0x8f, 0xc9, 0x78, 0x12, 0xca }, { slwpcb }, { r10d } +testcase { 0x8f, 0xc9, 0x78, 0x12, 0xc9 }, { slwpcb }, { r9d } +testcase { 0x8f, 0xc9, 0x78, 0x12, 0xc8 }, { slwpcb }, { r8d } +testcase { 0x8f, 0xe9, 0x78, 0x12, 0xcf }, { slwpcb }, { edi } +testcase { 0x8f, 0xe9, 0x78, 0x12, 0xce }, { slwpcb }, { esi } +testcase { 0x8f, 0xe9, 0x78, 0x12, 0xcd }, { slwpcb }, { ebp } +testcase { 0x8f, 0xe9, 0x78, 0x12, 0xcc }, { slwpcb }, { esp } +testcase { 0x8f, 0xe9, 0x78, 0x12, 0xcb }, { slwpcb }, { ebx } +testcase { 0x8f, 0xe9, 0x78, 0x12, 0xca }, { slwpcb }, { edx } +testcase { 0x8f, 0xe9, 0x78, 0x12, 0xc9 }, { slwpcb }, { ecx } +testcase { 0x8f, 0xe9, 0x78, 0x12, 0xc8 }, { slwpcb }, { eax } +testcase { 0x8f, 0xca, 0x78, 0x12, 0xc7, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,r15d,eax } +testcase { 0x8f, 0xca, 0x70, 0x12, 0xc6, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,r14d,ecx } +testcase { 0x8f, 0xca, 0x68, 0x12, 0xc5, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,r13d,edx } +testcase { 0x8f, 0xca, 0x60, 0x12, 0xc4, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,r12d,ebx } +testcase { 0x8f, 0xca, 0x58, 0x12, 0xc3, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,r11d,esp } +testcase { 0x8f, 0xca, 0x50, 0x12, 0xc2, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,r10d,ebp } +testcase { 0x8f, 0xca, 0x48, 0x12, 0xc1, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,r9d,esi } +testcase { 0x8f, 0xca, 0x40, 0x12, 0xc0, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,r8d,edi } +testcase { 0x8f, 0xea, 0x38, 0x12, 0xc7, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,edi,r8d } +testcase { 0x8f, 0xea, 0x30, 0x12, 0xc6, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,esi,r9d } +testcase { 0x8f, 0xea, 0x28, 0x12, 0xc5, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,ebp,r10d } +testcase { 0x8f, 0xea, 0x20, 0x12, 0xc4, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,esp,r11d } +testcase { 0x8f, 0xea, 0x18, 0x12, 0xc3, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,ebx,r12d } +testcase { 0x8f, 0xea, 0x10, 0x12, 0xc2, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,edx,r13d } +testcase { 0x8f, 0xea, 0x08, 0x12, 0xc1, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,ecx,r14d } +testcase { 0x8f, 0xea, 0x00, 0x12, 0xc0, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,eax,r15d } +testcase { 0x8f, 0xca, 0x78, 0x12, 0xcf, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,r15d,eax } +testcase { 0x8f, 0xca, 0x70, 0x12, 0xce, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,r14d,ecx } +testcase { 0x8f, 0xca, 0x68, 0x12, 0xcd, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,r13d,edx } +testcase { 0x8f, 0xca, 0x60, 0x12, 0xcc, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,r12d,ebx } +testcase { 0x8f, 0xca, 0x58, 0x12, 0xcb, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,r11d,esp } +testcase { 0x8f, 0xca, 0x50, 0x12, 0xca, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,r10d,ebp } +testcase { 0x8f, 0xca, 0x48, 0x12, 0xc9, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,r9d,esi } +testcase { 0x8f, 0xca, 0x40, 0x12, 0xc8, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,r8d,edi } +testcase { 0x8f, 0xea, 0x38, 0x12, 0xcf, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,edi,r8d } +testcase { 0x8f, 0xea, 0x30, 0x12, 0xce, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,esi,r9d } +testcase { 0x8f, 0xea, 0x28, 0x12, 0xcd, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,ebp,r10d } +testcase { 0x8f, 0xea, 0x20, 0x12, 0xcc, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,esp,r11d } +testcase { 0x8f, 0xea, 0x18, 0x12, 0xcb, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,ebx,r12d } +testcase { 0x8f, 0xea, 0x10, 0x12, 0xca, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,edx,r13d } +testcase { 0x8f, 0xea, 0x08, 0x12, 0xc9, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,ecx,r14d } +testcase { 0x8f, 0xea, 0x00, 0x12, 0xc8, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,eax,r15d } +testcase { 0x67, 0x8f, 0xca, 0x78, 0x12, 0x07, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[r15d],eax } +testcase { 0x67, 0x8f, 0xca, 0x70, 0x12, 0x06, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[r14d],ecx } +testcase { 0x67, 0x8f, 0xca, 0x68, 0x12, 0x45, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[r13d],edx } +testcase { 0x67, 0x8f, 0xca, 0x60, 0x12, 0x04, 0x24, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[r12d],ebx } +testcase { 0x67, 0x8f, 0xca, 0x58, 0x12, 0x03, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[r11d],esp } +testcase { 0x67, 0x8f, 0xca, 0x50, 0x12, 0x02, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[r10d],ebp } +testcase { 0x67, 0x8f, 0xca, 0x48, 0x12, 0x01, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[r9d],esi } +testcase { 0x67, 0x8f, 0xca, 0x40, 0x12, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[r8d],edi } +testcase { 0x67, 0x8f, 0xea, 0x38, 0x12, 0x07, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[edi],r8d } +testcase { 0x67, 0x8f, 0xea, 0x30, 0x12, 0x06, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[esi],r9d } +testcase { 0x67, 0x8f, 0xea, 0x28, 0x12, 0x45, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[ebp],r10d } +testcase { 0x67, 0x8f, 0xea, 0x20, 0x12, 0x04, 0x24, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[esp],r11d } +testcase { 0x67, 0x8f, 0xea, 0x18, 0x12, 0x03, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[ebx],r12d } +testcase { 0x67, 0x8f, 0xea, 0x10, 0x12, 0x02, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[edx],r13d } +testcase { 0x67, 0x8f, 0xea, 0x08, 0x12, 0x01, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[ecx],r14d } +testcase { 0x67, 0x8f, 0xea, 0x00, 0x12, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[eax],r15d } +testcase { 0x67, 0x8f, 0xca, 0x78, 0x12, 0x0f, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[r15d],eax } +testcase { 0x67, 0x8f, 0xca, 0x70, 0x12, 0x0e, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[r14d],ecx } +testcase { 0x67, 0x8f, 0xca, 0x68, 0x12, 0x4d, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[r13d],edx } +testcase { 0x67, 0x8f, 0xca, 0x60, 0x12, 0x0c, 0x24, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[r12d],ebx } +testcase { 0x67, 0x8f, 0xca, 0x58, 0x12, 0x0b, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[r11d],esp } +testcase { 0x67, 0x8f, 0xca, 0x50, 0x12, 0x0a, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[r10d],ebp } +testcase { 0x67, 0x8f, 0xca, 0x48, 0x12, 0x09, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[r9d],esi } +testcase { 0x67, 0x8f, 0xca, 0x40, 0x12, 0x08, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[r8d],edi } +testcase { 0x67, 0x8f, 0xea, 0x38, 0x12, 0x0f, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[edi],r8d } +testcase { 0x67, 0x8f, 0xea, 0x30, 0x12, 0x0e, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[esi],r9d } +testcase { 0x67, 0x8f, 0xea, 0x28, 0x12, 0x4d, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[ebp],r10d } +testcase { 0x67, 0x8f, 0xea, 0x20, 0x12, 0x0c, 0x24, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[esp],r11d } +testcase { 0x67, 0x8f, 0xea, 0x18, 0x12, 0x0b, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[ebx],r12d } +testcase { 0x67, 0x8f, 0xea, 0x10, 0x12, 0x0a, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[edx],r13d } +testcase { 0x67, 0x8f, 0xea, 0x08, 0x12, 0x09, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[ecx],r14d } +testcase { 0x67, 0x8f, 0xea, 0x00, 0x12, 0x08, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[eax],r15d } +testcase { 0x67, 0x8f, 0xca, 0x78, 0x12, 0x87, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[0xcafe+r15d],eax } +testcase { 0x67, 0x8f, 0xca, 0x70, 0x12, 0x86, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[0xcafe+r14d],ecx } +testcase { 0x67, 0x8f, 0xca, 0x68, 0x12, 0x85, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[0xcafe+r13d],edx } +testcase { 0x67, 0x8f, 0xca, 0x60, 0x12, 0x84, 0x24, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[0xcafe+r12d],ebx } +testcase { 0x67, 0x8f, 0xca, 0x58, 0x12, 0x83, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[0xcafe+r11d],esp } +testcase { 0x67, 0x8f, 0xca, 0x50, 0x12, 0x82, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[0xcafe+r10d],ebp } +testcase { 0x67, 0x8f, 0xca, 0x48, 0x12, 0x81, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[0xcafe+r9d],esi } +testcase { 0x67, 0x8f, 0xca, 0x40, 0x12, 0x80, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[0xcafe+r8d],edi } +testcase { 0x67, 0x8f, 0xea, 0x38, 0x12, 0x87, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[0xcafe+edi],r8d } +testcase { 0x67, 0x8f, 0xea, 0x30, 0x12, 0x86, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[0xcafe+esi],r9d } +testcase { 0x67, 0x8f, 0xea, 0x28, 0x12, 0x85, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[0xcafe+ebp],r10d } +testcase { 0x67, 0x8f, 0xea, 0x20, 0x12, 0x84, 0x24, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[0xcafe+esp],r11d } +testcase { 0x67, 0x8f, 0xea, 0x18, 0x12, 0x83, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[0xcafe+ebx],r12d } +testcase { 0x67, 0x8f, 0xea, 0x10, 0x12, 0x82, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[0xcafe+edx],r13d } +testcase { 0x67, 0x8f, 0xea, 0x08, 0x12, 0x81, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[0xcafe+ecx],r14d } +testcase { 0x67, 0x8f, 0xea, 0x00, 0x12, 0x80, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[0xcafe+eax],r15d } +testcase { 0x67, 0x8f, 0xca, 0x78, 0x12, 0x8f, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[0xcafe+r15d],eax } +testcase { 0x67, 0x8f, 0xca, 0x70, 0x12, 0x8e, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[0xcafe+r14d],ecx } +testcase { 0x67, 0x8f, 0xca, 0x68, 0x12, 0x8d, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[0xcafe+r13d],edx } +testcase { 0x67, 0x8f, 0xca, 0x60, 0x12, 0x8c, 0x24, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[0xcafe+r12d],ebx } +testcase { 0x67, 0x8f, 0xca, 0x58, 0x12, 0x8b, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[0xcafe+r11d],esp } +testcase { 0x67, 0x8f, 0xca, 0x50, 0x12, 0x8a, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[0xcafe+r10d],ebp } +testcase { 0x67, 0x8f, 0xca, 0x48, 0x12, 0x89, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[0xcafe+r9d],esi } +testcase { 0x67, 0x8f, 0xca, 0x40, 0x12, 0x88, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[0xcafe+r8d],edi } +testcase { 0x67, 0x8f, 0xea, 0x38, 0x12, 0x8f, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[0xcafe+edi],r8d } +testcase { 0x67, 0x8f, 0xea, 0x30, 0x12, 0x8e, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[0xcafe+esi],r9d } +testcase { 0x67, 0x8f, 0xea, 0x28, 0x12, 0x8d, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[0xcafe+ebp],r10d } +testcase { 0x67, 0x8f, 0xea, 0x20, 0x12, 0x8c, 0x24, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[0xcafe+esp],r11d } +testcase { 0x67, 0x8f, 0xea, 0x18, 0x12, 0x8b, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[0xcafe+ebx],r12d } +testcase { 0x67, 0x8f, 0xea, 0x10, 0x12, 0x8a, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[0xcafe+edx],r13d } +testcase { 0x67, 0x8f, 0xea, 0x08, 0x12, 0x89, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[0xcafe+ecx],r14d } +testcase { 0x67, 0x8f, 0xea, 0x00, 0x12, 0x88, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[0xcafe+eax],r15d } diff --git a/travis/test/lwp.bin.t b/travis/test/lwp.bin.t new file mode 100644 index 0000000000000000000000000000000000000000..13110779ac07db374b2819d6ab40c91962e8fabd GIT binary patch literal 1810 zcma)+xsKaF5Jc$%HhsVrI#S4B1BMJ7Fl1tYi2+6iLuSj6Aw%D{&0kubD~*o*j@3sP zu2xU8$Jr)@SE6<}!dBIA+tbwmnX$}S7A#Aa70a6Cn&pP&$Z}xWv+P(L%a&y`obcuT z?JF8i9jyggS_w3?6sTz-P|;kVq?tfLR|0sSKu1S`mJR|9?FDMu2~^|+O42{rWaLa3$(0u|jCDCwR+LH^r4y_8QndLhu#oAIRQ<4MotVMR{`N_rwt zP%O~X*S{|Ef7;O(GcA2K)6l02b2WW5Q_%-ACA~LO&^t3d4Q4v}W2U9wW*YkS--~|Q zql$i*De1eJg1(Ig|N1+nXv^P&%vk0u3zj9zie=4m&2qzXWI3?xS#~UrWy`YR$lWQG zPE+YLl}=OXG?h+M=`@v2Q|ZQ3=9=zI)17L%6HWJ2(>>92$C~cQryKW?bmKmfZrn%G zjr&NtaUV%H?jz~OeI(tuk56~5Ey=VcskS81mQ1xJ6KzSXEs5lu%K;ZU*97Ey0@9)Y zwJAVf6_D==$d?7=+j2Raay{{sN%Qbo>Z=D#eD{D;DIaJe?E}S9KTst7!`Z%oAm2cc zRuI^bbP!n6xr89!LXfW^$oCLu=Td1!vzJ03mT4B=e8wqnT-itYHI?Q1aksAwLO8G*r340wkU9s zO$uHgYzka3DsaK7z=g8{Thq8JaKW&^1=^7cd?9|} PxMX-1+myjYwq^eS2<6eg literal 0 HcmV?d00001 diff --git a/travis/test/lwp.json b/travis/test/lwp.json new file mode 100644 index 00000000..8a0dd562 --- /dev/null +++ b/travis/test/lwp.json @@ -0,0 +1,12 @@ +[ + { + "description": "Test LWP instructions", + "id": "lwp", + "format": "bin", + "source": "lwp.asm", + "option": "-Ox -DSRC", + "target": [ + { "output": "lwp.bin" } + ] + } +] From 0b7244fcd6ec913e3cd5df03a07ba39e326e15ce Mon Sep 17 00:00:00 2001 From: Cyrill Gorcunov Date: Tue, 25 Aug 2020 19:53:26 +0300 Subject: [PATCH 28/34] trevis: unify tmap descriptor Signed-off-by: Cyrill Gorcunov --- travis/test/tmap.json | 22 ++++++++++++---------- travis/test/{tmap.o.stderr => tmap.stderr} | 0 2 files changed, 12 insertions(+), 10 deletions(-) rename travis/test/{tmap.o.stderr => tmap.stderr} (100%) diff --git a/travis/test/tmap.json b/travis/test/tmap.json index 3978d998..a3b2829d 100644 --- a/travis/test/tmap.json +++ b/travis/test/tmap.json @@ -1,10 +1,12 @@ -{ - "description": "Test abuse the section flags which breaks NASM 0.98.37", - "format": "elf", - "source": "tmap.asm", - "option": "-DLINUX", - "target": [ - { "output": "tmap.o" }, - { "stderr": "tmap.o.stderr" } - ] -} +[ + { + "description": "Test abuse the section flags which breaks NASM 0.98.37", + "format": "elf", + "source": "tmap.asm", + "option": "-Ox -DLINUX", + "target": [ + { "output": "tmap.o" }, + { "stderr": "tmap.stderr" } + ] + } +] diff --git a/travis/test/tmap.o.stderr b/travis/test/tmap.stderr similarity index 100% rename from travis/test/tmap.o.stderr rename to travis/test/tmap.stderr From 2b4886afdd60106bac617408201e3d5160181dc6 Mon Sep 17 00:00:00 2001 From: "H. Peter Anvin (Intel)" Date: Thu, 27 Aug 2020 11:43:08 -0700 Subject: [PATCH 29/34] BR 3392715: fix %ifid with $ and $$ %ifid $ and %ifid $$ has traditionally been false, revert to that behavior. Reported-by: Mike Hommey Signed-off-by: H. Peter Anvin (Intel) --- asm/preproc.c | 6 ++---- doc/changes.src | 5 +++++ travis/test/ifid.asm | 19 +++++++++++++++++++ travis/test/ifid.bin.t | 3 +++ travis/test/ifid.json | 11 +++++++++++ 5 files changed, 40 insertions(+), 4 deletions(-) create mode 100644 travis/test/ifid.asm create mode 100644 travis/test/ifid.bin.t create mode 100644 travis/test/ifid.json diff --git a/asm/preproc.c b/asm/preproc.c index 3fa4e281..a03e6aba 100644 --- a/asm/preproc.c +++ b/asm/preproc.c @@ -1600,8 +1600,7 @@ static Token *tokenize(const char *line) /* type = -1; */ } } else if (p[0] == '$' && p[1] == '$') { - /* TOKEN_BASE - treat as TOK_ID for pasting purposes */ - type = TOK_ID; + type = TOK_OTHER; /* TOKEN_BASE */ p += 2; } else if (nasm_isnumstart(*p)) { bool is_hex = false; @@ -1667,8 +1666,7 @@ static Token *tokenize(const char *line) p--; /* Point to first character beyond number */ if (p == line+1 && *line == '$') { - /* TOKEN_HERE - treat as TOK_ID for pasting purposes */ - type = TOK_ID; + type = TOK_OTHER; /* TOKEN_HERE */ } else { if (has_e && !is_hex) { /* 1e13 is floating-point, but 1e13h is not */ diff --git a/doc/changes.src b/doc/changes.src index f6642168..9b0e02d0 100644 --- a/doc/changes.src +++ b/doc/changes.src @@ -7,6 +7,11 @@ The NASM 2 series supports x86-64, and is the production version of NASM since 2007. +\S{cl-2.15.05} Version 2.15.05 + +\b Correct \c{%ifid $} and \c{%ifid $$} being treated as true. See +\k{iftyp}. + \S{cl-2.15.04} Version 2.15.04 \b More sensible handling of the case where one single-line macro diff --git a/travis/test/ifid.asm b/travis/test/ifid.asm new file mode 100644 index 00000000..ffe03d27 --- /dev/null +++ b/travis/test/ifid.asm @@ -0,0 +1,19 @@ +; BR 3392715: Test proper operation of %ifid with $ and $$ +; This produces a human-readable file when compiled with -f bin + +%define LF 10 + +%macro ifid 2 + %ifid %1 + %define %%is 'true' + %else + %define %%is 'false' + %endif + %defstr %%what %1 + %defstr %%should %2 + db '%ifid ', %%what, ' = ', %%is, ' (expect ', %%should, ')', LF +%endmacro + + ifid hello, true + ifid $, false + ifid $$, false diff --git a/travis/test/ifid.bin.t b/travis/test/ifid.bin.t new file mode 100644 index 00000000..ca86592d --- /dev/null +++ b/travis/test/ifid.bin.t @@ -0,0 +1,3 @@ +%ifid hello = true (expect true) +%ifid $ = false (expect false) +%ifid $$ = false (expect false) diff --git a/travis/test/ifid.json b/travis/test/ifid.json new file mode 100644 index 00000000..cf1a3854 --- /dev/null +++ b/travis/test/ifid.json @@ -0,0 +1,11 @@ +[ + { + "description": "BR 3392715: Test proper operation of %ifid with $ and $$", + "id": "ifid", + "format": "bin", + "source": "ifid.asm", + "target": [ + { "output": "ifid.bin" } + ] + } +] From 48327377bd81d49a6d10ec2ee0c91bb7b64e39e9 Mon Sep 17 00:00:00 2001 From: "H. Peter Anvin (Intel)" Date: Thu, 27 Aug 2020 11:45:07 -0700 Subject: [PATCH 30/34] NASM 2.15.05rc1 --- version | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/version b/version index 0712419d..812cda4c 100644 --- a/version +++ b/version @@ -1 +1 @@ -2.15.04 +2.15.05rc1 From 7497737aa2ee4cd2e4a8f2f6bafde7719980b488 Mon Sep 17 00:00:00 2001 From: "H. Peter Anvin (Intel)" Date: Thu, 27 Aug 2020 12:22:09 -0700 Subject: [PATCH 31/34] travis: fix "warnstack" test The "warnstack" test is supposed to test the warning stack, but the [warning] directive is never seen in preprocess-only mode, so run it in -f bin mode. Signed-off-by: H. Peter Anvin (Intel) --- travis/test/warnstack.bin.t | 0 travis/test/warnstack.json | 11 ++++++----- travis/test/warnstack.stderr | 5 ++--- travis/test/warnstack.stdout | 9 --------- 4 files changed, 8 insertions(+), 17 deletions(-) create mode 100644 travis/test/warnstack.bin.t delete mode 100644 travis/test/warnstack.stdout diff --git a/travis/test/warnstack.bin.t b/travis/test/warnstack.bin.t new file mode 100644 index 00000000..e69de29b diff --git a/travis/test/warnstack.json b/travis/test/warnstack.json index 18f27fc6..c462b75b 100644 --- a/travis/test/warnstack.json +++ b/travis/test/warnstack.json @@ -1,11 +1,12 @@ [ { "description": "Test warning stack", - "id": "warnstack", - "source": "warnstack.asm", - "option": "-E", - "target": [ - { "stdout": "warnstack.stdout" }, + "id": "warnstack", + "format": "bin", + "source": "warnstack.asm", + "option": "-Ox", + "target": [ + { "output": "warnstack.bin" }, { "stderr": "warnstack.stderr" } ] } diff --git a/travis/test/warnstack.stderr b/travis/test/warnstack.stderr index 91fbf65f..76f81a8f 100644 --- a/travis/test/warnstack.stderr +++ b/travis/test/warnstack.stderr @@ -1,5 +1,4 @@ ./travis/test/warnstack.asm:1: warning: Good warning [-w+user] -./travis/test/warnstack.asm:4: warning: Bad warning [-w+user] ./travis/test/warnstack.asm:6: warning: Good warning [-w+user] -./travis/test/warnstack.asm:8: warning: Bad warning [-w+user] -./travis/test/warnstack.asm:10: warning: Good warning [-w+user] \ No newline at end of file +./travis/test/warnstack.asm:9: warning: warning stack empty [-w+warn-stack-empty] +./travis/test/warnstack.asm:10: warning: Good warning [-w+user] diff --git a/travis/test/warnstack.stdout b/travis/test/warnstack.stdout deleted file mode 100644 index 51db543c..00000000 --- a/travis/test/warnstack.stdout +++ /dev/null @@ -1,9 +0,0 @@ -%line 2+1 ./travis/test/warnstack.asm - [warning push] - [warning -user] - - [warning pop] - - [warning -user] - - [warning pop] \ No newline at end of file From bf79786e894ad16519e5374291205ebe71da07b8 Mon Sep 17 00:00:00 2001 From: "H. Peter Anvin (Intel)" Date: Thu, 27 Aug 2020 13:01:57 -0700 Subject: [PATCH 32/34] Add option to create reproducible output We need the ability to produce consistent output for our own tests, anyway, so make this a user-accessible feature. This was requested in BR 3392635. This obsoletes the NASM_TEST_RUN environment variable; simply use the normal NASMENV environment variable instead. The .obj tests in travis needed to be updated in order to remove the rather pointless suffix " CONST" from the NASM signatures. Reported-by: Joshua Watt Signed-off-by: H. Peter Anvin (Intel) --- asm/nasm.c | 9 ++++++- doc/changes.src | 3 +++ doc/nasmdoc.src | 6 +++++ include/nasm.h | 9 ++++++- include/ver.h | 6 ++--- nasmlib/ver.c | 44 ++++++++++++++------------------- output/outcoff.c | 11 +-------- travis/nasm-t.py | 2 +- travis/test/alonesym-obj.obj.t | Bin 1161 -> 1155 bytes travis/test/br3392643.obj.t | Bin 349 -> 343 bytes travis/test/elif.o.t | Bin 230 -> 224 bytes travis/test/obj.o.t | Bin 480 -> 474 bytes 12 files changed, 48 insertions(+), 42 deletions(-) diff --git a/asm/nasm.c b/asm/nasm.c index c5d03c8a..e5ae89af 100644 --- a/asm/nasm.c +++ b/asm/nasm.c @@ -938,7 +938,8 @@ enum text_options { OPT_LIMIT, OPT_KEEP_ALL, OPT_NO_LINE, - OPT_DEBUG + OPT_DEBUG, + OPT_REPRODUCIBLE }; enum need_arg { ARG_NO, @@ -970,6 +971,7 @@ static const struct textargs textopts[] = { {"keep-all", OPT_KEEP_ALL, ARG_NO, 0}, {"no-line", OPT_NO_LINE, ARG_NO, 0}, {"debug", OPT_DEBUG, ARG_MAYBE, 0}, + {"reproducible", OPT_REPRODUCIBLE, ARG_NO, 0}, {NULL, OPT_BOGUS, ARG_NO, 0} }; @@ -1332,6 +1334,9 @@ static bool process_arg(char *p, char *q, int pass) case OPT_DEBUG: debug_nasm = param ? strtoul(param, NULL, 10) : debug_nasm+1; break; + case OPT_REPRODUCIBLE: + reproducible = true; + break; case OPT_HELP: help(stdout); exit(0); @@ -2293,6 +2298,8 @@ static void help(FILE *out) " --lprefix str prepend the given string to local symbols\n" " --lpostfix str append the given string to local symbols\n" "\n" + " --reproducible attempt to produce run-to-run identical output\n" + "\n" " -w+x enable warning x (also -Wx)\n" " -w-x disable warning x (also -Wno-x)\n" " -w[+-]error promote all warnings to errors (also -Werror)\n" diff --git a/doc/changes.src b/doc/changes.src index 9b0e02d0..7b9665a2 100644 --- a/doc/changes.src +++ b/doc/changes.src @@ -12,6 +12,9 @@ since 2007. \b Correct \c{%ifid $} and \c{%ifid $$} being treated as true. See \k{iftyp}. +\b Add \c{--reproducible} option to suppress NASM version numbers and +timestamps in output files. See \k{opt-reproducible}. + \S{cl-2.15.04} Version 2.15.04 \b More sensible handling of the case where one single-line macro diff --git a/doc/nasmdoc.src b/doc/nasmdoc.src index 027c7445..efbf3b23 100644 --- a/doc/nasmdoc.src +++ b/doc/nasmdoc.src @@ -982,6 +982,12 @@ If this option is given, all \i\c{%line} directives in the source code are ignored. This can be useful for debugging already preprocessed code. See \k{line}. +\S{opt-reproducible} The \i\c{--reproducible} Option + +If this option is given, NASM will not emit information that is +inherently dependent on the NASM version or different from run to run +(such as timestamps) into the output file. + \S{nasmenv} The \i\c{NASMENV} \i{Environment} Variable diff --git a/include/nasm.h b/include/nasm.h index cf8b808e..f6e77db6 100644 --- a/include/nasm.h +++ b/include/nasm.h @@ -1,6 +1,6 @@ /* ----------------------------------------------------------------------- * * - * Copyright 1996-2018 The NASM Authors - All Rights Reserved + * Copyright 1996-2020 The NASM Authors - All Rights Reserved * See the file AUTHORS included with the NASM distribution for * the specific copyright holders. * @@ -67,6 +67,13 @@ struct compile_time { }; extern struct compile_time official_compile_time; +/* POSIX timestamp if and only if we are not a reproducible build */ +extern bool reproducible; +static inline int64_t posix_timestamp(void) +{ + return reproducible ? 0 : official_compile_time.posix; +} + #define NO_SEG INT32_C(-1) /* null segment value */ #define SEG_ABS 0x40000000L /* mask for far-absolute segments */ diff --git a/include/ver.h b/include/ver.h index ab6e9784..a5bbf384 100644 --- a/include/ver.h +++ b/include/ver.h @@ -1,6 +1,6 @@ /* ----------------------------------------------------------------------- * * - * Copyright 1996-2016 The NASM Authors - All Rights Reserved + * Copyright 1996-2020 The NASM Authors - All Rights Reserved * See the file AUTHORS included with the NASM distribution for * the specific copyright holders. * @@ -44,12 +44,12 @@ extern const char nasm_version[]; extern const char nasm_date[]; extern const char nasm_compile_options[]; +extern bool reproducible; + extern const char *nasm_comment(void); extern size_t nasm_comment_len(void); extern const char *nasm_signature(void); extern size_t nasm_signature_len(void); -extern int nasm_test_run(void); - #endif /* NASM_VER_H */ diff --git a/nasmlib/ver.c b/nasmlib/ver.c index 9f80f79c..96260b6c 100644 --- a/nasmlib/ver.c +++ b/nasmlib/ver.c @@ -1,6 +1,6 @@ /* ----------------------------------------------------------------------- * * - * Copyright 1996-2016 The NASM Authors - All Rights Reserved + * Copyright 1996-2020 The NASM Authors - All Rights Reserved * See the file AUTHORS included with the NASM distribution for * the specific copyright holders. * @@ -43,46 +43,38 @@ const char nasm_compile_options[] = "" #endif ; -/* These are used by some backends. */ -static const char __nasm_comment[] = - "The Netwide Assembler " NASM_VER; +bool reproducible; /* Reproducible output */ -static const char __nasm_signature[] = - "NASM " NASM_VER; - -/* These are constant so we could pass regression tests */ -static const char __nasm_comment_const[] ="The Netwide Assembler CONST"; -static const char __nasm_signature_const[] = "NASM CONST"; - -int nasm_test_run(void) +/* These are used by some backends. For a reproducible build, + * these cannot contain version numbers. + */ +static const char * const _nasm_comment[2] = { - return getenv("NASM_TEST_RUN") ? 1 : 0; -} + "The Netwide Assembler " NASM_VER, + "The Netwide Assembler" +}; + +static const char * const _nasm_signature[2] = { + "NASM " NASM_VER, + "NASM" +}; const char *nasm_comment(void) { - if (!nasm_test_run()) - return __nasm_comment; - return __nasm_comment_const; + return _nasm_comment[reproducible]; } size_t nasm_comment_len(void) { - if (!nasm_test_run()) - return strlen(__nasm_comment); - return strlen(__nasm_comment_const); + return strlen(nasm_comment()); } const char *nasm_signature(void) { - if (!nasm_test_run()) - return __nasm_signature; - return __nasm_signature_const; + return _nasm_signature[reproducible]; } size_t nasm_signature_len(void) { - if (!nasm_test_run()) - return strlen(__nasm_signature); - return strlen(__nasm_signature_const); + return strlen(nasm_signature()); } diff --git a/output/outcoff.c b/output/outcoff.c index 6568ac23..58fa0249 100644 --- a/output/outcoff.c +++ b/output/outcoff.c @@ -936,16 +936,7 @@ static void coff_write(void) i = IMAGE_FILE_MACHINE_I386; fwriteint16_t(i, ofile); /* machine type */ fwriteint16_t(coff_nsects, ofile); /* number of sections */ - - /* - * When running tests we'are comparing binary output - * so time should be zapped. - */ - if (nasm_test_run()) - fwriteint32_t(0, ofile); /* time stamp */ - else - fwriteint32_t(time(NULL), ofile); /* time stamp */ - + fwriteint32_t(posix_timestamp(), ofile); /* timestamp */ fwriteint32_t(sympos, ofile); fwriteint32_t(coff_nsyms + initsym, ofile); fwriteint16_t(0, ofile); /* no optional header */ diff --git a/travis/nasm-t.py b/travis/nasm-t.py index 02b145db..2470ad45 100755 --- a/travis/nasm-t.py +++ b/travis/nasm-t.py @@ -340,7 +340,7 @@ def exec_nasm(desc): opts = [args.nasm] + prepare_run_opts(desc) nasm_env = os.environ.copy() - nasm_env['NASM_TEST_RUN'] = 'y' + nasm_env['NASMENV'] = '--reproducible' desc_env = desc.get('environ') if desc_env: diff --git a/travis/test/alonesym-obj.obj.t b/travis/test/alonesym-obj.obj.t index 99ec34c493745bb2b64aaa1051519ca4851de289..aa25a5c9c4c9c0e6420b96a7fe1fb07e5ae32f06 100644 GIT binary patch delta 38 tcmeC=Z04MxA}z_lz#tluk*eUAT2h{wlB(cXT%4Mll#^Oiz0uW$1pvw$3#0%5 delta 44 zcmZqX?BtxFqA1V6z#tuxk*eUAT2h{wlB(cXT%4Mll#^Pd;Oy@g9CBi#y$cHf7YPld diff --git a/travis/test/br3392643.obj.t b/travis/test/br3392643.obj.t index de1dafbb75b2aa31f6c60935ccf802a37bdcd9ab..28fbb387213197a65e510d22470f99c2d0de9785 100644 GIT binary patch delta 49 zcmcc1be(B}qKYH~1A}NtMyi5eYDsx!N~(fmadB#HQch}7^)x0%hW~kqxv3K;Zk@y! F3jl*g5e5JN delta 44 zcmcc4beCy@qM|$l1A}x(Myi5eYDsx!N~(fmadB#HQch}-g0sJ0aL9>`Hqwj$Fd_~N diff --git a/travis/test/elif.o.t b/travis/test/elif.o.t index 60336dcdc5247f6c72cbf3e9007ff7c4258f8364..89787192ac8a7309db27cdf9568deac8da152ca5 100644 GIT binary patch delta 20 bcmaFH_<(VO467sq1B2*9MN!7;iMA^NIgkZn delta 26 icmaFB_>6Ia468f?1B3KLMNxJIXMexokP{QlR{{WBB?n>v diff --git a/travis/test/obj.o.t b/travis/test/obj.o.t index a91f3ad1a0db93f8d228e33dacab0749ecd37535..b3607882246a2c1871811d4f57319fb6b8e790d6 100644 GIT binary patch delta 21 ccmaFBe2aO4G^->71B2*91yRQ8jW$ad0Y0h)a{vGU delta 27 jcmcb`{D66aG^;!V1B3KL1yObdXMexokP{otmM{VUV*>|s From 2f01a5ba4e7c610de67659842ddc0cfc77ca51eb Mon Sep 17 00:00:00 2001 From: "H. Peter Anvin (Intel)" Date: Thu, 27 Aug 2020 13:07:04 -0700 Subject: [PATCH 33/34] NASM 2.15.05rc2 --- version | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/version b/version index 812cda4c..221de2ed 100644 --- a/version +++ b/version @@ -1 +1 @@ -2.15.05rc1 +2.15.05rc2 From 214f2d4c56925a280c480950bbf71389e2169e1a Mon Sep 17 00:00:00 2001 From: "H. Peter Anvin" Date: Fri, 28 Aug 2020 08:53:28 -0700 Subject: [PATCH 34/34] NASM 2.15.05 --- version | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/version b/version index 221de2ed..bbd7a891 100644 --- a/version +++ b/version @@ -1 +1 @@ -2.15.05rc2 +2.15.05