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Add autogenerated instruction list to NASM documentation
1. Allow included files in rdsrc.pl 2. New program inslist.pl to generate instruction list from insns.dat 3. Mark certain comments in insns.dat as documentation subheaders 4. Add Instruction List appendix to nasmdoc.src 5. Update build process to invoke inslist.pl
This commit is contained in:
Charles Crayne
parent
e6c01e659e
commit
c17a0eb31b
@ -33,8 +33,9 @@ all: $(OUT)
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os2: nasm.inf
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# Consider html, txt and ps output a side effect
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nasmdoc.dip: nasmdoc.src rdsrc.pl
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nasmdoc.dip: nasmdoc.src rdsrc.pl inslist.pl ../insns.dat
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mkdir -p html
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$(PERL) $(srcdir)/inslist.pl
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$(PERL) $(srcdir)/rdsrc.pl < $<
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mv -f *.html html
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66
doc/inslist.pl
Normal file
66
doc/inslist.pl
Normal file
@ -0,0 +1,66 @@
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#!/usr/bin/perl
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#
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# inslist.pl produce inslist.src
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#
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# The Netwide Assembler is copyright (C) 1996 Simon Tatham and
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# Julian Hall. All rights reserved. The software is
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# redistributable under the licence given in the file "Licence"
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# distributed in the NASM archive.
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# Opcode prefixes which need their own opcode tables
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# LONGER PREFIXES FIRST!
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@disasm_prefixes = qw(0F24 0F25 0F38 0F3A 0F7A 0FA6 0FA7 0F);
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print STDERR "Reading insns.dat...\n";
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@args = ();
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undef $output;
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foreach $arg ( @ARGV ) {
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if ( $arg =~ /^\-/ ) {
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if ( $arg =~ /^\-([adins])$/ ) {
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$output = $1;
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} else {
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die "$0: Unknown option: ${arg}\n";
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}
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} else {
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push (@args, $arg);
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}
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}
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$fname = "../insns.dat" unless $fname = $args[0];
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open (F, $fname) || die "unable to open $fname";
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print STDERR "Writing inslist.src...\n";
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open S, ">inslist.src";
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$line = 0;
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$insns = 0;
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while (<F>) {
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$line++;
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if ( /^\s*;/ ) # comments
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{
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if ( /^\s*;\#\s*(.+)/ ) # section subheader
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{
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print S "\n\\S{} $1\n\n";
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}
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next;
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}
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chomp;
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my @entry = split;
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next if $#entry == -1; # blank lines
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(warn "line $line does not contain four fields\n"), next if $#entry != 3;
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@entry[1] =~ s/ignore//;
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@entry[1] =~ s/void//;
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@entry[3] =~ s/ignore//;
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@entry[3] =~ s/,SB//;
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@entry[3] =~ s/,SM//;
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@entry[3] =~ s/,SM2//;
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@entry[3] =~ s/,SQ//;
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@entry[3] =~ s/,AR2//;
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printf S "\\c %-16s %-24s %s\n",@entry[0],@entry[1],@entry[3];
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$insns++;
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}
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print S "\n";
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close S;
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close F;
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printf STDERR "Done: %d instructions\n", $insns;
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@ -39,6 +39,7 @@ echo This takes a while. Stretch!
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echo.
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echo.
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perl inslist.pl
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perl rdsrc.pl<nasmdoc.src
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echo.
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echo.
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@ -6880,3 +6880,14 @@ developer's site at
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and we'll try to fix them. Feel free to send contributions and
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new features as well.
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\A{inslist} \i{Instruction List}
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\H{inslistintro} Introduction
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The following sections show the instructions which NASM currently supports. For each
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instruction, there is a separate entry for each supported addressing mode. The third
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column shows the processor type in which the instruction was introduced and,
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when appropriate, one or more usage flags.
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\& inslist.src
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43
doc/rdsrc.pl
43
doc/rdsrc.pl
@ -79,6 +79,12 @@
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# defines document metadata, such as authorship, title and copyright;
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# different output formats use this differently.
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#
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# Include subfile
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# \&{filename}
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# Includes filename. Recursion is allowed.
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#
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use IO::File;
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$diag = 1, shift @ARGV if $ARGV[0] eq "-d";
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@ -96,15 +102,7 @@ $pname = "para000000";
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@pnames = @pflags = ();
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$para = undef;
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while (<>) {
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chomp;
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if (!/\S/ || /^\\(IA|IR|M)/) { # special case: \IA \IR \M imply new-paragraph
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&got_para($para);
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$para = undef;
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}
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if (/\S/) {
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s/\\#.*$//; # strip comments
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$para .= " " . $_;
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}
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&check_include($_);
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}
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&got_para($para);
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print "done.\n";
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@ -143,6 +141,33 @@ print "Producing Documentation Intermediate Paragraphs: ";
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&write_dip;
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print "done.\n";
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sub check_include {
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local $_ = shift;
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if (/\\& (\S+)/) {
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&include($1);
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} else {
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&get_para($_);
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}
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}
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sub get_para($_) {
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chomp;
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if (!/\S/ || /^\\(IA|IR|M)/) { # special case: \IA \IR \M imply new-paragraph
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&got_para($para);
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$para = undef;
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}
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if (/\S/) {
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s/\\#.*$//; # strip comments
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$para .= " " . $_;
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}
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}
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sub include {
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my $name = shift;
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my $F = IO::File->new($name)
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or die "Cannot open $name: $!";
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while (<$F>) {
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&check_include($_);
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}
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}
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sub got_para {
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local ($_) = @_;
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my $pflags = "", $i, $w, $l, $t;
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48
insns.dat
48
insns.dat
@ -14,8 +14,11 @@
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; see the comment at the top of assemble.c. For a detailed description
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; of the flags (fourth field), please see insns.h.
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;
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; Comments with a pound sign after the semicolon generate section
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; subheaders in the NASM documentation.
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; Special instructions...
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;# Special instructions...
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DB ignore ignore ignore
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DW ignore ignore ignore
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DD ignore ignore ignore
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@ -29,7 +32,7 @@ RESQ ignore ignore ignore
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REST ignore ignore ignore
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RESO ignore ignore ignore
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; Conventional instructions
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;# Conventional instructions
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AAA void \1\x37 8086,NOLONG
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AAD void \2\xD5\x0A 8086,NOLONG
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AAD imm \1\xD5\24 8086,SB,NOLONG
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@ -1375,7 +1378,7 @@ Jcc imm \330\x70\50 8086
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SETcc mem \1\x0F\330\x90\200 386,SB
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SETcc reg8 \1\x0F\330\x90\200 386
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; Katmai Streaming SIMD instructions (SSE -- a.k.a. KNI, XMM, MMX2)
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;# Katmai Streaming SIMD instructions (SSE -- a.k.a. KNI, XMM, MMX2)
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ADDPS xmmreg,xmmrm \331\2\x0F\x58\110 KATMAI,SSE
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ADDSS xmmreg,xmmrm \333\2\x0F\x58\110 KATMAI,SSE
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ANDNPS xmmreg,xmmrm \2\x0F\x55\110 KATMAI,SSE
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@ -1457,11 +1460,12 @@ UNPCKHPS xmmreg,xmmrm \2\x0F\x15\110 KATMAI,SSE
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UNPCKLPS xmmreg,xmmrm \2\x0F\x14\110 KATMAI,SSE
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XORPS xmmreg,xmmrm \2\x0F\x57\110 KATMAI,SSE
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; Introduced in Deschutes but necessary for SSE support
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;# Introduced in Deschutes but necessary for SSE support
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FXRSTOR mem \2\x0F\xAE\201 P6,SSE,FPU
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FXSAVE mem \2\x0F\xAE\200 P6,SSE,FPU
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; These instructions are not SSE-specific; they are generic memory operations
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; These instructions are not SSE-specific; they are
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;# Generic memory operations
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; and work even if CR4.OSFXFR == 0
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PREFETCHNTA mem \2\x0F\x18\200 KATMAI
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PREFETCHT0 mem \2\x0F\x18\201 KATMAI
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@ -1469,7 +1473,7 @@ PREFETCHT1 mem \2\x0F\x18\202 KATMAI
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PREFETCHT2 mem \2\x0F\x18\203 KATMAI
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SFENCE void \3\x0F\xAE\xF8 KATMAI
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; New MMX instructions introduced in Katmai
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;# New MMX instructions introduced in Katmai
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MASKMOVQ mmxreg,mmxreg \2\x0F\xF7\110 KATMAI,MMX
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MOVNTQ mem,mmxreg \2\x0F\xE7\101 KATMAI,MMX,SM
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PAVGB mmxreg,mmxrm \2\x0F\xE0\110 KATMAI,MMX,SM
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@ -1490,14 +1494,14 @@ PMULHUW mmxreg,mmxrm \2\x0F\xE4\110 KATMAI,MMX,SQ
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PSADBW mmxreg,mmxrm \2\x0F\xF6\110 KATMAI,MMX,SQ
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PSHUFW mmxreg,mmxrm,imm \2\x0F\x70\110\22 KATMAI,MMX,SM2,SB,AR2
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; AMD Enhanced 3DNow! (Athlon) instructions
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;# AMD Enhanced 3DNow! (Athlon) instructions
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PF2IW mmxreg,mmxrm \2\x0F\x0F\110\01\x1C PENT,3DNOW,SQ
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PFNACC mmxreg,mmxrm \2\x0F\x0F\110\01\x8A PENT,3DNOW,SQ
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PFPNACC mmxreg,mmxrm \2\x0F\x0F\110\01\x8E PENT,3DNOW,SQ
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PI2FW mmxreg,mmxrm \2\x0F\x0F\110\01\x0C PENT,3DNOW,SQ
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PSWAPD mmxreg,mmxrm \2\x0F\x0F\110\01\xBB PENT,3DNOW,SQ
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; Willamette SSE2 Cacheability Instructions
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;# Willamette SSE2 Cacheability Instructions
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MASKMOVDQU xmmreg,xmmreg \366\2\x0F\xF7\110 WILLAMETTE,SSE2
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; CLFLUSH needs its own feature flag implemented one day
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CLFLUSH mem \2\x0F\xAE\207 WILLAMETTE,SSE2
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@ -1508,7 +1512,7 @@ PAUSE void \333\1\x90 WILLAMETTE,SSE2
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LFENCE void \3\x0F\xAE\xE8 WILLAMETTE,SSE2
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MFENCE void \3\x0F\xAE\xF0 WILLAMETTE,SSE2
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; Willamette MMX instructions (SSE2 SIMD Integer Instructions)
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;# Willamette MMX instructions (SSE2 SIMD Integer Instructions)
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MOVD xmmreg,reg32 \366\2\x0F\x6E\110 WILLAMETTE,SSE2
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MOVD reg32,xmmreg \366\2\x0F\x7E\101 WILLAMETTE,SSE2
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MOVD mem,xmmreg \366\2\x0F\x7E\101 WILLAMETTE,SSE2,SD
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@ -1612,7 +1616,7 @@ PUNPCKLDQ xmmreg,xmmrm \366\2\x0F\x62\110 WILLAMETTE,SSE2,SM
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PUNPCKLQDQ xmmreg,xmmrm \366\2\x0F\x6C\110 WILLAMETTE,SSE2,SM
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PXOR xmmreg,xmmrm \366\2\x0F\xEF\110 WILLAMETTE,SSE2,SM
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; Willamette Streaming SIMD instructions (SSE2)
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;# Willamette Streaming SIMD instructions (SSE2)
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ADDPD xmmreg,xmmrm \331\366\2\x0F\x58\110 WILLAMETTE,SSE2,SM
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ADDSD xmmreg,xmmrm \331\332\2\x0F\x58\110 WILLAMETTE,SSE2
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ANDNPD xmmreg,xmmrm \331\366\2\x0F\x55\110 WILLAMETTE,SSE2,SM
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@ -1693,7 +1697,7 @@ UNPCKHPD xmmreg,xmmrm \366\2\x0F\x15\110 WILLAMETTE,SSE2,SM
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UNPCKLPD xmmreg,xmmrm \366\2\x0F\x14\110 WILLAMETTE,SSE2,SM
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XORPD xmmreg,xmmrm \366\2\x0F\x57\110 WILLAMETTE,SSE2,SM
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; Prescott New Instructions (SSE3)
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;# Prescott New Instructions (SSE3)
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ADDSUBPD xmmreg,xmmrm \366\2\x0F\xD0\110 PRESCOTT,SSE3,SM
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ADDSUBPS xmmreg,xmmrm \332\2\x0F\xD0\110 PRESCOTT,SSE3,SM
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HADDPD xmmreg,xmmrm \366\2\x0F\x7C\110 PRESCOTT,SSE3,SM
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@ -1705,7 +1709,7 @@ MOVDDUP xmmreg,xmmrm \332\2\x0F\x12\110 PRESCOTT,SSE3
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MOVSHDUP xmmreg,xmmrm \333\2\x0F\x16\110 PRESCOTT,SSE3
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MOVSLDUP xmmreg,xmmrm \333\2\x0F\x12\110 PRESCOTT,SSE3
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; VMX Instructions
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;# VMX Instructions
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VMCALL void \3\x0F\x01\xC1 VMX
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VMCLEAR mem \366\2\x0F\xC7\206 VMX
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VMLAUNCH void \3\x0F\x01\xC2 VMX
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@ -1721,7 +1725,7 @@ VMWRITE reg32,rm32 \2\x0F\x79\110 VMX
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VMXOFF void \3\x0F\x01\xC4 VMX
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VMXON mem \333\2\x0F\xC7\206 VMX
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; Tejas New Instructions (SSSE3)
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;# Tejas New Instructions (SSSE3)
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PABSB mmxreg,mmxrm \364\3\x0F\x38\x1C\110 SSSE3,MMX,SQ
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PABSB xmmreg,xmmrm \366\3\x0F\x38\x1C\110 SSSE3
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PABSW mmxreg,mmxrm \364\3\x0F\x38\x1D\110 SSSE3,MMX,SQ
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@ -1755,7 +1759,7 @@ PSIGNW xmmreg,xmmrm \366\3\x0F\x38\x09\110 SSSE3
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PSIGND mmxreg,mmxrm \364\3\x0F\x38\x0A\110 SSSE3,MMX,SQ
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PSIGND xmmreg,xmmrm \366\3\x0F\x38\x0A\110 SSSE3
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; AMD SSE4A
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;# AMD SSE4A
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EXTRQ xmmreg,imm,imm \366\2\x0F\x78\200\25\26 SSE4A,AMD
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EXTRQ xmmreg,xmmreg \366\2\x0F\x79\110 SSE4A,AMD
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INSERTQ xmmreg,xmmreg,imm,imm \332\2\x0F\x78\110\26\27 SSE4A,AMD
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@ -1763,12 +1767,12 @@ INSERTQ xmmreg,xmmreg \332\2\x0F\x79\110 SSE4A,AMD
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MOVNTSD mem,xmmreg \332\2\x0F\x2B\101 SSE4A,AMD,SQ
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MOVNTSS mem,xmmreg \333\2\x0F\x2B\101 SSE4A,AMD,SD
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; New instructions in Barcelona
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;# New instructions in Barcelona
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LZCNT reg16,rm16 \320\333\2\x0F\xBD\110 P6,AMD
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LZCNT reg32,rm32 \321\333\2\x0F\xBD\110 P6,AMD
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LZCNT reg64,rm64 \324\333\2\x0F\xBD\110 P6,AMD
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; Penryn New Instructions (SSE4.1)
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;# Penryn New Instructions (SSE4.1)
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BLENDPD xmmreg,xmmrm,imm \366\3\x0F\x3A\x0D\110\26 SSE41
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BLENDPS xmmreg,xmmrm,imm \366\3\x0F\x3A\x0C\110\26 SSE41
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BLENDVPD xmmreg,xmmrm,xmm0 \366\3\x0F\x38\x15\110 SSE41
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@ -1825,7 +1829,7 @@ ROUNDPS xmmreg,xmmrm,imm \366\3\x0F\x3A\x08\110\26 SSE41
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ROUNDSD xmmreg,xmmrm,imm \366\3\x0F\x3A\x0B\110\26 SSE41
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ROUNDSS xmmreg,xmmrm,imm \366\3\x0F\x3A\x0A\110\26 SSE41
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; Nehalem New Instructions (SSE4.2)
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;# Nehalem New Instructions (SSE4.2)
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CRC32 reg32,rm8 \332\3\x0F\x38\1\xF0\110 SSE42
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CRC32 reg32,rm16 \332\3\x0F\x38\1\xF1\110 SSE42
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CRC32 reg32,rm32 \332\3\x0F\x38\1\xF1\110 SSE42
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@ -1840,7 +1844,7 @@ POPCNT reg16,rm16 \320\333\2\x0F\xB8\110 NEHALEM
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POPCNT reg32,rm32 \321\333\2\x0F\xB8\110 NEHALEM
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POPCNT reg64,rm32 \324\333\2\x0F\xB8\110 NEHALEM,X64
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; AMD SSE5 instructions
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;# AMD SSE5 instructions
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; Four operands with DREX
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FMADDPS xmmreg,=0,xmmreg,xmmrm \160\2\x0F\x24\170\132 SSE5,AMD
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@ -2006,14 +2010,14 @@ ROUNDPD xmmreg,xmmrm,imm \366\3\x0F\x3A\x08\110\26 SSE5,AMD
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ROUNDSS xmmreg,xmmrm,imm \366\3\x0F\x3A\x08\110\26 SSE5,AMD
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ROUNDSD xmmreg,xmmrm,imm \366\3\x0F\x3A\x08\110\26 SSE5,AMD
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; Intel SMX
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;# Intel SMX
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GETSEC void \2\x0F\x37 KATMAI
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; Geode (Cyrix) 3DNow! additions
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;# Geode (Cyrix) 3DNow! additions
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PFRCP mmxreg,mmxrm \2\x0F\x0F\110\1\x86 PENT,3DNOW,SM,CYRIX
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PFRSQRT mmxreg,mmxrm \2\x0F\x0F\110\1\x87 PENT,3DNOW,SM,CYRIX
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; VIA (Centaur) security instructions
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;# VIA (Centaur) security instructions
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XSTORE void \3\x0F\xA7\xC0 PENT,CYRIX
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XCRYPTECB void \333\3\x0F\xA7\xC8 PENT,CYRIX
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XCRYPTCBC void \333\3\x0F\xA7\xD0 PENT,CYRIX
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@ -2023,7 +2027,7 @@ MONTMUL void \333\3\x0F\xA6\xC0 PENT,CYRIX
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XSHA1 void \333\3\x0F\xA6\xC8 PENT,CYRIX
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XSHA256 void \333\3\x0F\xA6\xD0 PENT,CYRIX
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; Systematic names for the hinting nop instructions
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;# Systematic names for the hinting nop instructions
|
||||
HINT_NOP0 rm16 \320\2\x0F\x18\200 P6,UNDOC
|
||||
HINT_NOP0 rm32 \321\2\x0F\x18\200 P6,UNDOC
|
||||
HINT_NOP0 rm64 \324\2\x0F\x18\200 X64,UNDOC
|
||||
|
||||
@ -60,7 +60,7 @@ zip -k ${NASM_DOS_ZIP} *.exe misc/exasm.zip
|
||||
rm -f nasm.doc
|
||||
(cd doc; zip -l -k ../${NASM_DOC_ZIP} \
|
||||
Readme \
|
||||
nasmdoc.src rdsrc.pl \
|
||||
nasmdoc.src rdsrc.pl inslist.pl \
|
||||
nasmdoc.txt \
|
||||
nasmdoc.ps \
|
||||
*.html
|
||||
|
||||
Loading…
Reference in New Issue
Block a user