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https://github.com/netwide-assembler/nasm.git
synced 2025-03-19 18:00:23 +08:00
Fix handling of XCHG in 64-bit mode
The handling of XCHG in 64-bit mode somewhat broken. Add a register flag for "not accumulator", so we can generate all the appropriate modes.
This commit is contained in:
H. Peter Anvin
parent
ce6c8a7929
commit
aff9c93aa4
13
insns.dat
13
insns.dat
@ -1257,11 +1257,14 @@ XBTS reg16,mem \320\2\x0F\xA6\110 386,SW,UNDOC,ND
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XBTS reg16,reg16 \320\2\x0F\xA6\110 386,UNDOC,ND
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XBTS reg32,mem \321\2\x0F\xA6\110 386,SD,UNDOC,ND
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XBTS reg32,reg32 \321\2\x0F\xA6\110 386,UNDOC,ND
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XCHG reg_ax,reg16 \320\11\x90 8086,NOLONG
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XCHG reg_eax,reg32 \321\11\x90 386,NOLONG
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XCHG reg16,reg_ax \320\10\x90 8086,NOLONG
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XCHG reg32,reg_eax \321\10\x90 386,NOLONG
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XCHG reg_rax,reg_rax \321\11\x90 X64
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XCHG reg_ax,reg16 \320\11\x90 8086
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XCHG reg_eax,reg32na \321\11\x90 386
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XCHG reg_rax,reg64na \324\11\x90 X64
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XCHG reg16,reg_ax \320\10\x90 8086
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XCHG reg32na,reg_eax \321\10\x90 386
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XCHG reg64na,reg_rax \324\10\x90 X64
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XCHG reg_eax,reg_eax \321\1\x90 386,NOLONG
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XCHG reg_rax,reg_rax \323\1\x90 X64
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XCHG reg8,mem \1\x86\110 8086,SM
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XCHG reg8,reg8 \1\x86\110 8086
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XCHG reg16,mem \320\1\x87\110 8086,SM
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154
nasm.h
154
nasm.h
@ -397,17 +397,18 @@ enum {
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* 14: MEMORY (always has REGMEM attribute as well)
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* 15: REGMEM (valid EA operand)
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*
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* Bits 16-19: subclasses
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* Bits 16-19, 28: subclasses
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* With REG_CDT:
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* 16: REG_CREG (CRx)
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* 17: REG_DREG (DRx)
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* 18: REG_TREG (TRx)
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* With REG_GPR:
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* 16: REG_ACCUM (AL, AX, EAX, RAX)
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* 17: REG_COUNT (CL, CX, ECX, RCX)
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* 18: REG_DATA (DL, DX, EDX, RDX)
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* 19: REG_HIGH (AH, CH, DH, BH)
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* 16: REG_ACCUM (AL, AX, EAX, RAX)
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* 17: REG_COUNT (CL, CX, ECX, RCX)
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* 18: REG_DATA (DL, DX, EDX, RDX)
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* 19: REG_HIGH (AH, CH, DH, BH)
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* 28: REG_NOTACC (not REG_ACCUM)
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*
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* With REG_SREG:
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* 16: REG_CS
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@ -438,7 +439,7 @@ enum {
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* 25: RM_MMX (MMXREG)
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* 26: RM_XMM (XMMREG)
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*
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* Bits 27-29 & 31 are currently unallocated.
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* Bits 27, 31 are currently unallocated.
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*
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* 30: SAME_AS
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* Special flag only used in instruction patterns; means this operand
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@ -449,94 +450,99 @@ enum {
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typedef uint32_t opflags_t;
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/* Size, and other attributes, of the operand */
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#define BITS8 0x00000001L
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#define BITS16 0x00000002L
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#define BITS32 0x00000004L
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#define BITS64 0x00000008L /* x64 and FPU only */
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#define BITS80 0x00000010L /* FPU only */
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#define BITS128 0x20000000L
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#define FAR 0x00000020L /* grotty: this means 16:16 or */
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#define BITS8 0x00000001U
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#define BITS16 0x00000002U
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#define BITS32 0x00000004U
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#define BITS64 0x00000008U /* x64 and FPU only */
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#define BITS80 0x00000010U /* FPU only */
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#define BITS128 0x20000000U
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#define FAR 0x00000020U /* grotty: this means 16:16 or */
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/* 16:32, like in CALL/JMP */
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#define NEAR 0x00000040L
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#define SHORT 0x00000080L /* and this means what it says :) */
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#define NEAR 0x00000040U
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#define SHORT 0x00000080U /* and this means what it says :) */
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#define SIZE_MASK 0x200000FFL /* all the size attributes */
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#define SIZE_MASK 0x200000FFU /* all the size attributes */
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/* Modifiers */
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#define MODIFIER_MASK 0x00000f00L
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#define TO 0x00000100L /* reverse effect in FADD, FSUB &c */
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#define COLON 0x00000200L /* operand is followed by a colon */
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#define STRICT 0x00000400L /* do not optimize this operand */
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#define MODIFIER_MASK 0x00000f00U
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#define TO 0x00000100U /* reverse effect in FADD, FSUB &c */
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#define COLON 0x00000200U /* operand is followed by a colon */
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#define STRICT 0x00000400U /* do not optimize this operand */
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/* Type of operand: memory reference, register, etc. */
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#define OPTYPE_MASK 0x0000f000L
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#define REGISTER 0x00001000L /* register number in 'basereg' */
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#define IMMEDIATE 0x00002000L
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#define MEMORY 0x0000c000L
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#define REGMEM 0x00008000L /* for r/m, ie EA, operands */
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#define OPTYPE_MASK 0x0000f000U
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#define REGISTER 0x00001000U /* register number in 'basereg' */
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#define IMMEDIATE 0x00002000U
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#define MEMORY 0x0000c000U
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#define REGMEM 0x00008000U /* for r/m, ie EA, operands */
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/* Register classes */
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#define REG_EA 0x00009000L /* 'normal' reg, qualifies as EA */
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#define RM_GPR 0x00208000L /* integer operand */
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#define REG_GPR 0x00209000L /* integer register */
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#define REG8 0x00209001L /* 8-bit GPR */
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#define REG16 0x00209002L /* 16-bit GPR */
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#define REG32 0x00209004L /* 32-bit GPR */
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#define REG64 0x00209008L /* 64-bit GPR */
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#define IP_REG 0x00801000L /* RIP or EIP register */
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#define RIPREG 0x00801008L /* RIP */
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#define EIPREG 0x00801004L /* EIP */
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#define FPUREG 0x01001000L /* floating point stack registers */
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#define FPU0 0x01011000L /* FPU stack register zero */
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#define RM_MMX 0x02008000L /* MMX operand */
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#define MMXREG 0x02009000L /* MMX register */
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#define RM_XMM 0x04008000L /* XMM (SSE) operand */
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#define XMMREG 0x04009000L /* XMM (SSE) register */
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#define XMM0 0x04019000L /* XMM register zero */
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#define REG_CDT 0x00101004L /* CRn, DRn and TRn */
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#define REG_CREG 0x00111004L /* CRn */
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#define REG_DREG 0x00121004L /* DRn */
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#define REG_TREG 0x00141004L /* TRn */
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#define REG_SREG 0x00401002L /* any segment register */
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#define REG_CS 0x00411002L /* CS */
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#define REG_DESS 0x00421002L /* DS, ES, SS */
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#define REG_FSGS 0x00441002L /* FS, GS */
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#define REG_SEG67 0x00481002L /* Unimplemented segment registers */
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#define REG_EA 0x00009000U /* 'normal' reg, qualifies as EA */
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#define RM_GPR 0x00208000U /* integer operand */
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#define REG_GPR 0x00209000U /* integer register */
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#define REG8 0x00209001U /* 8-bit GPR */
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#define REG16 0x00209002U /* 16-bit GPR */
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#define REG32 0x00209004U /* 32-bit GPR */
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#define REG64 0x00209008U /* 64-bit GPR */
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#define IP_REG 0x00801000U /* RIP or EIP register */
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#define RIPREG 0x00801008U /* RIP */
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#define EIPREG 0x00801004U /* EIP */
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#define FPUREG 0x01001000U /* floating point stack registers */
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#define FPU0 0x01011000U /* FPU stack register zero */
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#define RM_MMX 0x02008000U /* MMX operand */
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#define MMXREG 0x02009000U /* MMX register */
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#define RM_XMM 0x04008000U /* XMM (SSE) operand */
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#define XMMREG 0x04009000U /* XMM (SSE) register */
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#define XMM0 0x04019000U /* XMM register zero */
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#define REG_CDT 0x00101004U /* CRn, DRn and TRn */
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#define REG_CREG 0x00111004U /* CRn */
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#define REG_DREG 0x00121004U /* DRn */
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#define REG_TREG 0x00141004U /* TRn */
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#define REG_SREG 0x00401002U /* any segment register */
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#define REG_CS 0x00411002U /* CS */
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#define REG_DESS 0x00421002U /* DS, ES, SS */
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#define REG_FSGS 0x00441002U /* FS, GS */
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#define REG_SEG67 0x00481002U /* Unimplemented segment registers */
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#define REG_RIP 0x00801008L /* RIP relative addressing */
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#define REG_EIP 0x00801004L /* EIP relative addressing */
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#define REG_RIP 0x00801008U /* RIP relative addressing */
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#define REG_EIP 0x00801004U /* EIP relative addressing */
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/* Special GPRs */
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#define REG_SMASK 0x000f0000L /* a mask for the following */
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#define REG_ACCUM 0x00219000L /* accumulator: AL, AX, EAX, RAX */
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#define REG_AL 0x00219001L
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#define REG_AX 0x00219002L
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#define REG_EAX 0x00219004L
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#define REG_RAX 0x00219008L
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#define REG_COUNT 0x00229000L /* counter: CL, CX, ECX, RCX */
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#define REG_CL 0x00229001L
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#define REG_CX 0x00229002L
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#define REG_ECX 0x00229004L
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#define REG_RCX 0x00229008L
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#define REG_DL 0x00249001L /* data: DL, DX, EDX, RDX */
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#define REG_DX 0x00249002L
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#define REG_EDX 0x00249004L
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#define REG_RDX 0x00249008L
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#define REG_HIGH 0x00289001L /* high regs: AH, CH, DH, BH */
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#define REG_SMASK 0x100f0000U /* a mask for the following */
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#define REG_ACCUM 0x00219000U /* accumulator: AL, AX, EAX, RAX */
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#define REG_AL 0x00219001U
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#define REG_AX 0x00219002U
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#define REG_EAX 0x00219004U
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#define REG_RAX 0x00219008U
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#define REG_COUNT 0x10229000U /* counter: CL, CX, ECX, RCX */
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#define REG_CL 0x10229001U
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#define REG_CX 0x10229002U
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#define REG_ECX 0x10229004U
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#define REG_RCX 0x10229008U
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#define REG_DL 0x10249001U /* data: DL, DX, EDX, RDX */
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#define REG_DX 0x10249002U
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#define REG_EDX 0x10249004U
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#define REG_RDX 0x10249008U
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#define REG_HIGH 0x10289001U /* high regs: AH, CH, DH, BH */
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#define REG_NOTACC 0x10000000U /* non-accumulator register */
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#define REG8NA 0x10209001U /* 8-bit non-acc GPR */
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#define REG16NA 0x10209002U /* 16-bit non-acc GPR */
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#define REG32NA 0x10209004U /* 32-bit non-acc GPR */
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#define REG64NA 0x10209008U /* 64-bit non-acc GPR */
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/* special types of EAs */
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#define MEM_OFFS 0x0001c000L /* simple [address] offset - absolute! */
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#define IP_REL 0x0002c000L /* IP-relative offset */
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#define MEM_OFFS 0x0001c000U /* simple [address] offset - absolute! */
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#define IP_REL 0x0002c000U /* IP-relative offset */
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/* memory which matches any type of r/m operand */
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#define MEMORY_ANY (MEMORY|RM_GPR|RM_MMX|RM_XMM)
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/* special type of immediate operand */
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#define UNITY 0x00012000L /* for shift/rotate instructions */
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#define SBYTE 0x00022000L /* for op r16/32,immediate instrs. */
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#define UNITY 0x00012000U /* for shift/rotate instructions */
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#define SBYTE 0x00022000U /* for op r16/32,immediate instrs. */
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/* special flags */
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#define SAME_AS 0x40000000L
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#define SAME_AS 0x40000000U
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/* Register names automatically generated from regs.dat */
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#include "regs.h"
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48
regs.dat
48
regs.dat
@ -16,11 +16,11 @@ ah REG_HIGH reg8 4
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ax REG_AX reg16 0
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eax REG_EAX reg32 0
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rax REG_RAX reg64 0
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bl REG8 reg8,reg8_rex 3
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bl REG8NA reg8,reg8_rex 3
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bh REG_HIGH reg8 7
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bx REG16 reg16 3
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ebx REG32 reg32 3
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rbx REG64 reg64 3
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bx REG16NA reg16 3
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ebx REG32NA reg32 3
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rbx REG64NA reg64 3
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cl REG_CL reg8,reg8_rex 1
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ch REG_HIGH reg8 5
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cx REG_CX reg16 1
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@ -31,26 +31,26 @@ dh REG_HIGH reg8 6
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dx REG_DX reg16 2
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edx REG_EDX reg32 2
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rdx REG_RDX reg64 2
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spl REG8 reg8_rex 4
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sp REG16 reg16 4
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esp REG32 reg32 4
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rsp REG64 reg64 4
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bpl REG8 reg8_rex 5
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bp REG16 reg16 5
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ebp REG32 reg32 5
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rbp REG64 reg64 5
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sil REG8 reg8_rex 6
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si REG16 reg16 6
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esi REG32 reg32 6
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rsi REG64 reg64 6
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dil REG8 reg8_rex 7
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di REG16 reg16 7
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edi REG32 reg32 7
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rdi REG64 reg64 7
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r8-15b REG8 reg8_rex 8
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r8-15w REG16 reg16 8
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r8-15d REG32 reg32 8
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r8-15 REG64 reg64 8
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spl REG8NA reg8_rex 4
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sp REG16NA reg16 4
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esp REG32NA reg32 4
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rsp REG64NA reg64 4
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bpl REG8NA reg8_rex 5
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bp REG16NA reg16 5
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ebp REG32NA reg32 5
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rbp REG64NA reg64 5
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sil REG8NA reg8_rex 6
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si REG16NA reg16 6
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esi REG32NA reg32 6
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rsi REG64NA reg64 6
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dil REG8NA reg8_rex 7
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di REG16NA reg16 7
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edi REG32NA reg32 7
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rdi REG64NA reg64 7
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r8-15b REG8NA reg8_rex 8
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r8-15w REG16NA reg16 8
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r8-15d REG32NA reg32 8
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r8-15 REG64NA reg64 8
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# Segment registers
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cs REG_CS sreg 1
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