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https://github.com/netwide-assembler/nasm.git
synced 2024-11-21 03:14:19 +08:00
Don't sort opcodes; move all pseudo-ops to the beginning
We don't need to sort opcodes anymore, since we are using an O(1) hash and not binary search. Instead, sort them in the order they first appear in insns.dat; this lets us move all the pseudo-ops to a contiguous range at the start of the file, for more efficient handling. Change the functions that process pseudo-ops accordingly. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
This commit is contained in:
H. Peter Anvin
parent
d23066906c
commit
af9fe8f597
@ -555,7 +555,7 @@ int64_t assemble(int32_t segment, int64_t start, int bits, insn *instruction)
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data.sign = OUT_WRAP;
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data.bits = bits;
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wsize = idata_bytes(instruction->opcode);
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wsize = db_bytes(instruction->opcode);
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if (wsize == -1)
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return 0;
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@ -790,7 +790,7 @@ int64_t insn_size(int32_t segment, int64_t offset, int bits, insn *instruction)
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int32_t isize, osize, wsize;
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isize = 0;
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wsize = idata_bytes(instruction->opcode);
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wsize = db_bytes(instruction->opcode);
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nasm_assert(wsize > 0);
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list_for_each(e, instruction->eops) {
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@ -666,7 +666,7 @@ is_float:
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eop->type = EOT_DB_STRING;
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result->eops_float = true;
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eop->stringlen = idata_bytes(result->opcode);
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eop->stringlen = db_bytes(result->opcode);
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if (eop->stringlen > 16) {
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nasm_error(ERR_NONFATAL, "floating-point constant"
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" encountered in DY or DZ instruction");
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@ -1129,7 +1129,7 @@ is_expression:
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* Transform RESW, RESD, RESQ, REST, RESO, RESY, RESZ into RESB.
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*/
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if (opcode_is_resb(result->opcode)) {
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result->oprs[0].offset *= resv_bytes(result->opcode);
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result->oprs[0].offset *= resb_bytes(result->opcode);
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result->oprs[0].offset *= result->times;
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result->times = 1;
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result->opcode = I_RESB;
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@ -62,61 +62,3 @@ const char *prefix_name(int token)
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return prefix_names[prefix];
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}
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/*
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* initialized data bytes length from opcode
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*/
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int idata_bytes(int opcode)
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{
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switch (opcode) {
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case I_DB:
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return 1;
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case I_DW:
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return 2;
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case I_DD:
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return 4;
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case I_DQ:
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return 8;
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case I_DT:
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return 10;
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case I_DO:
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return 16;
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case I_DY:
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return 32;
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case I_DZ:
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return 64;
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case I_none:
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return -1;
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default:
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return 0;
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}
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}
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/*
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* Uninitialized data bytes length from opcode
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*/
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int resv_bytes(int opcode)
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{
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switch (opcode) {
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case I_RESB:
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return 1;
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case I_RESW:
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return 2;
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case I_RESD:
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return 4;
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case I_RESQ:
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return 8;
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case I_REST:
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return 10;
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case I_RESO:
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return 16;
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case I_RESY:
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return 32;
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case I_RESZ:
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return 64;
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case I_none:
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return -1;
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default:
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return 0;
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}
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}
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@ -48,23 +48,79 @@ extern const uint8_t nasm_bytecodes[];
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*/
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#define ITEMPLATE_END {-1,-1,{-1,-1,-1,-1,-1},{-1,-1,-1,-1,-1},NULL,0}
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/* Width of Dx and RESx instructions */
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int const_func idata_bytes(enum opcode opcode);
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int const_func resv_bytes(enum opcode opcode);
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/*
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* Pseudo-op tests
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*/
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/* DB-type instruction (DB, DW, ...) */
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static inline bool opcode_is_db(enum opcode opcode)
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static inline bool const_func opcode_is_db(enum opcode opcode)
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{
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return idata_bytes(opcode) > 0;
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return opcode >= I_DB && opcode < I_RESB;
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}
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/* RESB-type instruction (RESB, RESW, ...) */
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static inline bool opcode_is_resb(enum opcode opcode)
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static inline bool const_func opcode_is_resb(enum opcode opcode)
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{
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return resv_bytes(opcode) > 0;
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return opcode >= I_RESB && opcode < I_INCBIN;
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}
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/* Width of Dx and RESx instructions */
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/*
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* initialized data bytes length from opcode
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*/
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static inline int const_func db_bytes(int opcode)
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{
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switch (opcode) {
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case I_DB:
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return 1;
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case I_DW:
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return 2;
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case I_DD:
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return 4;
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case I_DQ:
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return 8;
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case I_DT:
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return 10;
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case I_DO:
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return 16;
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case I_DY:
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return 32;
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case I_DZ:
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return 64;
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case I_none:
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return -1;
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default:
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return 0;
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}
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}
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/*
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* Uninitialized data bytes length from opcode
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*/
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static inline int resb_bytes(enum opcode opcode)
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{
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switch (opcode) {
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case I_RESB:
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return 1;
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case I_RESW:
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return 2;
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case I_RESD:
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return 4;
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case I_RESQ:
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return 8;
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case I_REST:
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return 10;
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case I_RESO:
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return 16;
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case I_RESY:
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return 32;
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case I_RESZ:
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return 64;
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case I_none:
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return -1;
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default:
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return 0;
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}
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}
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#endif /* NASM_INSNS_H */
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@ -48,6 +48,8 @@
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;
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;# Special instructions...
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; These MUST be first in this file and must maintain the pattern of
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; Dx by size, RESx by size, and INCBIN in that order.
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DB ignore ignore ignore
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DW ignore ignore ignore
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DD ignore ignore ignore
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@ -64,6 +66,7 @@ REST ignore ignore ignore
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RESO ignore ignore ignore
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RESY ignore ignore ignore
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RESZ ignore ignore ignore
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INCBIN ignore ignore ignore
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;# Conventional instructions
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AAA void [ 37] 8086,NOLONG
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@ -652,7 +655,6 @@ INC rm8 [m: hle fe /0] 8086,LOCK
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INC rm16 [m: hle o16 ff /0] 8086,LOCK
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INC rm32 [m: hle o32 ff /0] 386,LOCK
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INC rm64 [m: hle o64 ff /0] X64,LOCK
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INCBIN ignore ignore ignore
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INSB void [ 6c] 186
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INSD void [ o32 6d] 386
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INSW void [ o16 6d] 186
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15
x86/insns.pl
15
x86/insns.pl
@ -1,7 +1,7 @@
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#!/usr/bin/perl
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## --------------------------------------------------------------------------
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##
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## Copyright 1996-2016 The NASM Authors - All Rights Reserved
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## Copyright 1996-2017 The NASM Authors - All Rights Reserved
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## See the file AUTHORS included with the NASM distribution for
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## the specific copyright holders.
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##
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@ -89,6 +89,7 @@ open(F, '<', $fname) || die "unable to open $fname";
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$line = 0;
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$insns = 0;
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$n_opcodes = $n_opcodes_cc = 0;
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while (<F>) {
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$line++;
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chomp;
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@ -146,10 +147,14 @@ while (<F>) {
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}
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if ( $fields[0] =~ /cc$/ ) {
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# Conditional instruction
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$k_opcodes_cc{$fields[0]}++;
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if (!defined($k_opcodes_cc{$fields[0]})) {
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$k_opcodes_cc{$fields[0]} = $n_opcodes_cc++;
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}
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} else {
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# Unconditional instruction
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$k_opcodes{$fields[0]}++;
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if (!defined($k_opcodes{$fields[0]})) {
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$k_opcodes{$fields[0]} = $n_opcodes++;
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}
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}
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if ($formatted && !$nd) {
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push @big, $formatted;
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@ -189,8 +194,8 @@ foreach $bl (@bytecode_list) {
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}
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undef @bytecode_list;
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@opcodes = sort keys(%k_opcodes);
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@opcodes_cc = sort keys(%k_opcodes_cc);
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@opcodes = sort { $k_opcodes{$a} <=> $k_opcodes{$b} } keys(%k_opcodes);
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@opcodes_cc = sort { $k_opcodes_cc{$a} <=> $k_opcodes_cc{$b} } keys(%k_opcodes_cc);
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if ( $output eq 'b') {
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print STDERR "Writing $oname...\n";
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