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Remove bogus check for 64-bitness

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Remove a bogus check for 64-bit operands.  If appropriate, we will
detect this during REX generation and will bail then.  However, there
are other instructions (floating point, MMX, ...) which are legitimately
64 bits in non-64-bit mode.
This commit is contained in:
H. Peter Anvin 2007-05-30 03:44:02 +00:00
parent 3df97a7270
commit a57e8d411a
1 changed files with 1 additions and 8 deletions
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9
assemble.c
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@ -531,8 +531,6 @@ int32_t assemble(int32_t segment, int32_t offset, int bits, uint32_t cp,
error(ERR_NONFATAL, "no instruction for this cpu level"); error(ERR_NONFATAL, "no instruction for this cpu level");
else if (size_prob == 4) else if (size_prob == 4)
error(ERR_NONFATAL, "instruction not supported in 64-bit mode"); error(ERR_NONFATAL, "instruction not supported in 64-bit mode");
else if (size_prob == 5)
error(ERR_NONFATAL, "invalid operands in non-64-bit mode");
else else
error(ERR_NONFATAL, error(ERR_NONFATAL,
"invalid combination of opcode and operands"); "invalid combination of opcode and operands");
@ -1611,11 +1609,6 @@ static int matches(struct itemplate *itemp, insn * instruction, int bits)
(instruction->oprs[i].type & SIZE_MASK & ~size[i])) (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
return 2; return 2;
if ( (((itemp->opd[i] & SIZE_MASK) == BITS64) ||
((instruction->oprs[i].type & SIZE_MASK) == BITS64))
&& bits != 64)
return 5;
x = instruction->oprs[i].indexreg; x = instruction->oprs[i].indexreg;
b = instruction->oprs[i].basereg; b = instruction->oprs[i].basereg;
@ -1730,7 +1723,7 @@ static ea *process_ea(operand * input, ea * output, int addrbits,
if (bt != -1) { if (bt != -1) {
if ((REG_GPR & ~bx) && (IP_REG & ~bx)) if ((REG_GPR & ~bx) && (IP_REG & ~bx))
return NULL; /* Invalid register */ return NULL; /* Invalid register */
if (sok & ~bx) if (~sok & bx & SIZE_MASK)
return NULL; /* Invalid size */ return NULL; /* Invalid size */
sok &= ~bx; sok &= ~bx;
if (!(IP_REG & ~bx)) { if (!(IP_REG & ~bx)) {