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https://github.com/netwide-assembler/nasm.git
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Optimize mov r64,imm
Handle immediate-size optimization for "mov r64,imm" -- reduce it to "mov r32,imm32" or "mov r64,imm32" as appropriate. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
This commit is contained in:
H. Peter Anvin
parent
47fb7bc088
commit
9df010725f
@ -813,6 +813,8 @@ MOV reg64,reg64 \324\1\x8B\110 X64
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MOV reg8,imm \10\xB0\21 8086,SM
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MOV reg16,imm \320\10\xB8\31 8086,SM
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MOV reg32,imm \321\10\xB8\41 386,SM
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MOV reg64,udword64 \323\10\xB8\41 X64,SM,OPT,ND
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MOV reg64,sdword64 \324\1\xC7\200\255 X64,SM,OPT,ND
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MOV reg64,imm \324\10\xB8\55 X64,SM
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MOV rm8,imm \1\xC6\200\21 8086,SM
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MOV rm16,imm \320\1\xC7\200\31 8086,SM
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2
insns.pl
2
insns.pl
@ -442,7 +442,7 @@ sub format_insn($$$$$) {
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if ($opp =~ /^(.*[^\d])(8|16|32|64|80|128|256)$/) {
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my $ox = $1;
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my $on = $2;
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if ($ox !~ /^sbyte$/) {
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if ($ox !~ /^(sbyte|sdword|udword)$/) {
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$opp = $ox;
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push(@oppx, "bits$on");
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}
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2
nasm.h
2
nasm.h
@ -1,6 +1,6 @@
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/* ----------------------------------------------------------------------- *
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*
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* Copyright 1996-2009 The NASM Authors - All Rights Reserved
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* Copyright 1996-2010 The NASM Authors - All Rights Reserved
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* See the file AUTHORS included with the NASM distribution for
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* the specific copyright holders.
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*
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15
opflags.h
15
opflags.h
@ -66,11 +66,10 @@
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* 23: 256 bits (YWORD)
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* 29: 128 bits (OWORD)
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*
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* Bits 8-11 modifiers
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* Bits 8-10 modifiers
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* 8: TO
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* 9: COLON
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* 10: STRICT
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* 11: (reserved)
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*
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* Bits 12-15: type of operand
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* 12: REGISTER
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@ -78,7 +77,7 @@
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* 14: MEMORY (always has REGMEM attribute as well)
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* 15: REGMEM (valid EA operand)
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*
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* Bits 16-19, 28: subclasses
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* Bits 11, 16-19, 28: subclasses
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* With REG_CDT:
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* 16: REG_CREG (CRx)
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* 17: REG_DREG (DRx)
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@ -115,6 +114,8 @@
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* 17: BYTENESS16 (-128..127)
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* 18: BYTENESS32 (-128..127)
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* 19: BYTENESS64 (-128..127)
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* 28: SDWORD64 (-2^31..2^31-1)
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* 11: UDWORD64 (0..2^32-1)
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*
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* Bits 20-22, 24-27: register classes
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* 20: REG_CDT (CRx, DRx, TRx)
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@ -125,8 +126,6 @@
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* 26: RM_XMM (XMMREG)
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* 27: RM_YMM (YMMREG)
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*
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* Bit 31 is currently unallocated.
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*
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* 30: SAME_AS
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* Special flag only used in instruction patterns; means this operand
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* has to be identical to another operand. Currently only supported
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@ -151,7 +150,7 @@ typedef uint32_t opflags_t;
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#define SIZE_MASK 0x208000FFU /* all the size attributes */
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/* Modifiers */
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#define MODIFIER_MASK 0x00000f00U
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#define MODIFIER_MASK 0x00000700U
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#define TO 0x00000100U /* reverse effect in FADD, FSUB &c */
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#define COLON 0x00000200U /* operand is followed by a colon */
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#define STRICT 0x00000400U /* do not optimize this operand */
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@ -197,7 +196,7 @@ typedef uint32_t opflags_t;
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#define REG_EIP 0x00801004U /* EIP relative addressing */
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/* Special GPRs */
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#define REG_SMASK 0x100f0000U /* a mask for the following */
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#define REG_SMASK 0x100f0800U /* a mask for the following */
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#define REG_ACCUM 0x00219000U /* accumulator: AL, AX, EAX, RAX */
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#define REG_AL 0x00219001U
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#define REG_AX 0x00219002U
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@ -232,6 +231,8 @@ typedef uint32_t opflags_t;
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#define SBYTE32 0x00042000U /* for op r32,immediate instrs. */
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#define SBYTE64 0x00082000U /* for op r64,immediate instrs. */
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#define BYTENESS 0x000e0000U /* for testing for byteness */
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#define SDWORD64 0x10002000U /* for op r64,simm32 instrs. */
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#define UDWORD64 0x00002800U /* for op r64,uimm32 instrs. */
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/* special flags */
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#define SAME_AS 0x40000000U
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9
parser.c
9
parser.c
@ -843,7 +843,8 @@ is_expression:
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if(optimizing >= 0 && !(result->oprs[operand].type & STRICT))
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{
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/* Be optimistic */
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result->oprs[operand].type |= SBYTE16 | SBYTE32 | SBYTE64;
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result->oprs[operand].type |=
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SBYTE16 | SBYTE32 | SBYTE64 | UDWORD64 | SDWORD64;
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}
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} else if (is_reloc(value)) { /* it's immediate */
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result->oprs[operand].type |= IMMEDIATE;
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@ -865,6 +866,12 @@ is_expression:
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result->oprs[operand].type |= SBYTE32;
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if (v16 >= -128 && v16 <= 127)
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result->oprs[operand].type |= SBYTE16;
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if ((uint64_t)v64 <= UINT64_C(0xffffffff))
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result->oprs[operand].type |= UDWORD64;
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if (v64 >= -INT64_C(2147483648) &&
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v64 <= INT64_C(2147483647))
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result->oprs[operand].type |= SDWORD64;
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}
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}
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} else { /* it's a register */
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@ -9,3 +9,53 @@
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mov [rax],dword 11223344h ; 32-bit operation
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mov qword [rax],11223344h
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mov qword [rax],dword 11223344h
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mov rax,0_ffffffff_8899aabbh
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mov rax,dword 0_ffffffff_8899aabbh
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mov eax,0_ffffffff_8899aabbh
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mov [rax],dword 0_ffffffff_8899aabbh ; 32-bit operation
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mov qword [rax],0_ffffffff_8899aabbh
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mov qword [rax],dword 0_ffffffff_8899aabbh
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mov rax,7fffffffh
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mov rax,80000000h
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mov rax,0_ffffffffh
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mov rax,1_00000000h
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mov rax,0_ffffffff_7fffffffh
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mov rax,0_ffffffff_80000000h
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mov rax,0_11223344_8899aabbh
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mov rax,dword 0_11223344_8899aabbh
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mov eax,0_11223344_8899aabbh
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mov [rax],dword 0_11223344_8899aabbh ; 32-bit operation
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mov qword [rax],0_11223344_8899aabbh
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mov qword [rax],dword 0_11223344_8899aabbh
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mov rax,strict 11223344h
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mov rax,strict dword 11223344h
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mov eax,strict 11223344h
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mov [rax],strict dword 11223344h ; 32-bit operation
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mov qword [rax],strict 11223344h
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mov qword [rax],strict dword 11223344h
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mov rax,strict 0_ffffffff_8899aabbh
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mov rax,strict dword 0_ffffffff_8899aabbh
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mov eax,strict 0_ffffffff_8899aabbh
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mov [rax],strict dword 0_ffffffff_8899aabbh ; 32-bit operation
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mov qword [rax],strict 0_ffffffff_8899aabbh
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mov qword [rax],strict dword 0_ffffffff_8899aabbh
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mov rax,strict 7fffffffh
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mov rax,strict 80000000h
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mov rax,strict 0_ffffffffh
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mov rax,strict 1_00000000h
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mov rax,strict 0_ffffffff_7fffffffh
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mov rax,strict 0_ffffffff_80000000h
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mov rax,strict 0_11223344_8899aabbh
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mov rax,strict dword 0_11223344_8899aabbh
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mov eax,strict 0_11223344_8899aabbh
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mov [rax],strict dword 0_11223344_8899aabbh ; 32-bit operation
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mov qword [rax],strict 0_11223344_8899aabbh
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mov qword [rax],strict dword 0_11223344_8899aabbh
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