mirror of
https://github.com/netwide-assembler/nasm.git
synced 2025-03-19 18:00:23 +08:00
Clean up the 64-bitification of regs.dat for 64-bit ndisasm support
64-bit support required some major changes to regs.dat; clean some of it up (re-introduce patterns, where appropriate) and allow a single register to belong to multiple disassembly classes; also keep track of the x86 register number again.
This commit is contained in:
H. Peter Anvin
parent
2b8f5d2b80
commit
99f309cc07
1
nasm.h
1
nasm.h
@ -433,7 +433,6 @@ enum {
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#define REG_CREG 0x08101004L /* CRn */
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#define REG_DREG 0x10101004L /* DRn */
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#define REG_TREG 0x20101004L /* TRn */
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#define REG_C8REG 0x40101004L /* CR8 */
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/* special type of EA */
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#define MEM_OFFS 0x00604000L /* simple [address] offset */
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26
ndisasm.c
26
ndisasm.c
@ -25,8 +25,8 @@ static const char *help =
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"usage: ndisasm [-a] [-i] [-h] [-r] [-u] [-b bits] [-o origin] [-s sync...]\n"
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" [-e bytes] [-k start,bytes] [-p vendor] file\n"
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" -a or -i activates auto (intelligent) sync\n"
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" -u sets USE32 (32-bit mode)\n"
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" -b 16 or -b 32 sets number of bits too\n"
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" -u same as -b 32\n"
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" -b 16, -b 32 or -b 64 sets the processor mode\n"
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" -h displays this text\n"
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" -r or -v displays the version number\n"
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" -e skips <bytes> bytes of header\n"
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@ -38,7 +38,7 @@ static void skip(uint32_t dist, FILE * fp);
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int main(int argc, char **argv)
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{
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uint8_t buffer[INSN_MAX * 2], *p, *q;
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char buffer[INSN_MAX * 2], *p, *ep, *q;
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char outbuf[256];
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char *pname = *argv;
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char *filename = NULL;
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@ -46,7 +46,7 @@ int main(int argc, char **argv)
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int lenread;
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int32_t lendis;
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int autosync = FALSE;
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int bits = 16;
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int bits = 16, b;
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int eof = FALSE;
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uint32_t prefer = 0;
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int rn_error;
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@ -76,8 +76,9 @@ int main(int argc, char **argv)
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"NDISASM version %s compiled " __DATE__ "\n",
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NASM_VER);
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return 0;
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case 'u': /* USE32 */
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bits = 32;
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case 'u': /* -u for -b 32, -uu for -b 64 */
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if (bits < 64)
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bits <<= 1;
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p++;
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break;
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case 'b': /* bits */
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@ -87,14 +88,13 @@ int main(int argc, char **argv)
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pname);
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return 1;
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}
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if (!strcmp(v, "16"))
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bits = 16;
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else if (!strcmp(v, "32"))
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bits = 32;
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else {
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b = strtoul(v, &ep, 10);
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if (*ep || !(bits == 16 || bits == 32 || bits == 64)) {
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fprintf(stderr, "%s: argument to `-b' should"
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" be `16' or `32'\n", pname);
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}
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" be 16, 32 or 64\n", pname);
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} else {
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bits = b;
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}
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p = ""; /* force to next argument */
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break;
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case 'o': /* origin */
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256
regs.dat
256
regs.dat
@ -2,8 +2,17 @@
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#
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# List of registers and their classes; classes are defined in nasm.h
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#
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# The columns are: register name, assembler class, disassembler class, regval
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# A * means the line should be repeated for each value from 0 to 7
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# The columns are:
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#
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# register name, assembler class, disassembler class(es),
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# NASM register number, x86 register number
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#
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# If the register name ends in *, then it is repeated 8 times
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# with the following changes:
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# - a numerical tail to register number is incremented
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# - the NASM and x86 register numbers are incremented
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#
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# For 16-register register sets, two * lines are required.
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#
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# Legacy Registers
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@ -35,169 +44,112 @@
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# General-purpose registers
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al REG_AL reg8 0000
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ah REG8 reg8 0004
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ax REG_AX reg16 0010
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eax REG_EAX reg32 0020
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rax REG_RAX reg64 0440
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bl REG8 reg8 0003
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bh REG8 reg8 0007
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bx REG16 reg16 0013
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ebx REG32 reg32 0023
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rbx REG64 reg64 0443
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cl REG_CL reg8 0001
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ch REG8 reg8 0005
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cx REG_CX reg16 0011
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ecx REG_ECX reg32 0021
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rcx REG_RCX reg64 0441
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dl REG_DL reg8 0002
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dh REG8 reg8 0006
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dx REG_DX reg16 0012
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edx REG_EDX reg32 0022
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rdx REG_RDX reg64 0442
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spl REG8 reg8 0404
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sp REG16 reg16 0014
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esp REG32 reg32 0024
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rsp REG64 reg64 0444
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bpl REG8 reg8 0405
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bp REG16 reg16 0015
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ebp REG32 reg32 0025
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rbp REG64 reg64 0445
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sil REG8 reg8 0406
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si REG16 reg16 0016
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esi REG32 reg32 0026
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rsi REG64 reg64 0446
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dil REG8 reg8 0407
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di REG16 reg16 0017
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edi REG32 reg32 0027
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rdi REG64 reg64 0447
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r8b REG8 reg8 0410
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r8w REG16 reg16 0420
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r8d REG32 reg32 0430
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r8 REG64 reg64 0450
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r9b REG8 reg8 0411
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r9w REG16 reg16 0421
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r9d REG32 reg32 0431
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r9 REG64 reg64 0451
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r10b REG8 reg8 0412
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r10w REG16 reg16 0422
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r10d REG32 reg32 0432
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r10 REG64 reg64 0452
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r11b REG8 reg8 0413
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r11w REG16 reg16 0423
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r11d REG32 reg32 0433
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r11 REG64 reg64 0453
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r12b REG8 reg8 0414
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r12w REG16 reg16 0424
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r12d REG32 reg32 0434
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r12 REG64 reg64 0454
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r13b REG8 reg8 0415
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r13w REG16 reg16 0425
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r13d REG32 reg32 0435
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r13 REG64 reg64 0455
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r14b REG8 reg8 0416
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r14w REG16 reg16 0426
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r14d REG32 reg32 0436
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r14 REG64 reg64 0456
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r15b REG8 reg8 0417
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r15w REG16 reg16 0427
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r15d REG32 reg32 0437
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r15 REG64 reg64 0457
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al REG_AL reg8,reg8_rex 0000 0
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ah REG8 reg8 0004 4
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ax REG_AX reg16 0010 0
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eax REG_EAX reg32 0020 0
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rax REG_RAX reg64 0440 0
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bl REG8 reg8,reg8_rex 0003 3
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bh REG8 reg8 0007 7
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bx REG16 reg16 0013 3
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ebx REG32 reg32 0023 3
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rbx REG64 reg64 0443 3
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cl REG_CL reg8,reg8_rex 0001 1
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ch REG8 reg8 0005 5
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cx REG_CX reg16 0011 1
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ecx REG_ECX reg32 0021 1
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rcx REG_RCX reg64 0441 1
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dl REG_DL reg8,reg8_rex 0002 2
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dh REG8 reg8 0006 6
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dx REG_DX reg16 0012 2
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edx REG_EDX reg32 0022 2
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rdx REG_RDX reg64 0442 2
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spl REG8 reg8_rex 0404 4
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sp REG16 reg16 0014 4
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esp REG32 reg32 0024 4
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rsp REG64 reg64 0444 4
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bpl REG8 reg8_rex 0405 5
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bp REG16 reg16 0015 5
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ebp REG32 reg32 0025 5
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rbp REG64 reg64 0445 5
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sil REG8 reg8_rex 0406 6
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si REG16 reg16 0016 6
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esi REG32 reg32 0026 6
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rsi REG64 reg64 0446 6
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dil REG8 reg8_rex 0407 7
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di REG16 reg16 0017 7
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edi REG32 reg32 0027 7
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rdi REG64 reg64 0447 7
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r8b REG8 reg8_rex 0410 8
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r8w REG16 reg16 0420 8
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r8d REG32 reg32 0430 8
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r8 REG64 reg64 0450 8
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r9b REG8 reg8_rex 0411 9
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r9w REG16 reg16 0421 9
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r9d REG32 reg32 0431 9
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r9 REG64 reg64 0451 9
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r10b REG8 reg8_rex 0412 10
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r10w REG16 reg16 0422 10
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r10d REG32 reg32 0432 10
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r10 REG64 reg64 0452 10
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r11b REG8 reg8_rex 0413 11
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r11w REG16 reg16 0423 11
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r11d REG32 reg32 0433 11
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r11 REG64 reg64 0453 11
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r12b REG8 reg8_rex 0414 12
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r12w REG16 reg16 0424 12
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r12d REG32 reg32 0434 12
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r12 REG64 reg64 0454 12
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r13b REG8 reg8_rex 0415 13
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r13w REG16 reg16 0425 13
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r13d REG32 reg32 0435 13
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r13 REG64 reg64 0455 13
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r14b REG8 reg8_rex 0416 14
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r14w REG16 reg16 0426 14
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r14d REG32 reg32 0436 14
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r14 REG64 reg64 0456 14
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r15b REG8 reg8_rex 0417 15
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r15w REG16 reg16 0427 15
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r15d REG32 reg32 0437 15
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r15 REG64 reg64 0457 15
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# Segment registers
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cs REG_CS sreg 0101
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ds REG_DESS sreg 0103
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es REG_DESS sreg 0100
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ss REG_DESS sreg 0102
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fs REG_FSGS sreg 0104
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gs REG_FSGS sreg 0105
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segr6 REG_SEG67 sreg 0106
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segr7 REG_SEG67 sreg 0107
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cs REG_CS sreg 0101 1
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ds REG_DESS sreg 0103 3
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es REG_DESS sreg 0100 0
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ss REG_DESS sreg 0102 2
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fs REG_FSGS sreg 0104 4
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gs REG_FSGS sreg 0105 5
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segr6 REG_SEG67 sreg 0106 6
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segr7 REG_SEG67 sreg 0107 7
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# Control registers
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cr0 REG_CREG creg 0110
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cr1 REG_CREG creg 0111
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cr2 REG_CREG creg 0112
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cr3 REG_CREG creg 0113
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cr4 REG_CREG creg 0114
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cr5 REG_CREG creg 0115
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cr6 REG_CREG creg 0116
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cr7 REG_CREG creg 0117
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cr8 REG_C8REG creg 0120
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cr9 REG_CREG creg 0121
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cr10 REG_CREG creg 0122
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cr11 REG_CREG creg 0123
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cr12 REG_CREG creg 0124
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cr13 REG_CREG creg 0125
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cr14 REG_CREG creg 0126
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cr15 REG_CREG creg 0127
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cr0* REG_CREG creg 0110 0
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cr8* REG_CREG creg 0120 8
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# Debug registers
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dr0 REG_DREG dreg 0130
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dr1 REG_DREG dreg 0131
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dr2 REG_DREG dreg 0132
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dr3 REG_DREG dreg 0133
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dr4 REG_DREG dreg 0134
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dr5 REG_DREG dreg 0135
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dr6 REG_DREG dreg 0136
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dr7 REG_DREG dreg 0137
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dr8 REG_DREG dreg 0140
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dr9 REG_DREG dreg 0141
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dr10 REG_DREG dreg 0142
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dr11 REG_DREG dreg 0143
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dr12 REG_DREG dreg 0144
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dr13 REG_DREG dreg 0145
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dr14 REG_DREG dreg 0146
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dr15 REG_DREG dreg 0147
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dr0* REG_DREG dreg 0130 0
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dr8* REG_DREG dreg 0140 8
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# Test registers
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tr0 REG_TREG treg 0150
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tr1 REG_TREG treg 0151
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tr2 REG_TREG treg 0152
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tr3 REG_TREG treg 0153
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tr4 REG_TREG treg 0154
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tr5 REG_TREG treg 0155
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tr6 REG_TREG treg 0156
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tr7 REG_TREG treg 0157
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tr0* REG_TREG treg 0150 0
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# Floating-point registers
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st0 FPU0 fpureg 0200
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st1 FPUREG fpureg 0201
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st2 FPUREG fpureg 0202
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st3 FPUREG fpureg 0203
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st4 FPUREG fpureg 0204
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st5 FPUREG fpureg 0205
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st6 FPUREG fpureg 0206
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st7 FPUREG fpureg 0207
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st0 FPU0 fpureg 0200 0
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st1 FPUREG fpureg 0201 1
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st2 FPUREG fpureg 0202 2
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st3 FPUREG fpureg 0203 3
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st4 FPUREG fpureg 0204 4
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st5 FPUREG fpureg 0205 5
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st6 FPUREG fpureg 0206 6
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st7 FPUREG fpureg 0207 7
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# MMX registers
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mm0 MMXREG mmxreg 0220
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mm1 MMXREG mmxreg 0221
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mm2 MMXREG mmxreg 0222
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mm3 MMXREG mmxreg 0223
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mm4 MMXREG mmxreg 0224
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mm5 MMXREG mmxreg 0225
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mm6 MMXREG mmxreg 0226
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mm7 MMXREG mmxreg 0227
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mm0* MMXREG mmxreg 0220 0
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# SSE registers
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xmm0 XMMREG xmmreg 0240
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xmm1 XMMREG xmmreg 0241
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xmm2 XMMREG xmmreg 0242
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xmm3 XMMREG xmmreg 0243
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xmm4 XMMREG xmmreg 0244
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xmm5 XMMREG xmmreg 0245
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xmm6 XMMREG xmmreg 0246
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xmm7 XMMREG xmmreg 0247
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xmm8 XMMREG xmmreg 0460
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xmm9 XMMREG xmmreg 0461
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xmm10 XMMREG xmmreg 0462
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xmm11 XMMREG xmmreg 0463
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xmm12 XMMREG xmmreg 0464
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xmm13 XMMREG xmmreg 0465
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xmm14 XMMREG xmmreg 0466
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xmm15 XMMREG xmmreg 0467
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xmm0* XMMREG xmmreg 0240 0
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xmm8* XMMREG xmmreg 0460 8
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# Special registers
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rip REG_RIP ripreg 0500
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rip REG_RIP ripreg 0500
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60
regs.pl
60
regs.pl
@ -6,26 +6,51 @@
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$nline = 0;
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sub toint($) {
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my($v) = @_;
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return ($v =~ /^0/) ? oct $v : $v+0;
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}
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sub process_line($) {
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my($line) = @_;
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my @v;
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if ( $line !~ /^\s*(\S+)\s*(\S+)\s*(\S+)\s*([0-9]+)\s*$/ ) {
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if ( $line !~ /^\s*(\S+)\s*(\S+)\s*(\S+)\s*([1-9][0-9]+|0[0-7]+|0x[0-9a-f]+)\s*([0-9]+)$/i ) {
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die "regs.dat:$nline: invalid input\n";
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}
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$reg = $1;
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$aclass = $2;
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$dclass = $3;
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$regval = $4;
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$reg = $1;
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$aclass = $2;
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$dclasses = $3;
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$regval = toint($4);
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$x86regno = toint($5);
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$regs{$reg} = $aclass;
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$regvals{$reg} = $regval;
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if ( !defined($disclass{$dclass}) ) {
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$disclass{$dclass} = [(undef) x 8];
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if ($reg =~ /\*$/) {
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$nregs = 8;
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$reg =~ s/\*$//;
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} else {
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$nregs = 1;
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}
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$disclass{$dclass}->[$regval] = $reg;
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while ($nregs--) {
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$regs{$reg} = $aclass;
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$regvals{$reg} = $regval;
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foreach $dclass (split(/,/, $dclasses)) {
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if ( !defined($disclass{$dclass}) ) {
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$disclass{$dclass} = [];
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}
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$disclass{$dclass}->[$x86regno] = $reg;
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}
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# Compute the next register, if any
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$regval++;
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$x86regno++;
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if ($reg =~ /^(|.*[^0-9])([0-9]+)$/) {
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$reg = sprintf("%s%u", $1, $2+1);
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}
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}
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}
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($fmt, $file) = @ARGV;
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@ -42,14 +67,7 @@ while ( defined($line = <REGS>) ) {
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next if ( $line eq '' );
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if ( $line =~ /\*/ ) {
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for ( $i = 0 ; $i < 8 ; $i++ ) {
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($xline = $line) =~ s/\*/$i/g;
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process_line($xline);
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}
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} else {
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process_line($line);
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}
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process_line($line);
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}
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close(REGS);
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@ -93,7 +111,7 @@ if ( $fmt eq 'h' ) {
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print "static const int regvals[] = {\n";
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print " -1"; # Dummy entry for 0
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foreach $reg ( sort(keys(%regs)) ) {
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print ",\n ", $regvals{$reg}; # Print the regval of the register
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printf ",\n 0%03o", $regvals{$reg}; # Print the regval of the register
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}
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print "\n};\n";
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} elsif ( $fmt eq 'dc' ) {
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@ -106,6 +124,8 @@ if ( $fmt eq 'h' ) {
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for ( $i = 0 ; $i < scalar(@foo) ; $i++ ) {
|
||||
if (defined($foo[$i])) {
|
||||
push(@bar, "R_\U$foo[$i]\E");
|
||||
} else {
|
||||
die "$0: No register name for class $class, value $i\n";
|
||||
}
|
||||
}
|
||||
print join(',', @bar), "};\n";
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user