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Implement the VGATHERP instruction

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As an initial test of the VSIB handling, implement the VGATHERP
instruction.

Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
This commit is contained in:
H. Peter Anvin 2011-06-22 18:20:28 -07:00
parent 3089f7ef8a
commit 95adeabff5
2 changed files with 81 additions and 0 deletions
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5
insns.dat
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@ -3117,6 +3117,11 @@ VPSHLQ xmmreg,xmmreg*,xmmrm128 [rvm: xop.m9.w1.nds.l0.p0 97 /r] AMD,SSE5
VPSHLW xmmreg,xmmrm128*,xmmreg [rmv: xop.m9.w0.nds.l0.p0 95 /r] AMD,SSE5
VPSHLW xmmreg,xmmreg*,xmmrm128 [rvm: xop.m9.w1.nds.l0.p0 95 /r] AMD,SSE5
;# AVX2
VGATHERDPD xmmreg,mem32,xmmreg [rmv: vm32x vex.dds.128.66.0f38.w1 92 /r] FUTURE,AVX
VGATHERQPD xmmreg,mem64,xmmreg [rmv: vm64x vex.dds.128.66.0f38.w1 93 /r] FUTURE,AVX
VGATHERDPD ymmreg,mem32,ymmreg [rmv: vm32x vex.dds.256.66.0f38.w1 92 /r] FUTURE,AVX
VGATHERQPD ymmreg,mem64,ymmreg [rmv: vm64y vex.dds.256.66.0f38.w1 92 /r] FUTURE,AVX
;# Systematic names for the hinting nop instructions
; These should be last in the file

76
test/vgather.asm Normal file
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@ -0,0 +1,76 @@
bits 64
vgatherdpd xmm0,[rcx+xmm2],xmm3
vgatherqpd xmm0,[rcx+xmm2],xmm3
vgatherdpd ymm0,[rcx+xmm2],ymm3
vgatherqpd ymm0,[rcx+ymm2],ymm3
vgatherdpd xmm0,[rcx+xmm2*1],xmm3
vgatherqpd xmm0,[rcx+xmm2*1],xmm3
vgatherdpd ymm0,[rcx+xmm2*1],ymm3
vgatherqpd ymm0,[rcx+ymm2*1],ymm3
vgatherdpd xmm0,[rcx+xmm2*2],xmm3
vgatherqpd xmm0,[rcx+xmm2*2],xmm3
vgatherdpd ymm0,[rcx+xmm2*2],ymm3
vgatherqpd ymm0,[rcx+ymm2*2],ymm3
vgatherdpd xmm0,[rcx+xmm2*4],xmm3
vgatherqpd xmm0,[rcx+xmm2*4],xmm3
vgatherdpd ymm0,[rcx+xmm2*4],ymm3
vgatherqpd ymm0,[rcx+ymm2*4],ymm3
vgatherdpd xmm0,[rcx+xmm2*8],xmm3
vgatherqpd xmm0,[rcx+xmm2*8],xmm3
vgatherdpd ymm0,[rcx+xmm2*8],ymm3
vgatherqpd ymm0,[rcx+ymm2*8],ymm3
vgatherdpd xmm0,[xmm2],xmm3
vgatherqpd xmm0,[xmm2],xmm3
vgatherdpd ymm0,[xmm2],ymm3
vgatherqpd ymm0,[ymm2],ymm3
vgatherdpd xmm0,[xmm2*1],xmm3
vgatherqpd xmm0,[xmm2*1],xmm3
vgatherdpd ymm0,[xmm2*1],ymm3
vgatherqpd ymm0,[ymm2*1],ymm3
vgatherdpd xmm0,[xmm2*2],xmm3
vgatherqpd xmm0,[xmm2*2],xmm3
vgatherdpd ymm0,[xmm2*2],ymm3
vgatherqpd ymm0,[ymm2*2],ymm3
vgatherdpd xmm0,[xmm2*4],xmm3
vgatherqpd xmm0,[xmm2*4],xmm3
vgatherdpd ymm0,[xmm2*4],ymm3
vgatherqpd ymm0,[ymm2*4],ymm3
vgatherdpd xmm0,[xmm2*8],xmm3
vgatherqpd xmm0,[xmm2*8],xmm3
vgatherdpd ymm0,[xmm2*8],ymm3
vgatherqpd ymm0,[ymm2*8],ymm3
vgatherdpd xmm0,[xmm2+rcx],xmm3
vgatherqpd xmm0,[xmm2+rcx],xmm3
vgatherdpd ymm0,[xmm2+rcx],ymm3
vgatherqpd ymm0,[ymm2+rcx],ymm3
vgatherdpd xmm0,[xmm2*1+rcx],xmm3
vgatherqpd xmm0,[xmm2*1+rcx],xmm3
vgatherdpd ymm0,[xmm2*1+rcx],ymm3
vgatherqpd ymm0,[ymm2*1+rcx],ymm3
vgatherdpd xmm0,[xmm2*2+rcx],xmm3
vgatherqpd xmm0,[xmm2*2+rcx],xmm3
vgatherdpd ymm0,[xmm2*2+rcx],ymm3
vgatherqpd ymm0,[ymm2*2+rcx],ymm3
vgatherdpd xmm0,[xmm2*4+rcx],xmm3
vgatherqpd xmm0,[xmm2*4+rcx],xmm3
vgatherdpd ymm0,[xmm2*4+rcx],ymm3
vgatherqpd ymm0,[ymm2*4+rcx],ymm3
vgatherdpd xmm0,[xmm2*8+rcx],xmm3
vgatherqpd xmm0,[xmm2*8+rcx],xmm3
vgatherdpd ymm0,[xmm2*8+rcx],ymm3
vgatherqpd ymm0,[ymm2*8+rcx],ymm3