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AVX-512: Add {evex} instruction prefix

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For instructions that can be encoded either in VEX or EVEX,
{evex} forces nasm to encode in EVEX.

Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
This commit is contained in:
Jin Kyu Song 2013-10-25 19:29:53 -07:00
parent 267d0af79c
commit 945b1b8f36
4 changed files with 14 additions and 0 deletions
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7
assemble.c
View File

@ -632,6 +632,9 @@ int64_t assemble(int32_t segment, int64_t offset, int bits, iflags_t cp,
case P_OSP:
c = 0x66;
break;
case P_EVEX:
/* EVEX */
break;
case P_none:
break;
default:
@ -786,6 +789,7 @@ int64_t insn_size(int32_t segment, int64_t offset, int bits, iflags_t cp,
break;
case P_A64:
case P_O64:
case P_EVEX:
case P_none:
break;
default:
@ -2186,6 +2190,9 @@ static enum match_result matches(const struct itemplate *itemp,
nasm_regvals[instruction->oprs[i].basereg] >= 16 &&
!(itemp->flags & IF_AVX512)) {
return MERR_ENCMISMATCH;
} else if (instruction->prefixes[PPS_EVEX] &&
!(itemp->flags & IF_AVX512)) {
return MERR_ENCMISMATCH;
}
}

2
nasm.h
View File

@ -553,6 +553,7 @@ enum prefixes { /* instruction prefixes */
P_XACQUIRE,
P_XRELEASE,
P_BND,
P_EVEX,
PREFIX_ENUM_LIMIT
};
@ -635,6 +636,7 @@ enum prefix_pos {
PPS_SEG, /* Segment override prefix */
PPS_OSIZE, /* Operand size prefix */
PPS_ASIZE, /* Address size prefix */
PPS_EVEX, /* EVEX prefix */
MAXPREFIX /* Total number of prefix slots */
};

2
parser.c
View File

@ -101,6 +101,8 @@ static int prefix_slot(int prefix)
case P_A64:
case P_ASP:
return PPS_ASIZE;
case P_EVEX:
return PPS_EVEX;
default:
nasm_error(ERR_PANIC, "Invalid value %d passed to prefix_slot()", prefix);
return -1;

3
tokens.dat
View File

@ -122,3 +122,6 @@ rz-sae
% TOKEN_DECORATOR, 0, TFLAG_BRC, BRC_*
sae
z
% TOKEN_PREFIX, 0, TFLAG_BRC, P_*
evex