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insns.dat: accept explicit ax/eax/rax operand to CLZERO

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AMD documents this instruction with an rax operand. The error behavior
implies this is an address-size-sensitive instruction. Add support for
specifying the explicit operand, but consistent with normal ndisasm
behavior, don't disassemble the implicit operand.

Signed-off-by: H. Peter Anvin <hpa@zytor.com>
This commit is contained in:
H. Peter Anvin 2018-12-22 17:50:26 -08:00
parent e7f4e0e229
commit 7f688841ce
2 changed files with 29 additions and 0 deletions
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26
test/clzero.asm Normal file
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@ -0,0 +1,26 @@
bits 16
clzero
clzero ax
clzero eax
%ifdef ERROR
clzero rax
%endif
bits 32
clzero
clzero ax
clzero eax
%ifdef ERROR
clzero rax
%endif
bits 64
clzero
%ifdef ERROR
clzero ax
%endif
clzero eax
clzero rax

3
x86/insns.dat
View File

@ -5196,6 +5196,9 @@ PCOMMIT void [ 66 0f ae f8]
; AMD Zen v1
CLZERO void [ 0f 01 fc] FUTURE,AMD
CLZERO reg_ax [-: a16 0f 01 fc] FUTURE,AMD,ND,NOLONG
CLZERO reg_eax [-: a32 0f 01 fc] FUTURE,AMD,ND
CLZERO reg_rax [-: a64 0f 01 fc] FUTURE,AMD,ND,X64
;# Processor trace write
PTWRITE rm32 [m: np 0f ae /4] FUTURE