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https://github.com/netwide-assembler/nasm.git
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BR 993895: Support zero-operand floating-point insn
Support the zero-operand form of floating-point instructions. Note that in most cases, the form generated is actually the "popping" form, e.g. "FADD" becomes "FADDP st0,st1". This is in accordance with the Intel documentation. "FADDP" is also supported.
This commit is contained in:
H. Peter Anvin
parent
428fd671ec
commit
7812644665
39
insns.dat
39
insns.dat
@ -313,8 +313,10 @@ FADD fpureg|to \1\xDC\10\xC0 8086,FPU
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FADD fpureg \1\xD8\10\xC0 8086,FPU
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FADD fpureg,fpu0 \1\xDC\10\xC0 8086,FPU
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FADD fpu0,fpureg \1\xD8\11\xC0 8086,FPU
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FADD void \2\xDE\xC1 8086,FPU,ND
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FADDP fpureg \1\xDE\10\xC0 8086,FPU
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FADDP fpureg,fpu0 \1\xDE\10\xC0 8086,FPU
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FADDP void \2\xDE\xC1 8086,FPU,ND
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FBLD mem80 \1\xDF\204 8086,FPU
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FBLD mem \1\xDF\204 8086,FPU
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FBSTP mem80 \1\xDF\206 8086,FPU
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@ -323,32 +325,44 @@ FCHS void \2\xD9\xE0 8086,FPU
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FCLEX void \3\x9B\xDB\xE2 8086,FPU
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FCMOVB fpureg \1\xDA\10\xC0 P6,FPU
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FCMOVB fpu0,fpureg \1\xDA\11\xC0 P6,FPU
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FCMOVB void \2\xDA\xC1 P6,FPU,ND
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FCMOVBE fpureg \1\xDA\10\xD0 P6,FPU
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FCMOVBE fpu0,fpureg \1\xDA\11\xD0 P6,FPU
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FCMOVBE void \2\xDA\xD1 P6,FPU,ND
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FCMOVE fpureg \1\xDA\10\xC8 P6,FPU
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FCMOVE fpu0,fpureg \1\xDA\11\xC8 P6,FPU
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FCMOVE void \2\xDA\xC9 P6,FPU,ND
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FCMOVNB fpureg \1\xDB\10\xC0 P6,FPU
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FCMOVNB fpu0,fpureg \1\xDB\11\xC0 P6,FPU
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FCMOVNB void \2\xDB\xC1 P6,FPU,ND
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FCMOVNBE fpureg \1\xDB\10\xD0 P6,FPU
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FCMOVNBE fpu0,fpureg \1\xDB\11\xD0 P6,FPU
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FCMOVNBE void \2\xDB\xD1 P6,FPU,ND
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FCMOVNE fpureg \1\xDB\10\xC8 P6,FPU
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FCMOVNE fpu0,fpureg \1\xDB\11\xC8 P6,FPU
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FCMOVNE void \2\xDB\xC9 P6,FPU,ND
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FCMOVNU fpureg \1\xDB\10\xD8 P6,FPU
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FCMOVNU fpu0,fpureg \1\xDB\11\xD8 P6,FPU
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FCMOVNU void \2\xDB\xD9 P6,FPU,ND
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FCMOVU fpureg \1\xDA\10\xD8 P6,FPU
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FCMOVU fpu0,fpureg \1\xDA\11\xD8 P6,FPU
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FCMOVU void \2\xDA\xD9 P6,FPU,ND
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FCOM mem32 \1\xD8\202 8086,FPU
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FCOM mem64 \1\xDC\202 8086,FPU
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FCOM fpureg \1\xD8\10\xD0 8086,FPU
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FCOM fpu0,fpureg \1\xD8\11\xD0 8086,FPU
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FCOM void \2\xD8\xD1 8086,FPU,ND
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FCOMI fpureg \1\xDB\10\xF0 P6,FPU
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FCOMI fpu0,fpureg \1\xDB\11\xF0 P6,FPU
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FCOMI void \2\xDB\xF1 P6,FPU,ND
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FCOMIP fpureg \1\xDF\10\xF0 P6,FPU
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FCOMIP fpu0,fpureg \1\xDF\11\xF0 P6,FPU
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FCOMIP void \2\xDF\xF1 P6,FPU,ND
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FCOMP mem32 \1\xD8\203 8086,FPU
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FCOMP mem64 \1\xDC\203 8086,FPU
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FCOMP fpureg \1\xD8\10\xD8 8086,FPU
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FCOMP fpu0,fpureg \1\xD8\11\xD8 8086,FPU
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FCOMP void \2\xD8\xD9 8086,FPU,ND
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FCOMPP void \2\xDE\xD9 8086,FPU
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FCOS void \2\xD9\xFF 386,FPU
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FDECSTP void \2\xD9\xF6 8086,FPU
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@ -356,23 +370,29 @@ FDISI void \3\x9B\xDB\xE1 8086,FPU
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FDIV mem32 \1\xD8\206 8086,FPU
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FDIV mem64 \1\xDC\206 8086,FPU
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FDIV fpureg|to \1\xDC\10\xF8 8086,FPU
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FDIV fpureg,fpu0 \1\xDC\10\xF8 8086,FPU
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FDIV fpureg \1\xD8\10\xF0 8086,FPU
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FDIV fpureg,fpu0 \1\xDC\10\xF8 8086,FPU
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FDIV fpu0,fpureg \1\xD8\11\xF0 8086,FPU
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FDIVP fpureg,fpu0 \1\xDE\10\xF8 8086,FPU
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FDIV void \2\xDE\xF9 8086,FPU,ND
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FDIVP fpureg \1\xDE\10\xF8 8086,FPU
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FDIVP fpureg,fpu0 \1\xDE\10\xF8 8086,FPU
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FDIVP void \2\xDE\xF9 8086,FPU,ND
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FDIVR mem32 \1\xD8\207 8086,FPU
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FDIVR mem64 \1\xDC\207 8086,FPU
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FDIVR fpureg|to \1\xDC\10\xF0 8086,FPU
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FDIVR fpureg,fpu0 \1\xDC\10\xF0 8086,FPU
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FDIVR fpureg \1\xD8\10\xF8 8086,FPU
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FDIVR fpu0,fpureg \1\xD8\11\xF8 8086,FPU
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FDIVR void \2\xDE\xF1 8086,FPU,ND
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FDIVRP fpureg \1\xDE\10\xF0 8086,FPU
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FDIVRP fpureg,fpu0 \1\xDE\10\xF0 8086,FPU
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FDIVRP void \2\xDE\xF1 8086,FPU,ND
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FEMMS void \2\x0F\x0E PENT,3DNOW
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FENI void \3\x9B\xDB\xE0 8086,FPU
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FFREE fpureg \1\xDD\10\xC0 8086,FPU
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FFREE void \2\xDD\xC1 8086,FPU
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FFREEP fpureg \1\xDF\10\xC0 286,FPU,UNDOC
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FFREEP void \2\xDF\xC1 286,FPU,UNDOC
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FIADD mem32 \1\xDA\200 8086,FPU
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FIADD mem16 \1\xDE\200 8086,FPU
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FICOM mem32 \1\xDA\202 8086,FPU
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@ -406,6 +426,7 @@ FLD mem32 \1\xD9\200 8086,FPU
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FLD mem64 \1\xDD\200 8086,FPU
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FLD mem80 \1\xDB\205 8086,FPU
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FLD fpureg \1\xD9\10\xC0 8086,FPU
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FLD void \2\xD9\xC1 8086,FPU,ND
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FLD1 void \2\xD9\xE8 8086,FPU
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FLDCW mem \1\xD9\205 8086,FPU,SW
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FLDENV mem \1\xD9\204 8086,FPU
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@ -421,8 +442,10 @@ FMUL fpureg|to \1\xDC\10\xC8 8086,FPU
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FMUL fpureg,fpu0 \1\xDC\10\xC8 8086,FPU
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FMUL fpureg \1\xD8\10\xC8 8086,FPU
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FMUL fpu0,fpureg \1\xD8\11\xC8 8086,FPU
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FMUL void \2\xDE\xC9 8086,FPU,ND
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FMULP fpureg \1\xDE\10\xC8 8086,FPU
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FMULP fpureg,fpu0 \1\xDE\10\xC8 8086,FPU
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FMULP void \2\xDE\xC9 8086,FPU,ND
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FNCLEX void \2\xDB\xE2 8086,FPU
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FNDISI void \2\xDB\xE1 8086,FPU
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FNENI void \2\xDB\xE0 8086,FPU
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@ -448,12 +471,14 @@ FSQRT void \2\xD9\xFA 8086,FPU
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FST mem32 \1\xD9\202 8086,FPU
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FST mem64 \1\xDD\202 8086,FPU
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FST fpureg \1\xDD\10\xD0 8086,FPU
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FST void \2\xDD\xD1 8086,FPU,ND
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FSTCW mem \2\x9B\xD9\207 8086,FPU,SW
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FSTENV mem \2\x9B\xD9\206 8086,FPU
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FSTP mem32 \1\xD9\203 8086,FPU
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FSTP mem64 \1\xDD\203 8086,FPU
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FSTP mem80 \1\xDB\207 8086,FPU
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FSTP fpureg \1\xDD\10\xD8 8086,FPU
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FSTP void \2\xDD\xD9 8086,FPU,ND
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FSTSW mem \2\x9B\xDD\207 8086,FPU,SW
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FSTSW reg_ax \3\x9B\xDF\xE0 286,FPU
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FSUB mem32 \1\xD8\204 8086,FPU
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@ -462,31 +487,39 @@ FSUB fpureg|to \1\xDC\10\xE8 8086,FPU
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FSUB fpureg,fpu0 \1\xDC\10\xE8 8086,FPU
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FSUB fpureg \1\xD8\10\xE0 8086,FPU
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FSUB fpu0,fpureg \1\xD8\11\xE0 8086,FPU
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FSUB void \2\xDE\xE9 8086,FPU,ND
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FSUBP fpureg \1\xDE\10\xE8 8086,FPU
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FSUBP fpureg,fpu0 \1\xDE\10\xE8 8086,FPU
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FSUBP void \2\xDE\xE9 8086,FPU,ND
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FSUBR mem32 \1\xD8\205 8086,FPU
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FSUBR mem64 \1\xDC\205 8086,FPU
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FSUBR fpureg|to \1\xDC\10\xE0 8086,FPU
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FSUBR fpureg,fpu0 \1\xDC\10\xE0 8086,FPU
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FSUBR fpureg \1\xD8\10\xE8 8086,FPU
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FSUBR fpu0,fpureg \1\xD8\11\xE8 8086,FPU
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FSUBR void \2\xDE\xE1 8086,FPU,ND
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FSUBRP fpureg \1\xDE\10\xE0 8086,FPU
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FSUBRP fpureg,fpu0 \1\xDE\10\xE0 8086,FPU
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FSUBRP void \2\xDE\xE1 8086,FPU,ND
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FTST void \2\xD9\xE4 8086,FPU
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FUCOM fpureg \1\xDD\10\xE0 386,FPU
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FUCOM fpu0,fpureg \1\xDD\11\xE0 386,FPU
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FUCOM void \2\xDD\xE1 386,FPU,ND
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FUCOMI fpureg \1\xDB\10\xE8 P6,FPU
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FUCOMI fpu0,fpureg \1\xDB\11\xE8 P6,FPU
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FUCOMI void \2\xDB\xE9 P6,FPU,ND
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FUCOMIP fpureg \1\xDF\10\xE8 P6,FPU
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FUCOMIP fpu0,fpureg \1\xDF\11\xE8 P6,FPU
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FUCOMIP void \2\xDF\xE9 P6,FPU,ND
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FUCOMP fpureg \1\xDD\10\xE8 386,FPU
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FUCOMP fpu0,fpureg \1\xDD\11\xE8 386,FPU
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FUCOMP void \2\xDD\xE9 386,FPU,ND
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FUCOMPP void \2\xDA\xE9 386,FPU
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FXAM void \2\xD9\xE5 8086,FPU
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FXCH void \2\xD9\xC9 8086,FPU
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FXCH fpureg \1\xD9\10\xC8 8086,FPU
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FXCH fpureg,fpu0 \1\xD9\10\xC8 8086,FPU
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FXCH fpu0,fpureg \1\xD9\11\xC8 8086,FPU
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FXCH void \2\xD9\xC9 8086,FPU,ND
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FXTRACT void \2\xD9\xF4 8086,FPU
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FYL2X void \2\xD9\xF1 8086,FPU
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FYL2XP1 void \2\xD9\xF9 8086,FPU
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125
test/fpu.asm
Normal file
125
test/fpu.asm
Normal file
@ -0,0 +1,125 @@
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; relaxed encodings for FPU instructions, which NASM should support
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; -----------------------------------------------------------------
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%define void
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%define reg_fpu0 st0
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%define reg_fpu st1
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; no operands instead of one operand:
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; F(U)COM(P), FCOM2, FCOMP3, FCOMP5
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FCOM void
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FCOMP void
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FUCOM void
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FUCOMP void
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; FCOM2 void
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; FCOMP3 void
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; FCOMP5 void
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; FLD, FST, FSTP, FSTP1, FSTP8, FSTP9
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FLD void
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FST void
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FSTP void
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; FSTP1 void
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; FSTP8 void
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; FSTP9 void
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; FXCH, FXCH4, FXCH7, FFREE, FFREEP
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FXCH void
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; FXCH4 void
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; FXCH7 void
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FFREE void
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FFREEP void
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; no operands instead of two operands:
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; FADD(P), FMUL(P), FSUBR(P), FSUB(P), FDIVR(P), FDIV(P)
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FADD void
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FADDP void
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FMUL void
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FMULP void
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FSUBR void
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FSUBRP void
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FSUB void
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FSUBP void
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FDIVR void
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FDIVRP void
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FDIV void
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FDIVP void
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; one operand instead of two operands:
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; FADD, FMUL, FSUB, FSUBR, FDIV, FDIVR
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FADD reg_fpu
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FMUL reg_fpu
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FSUB reg_fpu
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FSUBR reg_fpu
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FDIV reg_fpu
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FDIVR reg_fpu
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; FADD, FMUL, FSUBR, FSUB, FDIVR, FDIV (with TO qualifier)
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FADD to reg_fpu
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FMUL to reg_fpu
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FSUBR to reg_fpu
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FSUB to reg_fpu
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FDIVR to reg_fpu
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FDIV to reg_fpu
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; FADDP, FMULP, FSUBRP, FSUBP, FDIVRP, FDIVP
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FADDP reg_fpu
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FMULP reg_fpu
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FSUBRP reg_fpu
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FSUBP reg_fpu
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FDIVRP reg_fpu
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FDIVP reg_fpu
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; FCMOV(N)B, FCMOV(N)E, FCMOV(N)BE, FCMOV(N)U, and F(U)COMI(P)
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FCMOVB reg_fpu
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FCMOVNB reg_fpu
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FCMOVE reg_fpu
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FCMOVNE reg_fpu
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FCMOVBE reg_fpu
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FCMOVNBE reg_fpu
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FCMOVU reg_fpu
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FCMOVNU reg_fpu
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FCOMI reg_fpu
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FCOMIP reg_fpu
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FUCOMI reg_fpu
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FUCOMIP reg_fpu
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; two operands instead of one operand:
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; these don't really exist, and thus are _NOT_ supported:
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; FCOM reg_fpu,reg_fpu0
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; FCOM reg_fpu0,reg_fpu
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; FUCOM reg_fpu,reg_fpu0
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; FUCOM reg_fpu0,reg_fpu
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; FCOMP reg_fpu,reg_fpu0
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; FCOMP reg_fpu0,reg_fpu
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; FUCOMP reg_fpu,reg_fpu0
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; FUCOMP reg_fpu0,reg_fpu
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; FCOM2 reg_fpu,reg_fpu0
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; FCOM2 reg_fpu0,reg_fpu
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; FCOMP3 reg_fpu,reg_fpu0
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; FCOMP3 reg_fpu0,reg_fpu
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; FCOMP5 reg_fpu,reg_fpu0
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; FCOMP5 reg_fpu0,reg_fpu
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; FXCH reg_fpu,reg_fpu0
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; FXCH reg_fpu0,reg_fpu
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; FXCH4 reg_fpu,reg_fpu0
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; FXCH4 reg_fpu0,reg_fpu
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; FXCH7 reg_fpu,reg_fpu0
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; FXCH7 reg_fpu0,reg_fpu
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; EOF
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