mirror of
https://github.com/netwide-assembler/nasm.git
synced 2025-03-25 18:10:23 +08:00
Remove all remaining explicit bytecodes from insns.dat
Get rid of the last vestiges of the explicit byte codes in insns.dat. The only files that now depend on actual byte code numbers are insns.pl, assemble.c and disasm.c. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
This commit is contained in:
H. Peter Anvin
parent
8cc8a1d836
commit
755f5214b7
11
assemble.c
11
assemble.c
@ -127,8 +127,8 @@
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* \333 - REP prefix (0xF3 byte) used as opcode extension.
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* \334 - LOCK prefix used as REX.R (used in non-64-bit mode)
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* \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
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* \336 - force a REP(E) prefix (0xF2) even if not specified.
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* \337 - force a REPNE prefix (0xF3) even if not specified.
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* \336 - force a REP(E) prefix (0xF3) even if not specified.
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* \337 - force a REPNE prefix (0xF2) even if not specified.
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* \336-\337 are still listed as prefixes in the disassembler.
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* \340 - reserve <operand 0> bytes of uninitialized storage.
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* Operand 0 had better be a segmentless constant.
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@ -145,7 +145,7 @@
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* \365 - address-size prefix (0x67) not permitted
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* \366 - operand-size prefix (0x66) used as opcode extension
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* \367 - address-size prefix (0x67) used as opcode extension
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* \370,\371,\372 - match only if operand 0 meets byte jump criteria.
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* \370,\371 - match only if operand 0 meets byte jump criteria.
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* 370 is used for Jcc, 371 is used for JMP.
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* \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
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* used for conditional jump over longer jump
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@ -326,7 +326,7 @@ static bool jmp_match(int32_t segment, int64_t offset, int bits,
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const uint8_t *code = temp->code;
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uint8_t c = code[0];
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if ((c != 0370 && c != 0371) || (ins->oprs[0].type & STRICT))
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if (((c & ~1) != 0370) || (ins->oprs[0].type & STRICT))
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return false;
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if (!optimizing)
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return false;
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@ -1831,7 +1831,6 @@ static void gencode(int32_t segment, int64_t offset, int bits,
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case 0370:
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case 0371:
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case 0372:
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break;
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case 0373:
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@ -2250,7 +2249,7 @@ static enum match_result matches(const struct itemplate *itemp,
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/*
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* Check if special handling needed for Jumps
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*/
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if ((itemp->code[0] & 0374) == 0370)
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if ((itemp->code[0] & ~1) == 0370)
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return MOK_JUMP;
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return MOK_GOOD;
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82
insns.dat
82
insns.dat
@ -55,7 +55,7 @@ DQ ignore ignore ignore
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DT ignore ignore ignore
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DO ignore ignore ignore
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DY ignore ignore ignore
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RESB imm \340 8086
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RESB imm [ resb] 8086
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RESW ignore ignore ignore
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RESD ignore ignore ignore
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RESQ ignore ignore ignore
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@ -338,8 +338,8 @@ DIV rm64 [m: o64 f7 /6] X64
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DMINT void [ 0f 39] P6,CYRIX
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EMMS void [ 0f 77] PENT,MMX
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ENTER imm,imm [ij: c8 iw ib,u] 186
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EQU imm \0 8086
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EQU imm:imm \0 8086
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EQU imm ignore 8086
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EQU imm:imm ignore 8086
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F2XM1 void [ d9 f0] 8086,FPU
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FABS void [ d9 e1] 8086,FPU
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FADD mem32 [m: d8 /0] 8086,FPU
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@ -652,7 +652,7 @@ JCXZ imm [i: a16 e3 rel8] 8086,NOLONG
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JECXZ imm [i: a32 e3 rel8] 386
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JRCXZ imm [i: a64 e3 rel8] X64
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JMP imm|short [i: eb rel8] 8086
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JMP imm [i: \371 eb rel8] 8086,ND
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JMP imm [i: jmp8 eb rel8] 8086,ND
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JMP imm [i: odf e9 rel] 8086
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JMP imm|near [i: odf e9 rel] 8086,ND
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JMP imm|far [i: odf ea iwd seg] 8086,ND,NOLONG
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@ -730,23 +730,23 @@ LODSB void [ ac] 8086
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LODSD void [ o32 ad] 386
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LODSQ void [ o64 ad] X64
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LODSW void [ o16 ad] 8086
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LOOP imm [i: \312 e2 rel8] 8086
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LOOP imm [i: adf e2 rel8] 8086
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LOOP imm,reg_cx [i-: a16 e2 rel8] 8086,NOLONG
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LOOP imm,reg_ecx [i-: a32 e2 rel8] 386
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LOOP imm,reg_rcx [i-: a64 e2 rel8] X64
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LOOPE imm [i: \312 e1 rel8] 8086
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LOOPE imm [i: adf e1 rel8] 8086
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LOOPE imm,reg_cx [i-: a16 e1 rel8] 8086,NOLONG
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LOOPE imm,reg_ecx [i-: a32 e1 rel8] 386
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LOOPE imm,reg_rcx [i-: a64 e1 rel8] X64
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LOOPNE imm [i: \312 e0 rel8] 8086
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LOOPNE imm [i: adf e0 rel8] 8086
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LOOPNE imm,reg_cx [i-: a16 e0 rel8] 8086,NOLONG
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LOOPNE imm,reg_ecx [i-: a32 e0 rel8] 386
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LOOPNE imm,reg_rcx [i-: a64 e0 rel8] X64
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LOOPNZ imm [i: \312 e0 rel8] 8086
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LOOPNZ imm [i: adf e0 rel8] 8086
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LOOPNZ imm,reg_cx [i-: a16 e0 rel8] 8086,NOLONG
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LOOPNZ imm,reg_ecx [i-: a32 e0 rel8] 386
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LOOPNZ imm,reg_rcx [i-: a64 e0 rel8] X64
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LOOPZ imm [i: \312 e1 rel8] 8086
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LOOPZ imm [i: adf e1 rel8] 8086
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LOOPZ imm,reg_cx [i-: a16 e1 rel8] 8086,NOLONG
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LOOPZ imm,reg_ecx [i-: a32 e1 rel8] 386
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LOOPZ imm,reg_rcx [i-: a64 e1 rel8] X64
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@ -868,7 +868,7 @@ NEG rm8 [m: f6 /3] 8086
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NEG rm16 [m: o16 f7 /3] 8086
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NEG rm32 [m: o32 f7 /3] 386
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NEG rm64 [m: o64 f7 /3] X64
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NOP void [ \314 90] 8086
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NOP void [ norexb 90] 8086
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NOP rm16 [m: o16 0f 1f /0] P6
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NOP rm32 [m: o32 0f 1f /0] P6
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NOP rm64 [m: o64 0f 1f /0] X64
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@ -931,7 +931,7 @@ PADDUSW mmxreg,mmxrm [rm: np o64nw 0f dd /r] PENT,MMX,SQ
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PADDW mmxreg,mmxrm [rm: np o64nw 0f fd /r] PENT,MMX,SQ
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PAND mmxreg,mmxrm [rm: np o64nw 0f db /r] PENT,MMX,SQ
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PANDN mmxreg,mmxrm [rm: np o64nw 0f df /r] PENT,MMX,SQ
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PAUSE void [ \314 \333 90] 8086
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PAUSE void [ norexb f3i 90] 8086
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PAVEB mmxreg,mmxrm [rm: o64nw 0f 50 /r] PENT,MMX,SQ,CYRIX
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PAVGUSB mmxreg,mmxrm [rm: o64nw 0f 0f /r bf] PENT,3DNOW,SQ
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PCMPEQB mmxreg,mmxrm [rm: np o64nw 0f 74 /r] PENT,MMX,SQ
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@ -977,8 +977,8 @@ POP rm16 [m: o16 8f /0] 8086
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POP rm32 [m: o32 8f /0] 386,NOLONG
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POP rm64 [m: o64nw 8f /0] X64
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POP reg_cs [-: 0f] 8086,UNDOC,ND
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POP reg_dess [-: \345] 8086,NOLONG
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POP reg_fsgs [-: 0f \347] 386
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POP reg_dess [-: popseg] 8086,NOLONG
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POP reg_fsgs [-: 0f popseg2] 386
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POPA void [ odf 61] 186,NOLONG
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POPAD void [ o32 61] 386,NOLONG
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POPAW void [ o16 61] 186,NOLONG
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@ -1025,9 +1025,9 @@ PUSH reg64 [r: o64nw 50+r] X64
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PUSH rm16 [m: o16 ff /6] 8086
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PUSH rm32 [m: o32 ff /6] 386,NOLONG
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PUSH rm64 [m: o64nw ff /6] X64
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PUSH reg_cs [-: \344] 8086,NOLONG
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PUSH reg_dess [-: \344] 8086,NOLONG
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PUSH reg_fsgs [-: 0f \346] 386
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PUSH reg_cs [-: pushseg] 8086,NOLONG
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PUSH reg_dess [-: pushseg] 8086,NOLONG
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PUSH reg_fsgs [-: 0f pushseg2] 386
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PUSH imm8 [i: 6a ibx] 186
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PUSH imm16 [i: o16 68+s ibw] 186,AR0,SZ
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PUSH imm32 [i: o32 68+s ibd] 386,NOLONG,AR0,SZ
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@ -1421,9 +1421,9 @@ Jcc imm|near [i: odf 0f 80+c rel] 386
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Jcc imm16|near [i: o16 0f 80+c rel] 386
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Jcc imm32|near [i: o32 0f 80+c rel] 386
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Jcc imm|short [i: 70+c rel8] 8086,ND
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Jcc imm [i: \370 70+c rel8] 8086,ND
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Jcc imm [i: jcc8 70+c rel8] 8086,ND
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Jcc imm [i: 0f 80+c rel] 386,ND
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Jcc imm [i: 71+c \373 e9 rel] 8086,ND
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Jcc imm [i: 71+c jlen e9 rel] 8086,ND
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Jcc imm [i: 70+c rel8] 8086
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SETcc mem [m: 0f 90+c /0] 386,SB
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SETcc reg8 [m: 0f 90+c /0] 386
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@ -1575,10 +1575,10 @@ LFENCE void [ 0f ae e8] WILLAMETTE,SSE2
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MFENCE void [ 0f ae f0] WILLAMETTE,SSE2
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;# Willamette MMX instructions (SSE2 SIMD Integer Instructions)
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MOVD mem,xmmreg [mr: 66 \317 0f 7e /r] WILLAMETTE,SSE2,SD
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MOVD xmmreg,mem [rm: 66 \317 0f 6e /r] WILLAMETTE,SSE2,SD
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MOVD xmmreg,rm32 [rm: 66 \317 0f 6e /r] WILLAMETTE,SSE2
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MOVD rm32,xmmreg [mr: 66 \317 0f 7e /r] WILLAMETTE,SSE2
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MOVD mem,xmmreg [mr: 66 norexw 0f 7e /r] WILLAMETTE,SSE2,SD
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MOVD xmmreg,mem [rm: 66 norexw 0f 6e /r] WILLAMETTE,SSE2,SD
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MOVD xmmreg,rm32 [rm: 66 norexw 0f 6e /r] WILLAMETTE,SSE2
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MOVD rm32,xmmreg [mr: 66 norexw 0f 7e /r] WILLAMETTE,SSE2
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MOVDQA xmmreg,xmmreg [rm: 66 0f 6f /r] WILLAMETTE,SSE2
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MOVDQA mem,xmmreg [mr: 66 0f 7f /r] WILLAMETTE,SSE2,SO
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MOVDQA xmmreg,mem [rm: 66 0f 6f /r] WILLAMETTE,SSE2,SO
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@ -1845,9 +1845,9 @@ MOVNTSD mem,xmmreg [mr: f2 0f 2b /r] SSE4A,AMD,SQ
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MOVNTSS mem,xmmreg [mr: f3 0f 2b /r] SSE4A,AMD,SD
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;# New instructions in Barcelona
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LZCNT reg16,rm16 [rm: o16 \333 0f bd /r] P6,AMD
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LZCNT reg32,rm32 [rm: o32 \333 0f bd /r] P6,AMD
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LZCNT reg64,rm64 [rm: o64 \333 0f bd /r] X64,AMD
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LZCNT reg16,rm16 [rm: o16 f3i 0f bd /r] P6,AMD
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LZCNT reg32,rm32 [rm: o32 f3i 0f bd /r] P6,AMD
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LZCNT reg64,rm64 [rm: o64 f3i 0f bd /r] X64,AMD
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;# Penryn New Instructions (SSE4.1)
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BLENDPD xmmreg,xmmrm,imm [rmi: 66 0f 3a 0d /r ib,u] SSE41
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@ -1910,19 +1910,19 @@ ROUNDSD xmmreg,xmmrm,imm [rmi: 66 0f 3a 0b /r ib,u] SSE41
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ROUNDSS xmmreg,xmmrm,imm [rmi: 66 0f 3a 0a /r ib,u] SSE41
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;# Nehalem New Instructions (SSE4.2)
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CRC32 reg32,rm8 [rm: \332 0f 38 f0 /r] SSE42
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CRC32 reg32,rm16 [rm: o16 \332 0f 38 f1 /r] SSE42
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CRC32 reg32,rm32 [rm: o32 \332 0f 38 f1 /r] SSE42
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CRC32 reg64,rm8 [rm: o64 \332 0f 38 f0 /r] SSE42,X64
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CRC32 reg64,rm64 [rm: o64 \332 0f 38 f1 /r] SSE42,X64
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CRC32 reg32,rm8 [rm: f2i 0f 38 f0 /r] SSE42
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CRC32 reg32,rm16 [rm: o16 f2i 0f 38 f1 /r] SSE42
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CRC32 reg32,rm32 [rm: o32 f2i 0f 38 f1 /r] SSE42
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CRC32 reg64,rm8 [rm: o64 f2i 0f 38 f0 /r] SSE42,X64
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CRC32 reg64,rm64 [rm: o64 f2i 0f 38 f1 /r] SSE42,X64
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PCMPESTRI xmmreg,xmmrm,imm [rmi: 66 0f 3a 61 /r ib,u] SSE42
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PCMPESTRM xmmreg,xmmrm,imm [rmi: 66 0f 3a 60 /r ib,u] SSE42
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PCMPISTRI xmmreg,xmmrm,imm [rmi: 66 0f 3a 63 /r ib,u] SSE42
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PCMPISTRM xmmreg,xmmrm,imm [rmi: 66 0f 3a 62 /r ib,u] SSE42
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PCMPGTQ xmmreg,xmmrm [rm: 66 0f 38 37 /r] SSE42
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POPCNT reg16,rm16 [rm: o16 \333 0f b8 /r] NEHALEM,SW
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POPCNT reg32,rm32 [rm: o32 \333 0f b8 /r] NEHALEM,SD
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POPCNT reg64,rm64 [rm: o64 \333 0f b8 /r] NEHALEM,SQ,X64
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POPCNT reg16,rm16 [rm: o16 f3i 0f b8 /r] NEHALEM,SW
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POPCNT reg32,rm32 [rm: o32 f3i 0f b8 /r] NEHALEM,SD
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POPCNT reg64,rm64 [rm: o64 f3i 0f b8 /r] NEHALEM,SQ,X64
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;# Intel SMX
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GETSEC void [ 0f 37] KATMAI
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@ -2877,14 +2877,14 @@ VCVTPS2PH xmmrm64,xmmreg,imm8 [mri: vex.128.66.0f3a.w0 1d /r ib] AVX,FUTURE
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;# VIA (Centaur) security instructions
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XSTORE void [ 0f a7 c0] PENT,CYRIX
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XCRYPTECB void [ \336 0f a7 c8] PENT,CYRIX
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XCRYPTCBC void [ \336 0f a7 d0] PENT,CYRIX
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XCRYPTCTR void [ \336 0f a7 d8] PENT,CYRIX
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XCRYPTCFB void [ \336 0f a7 e0] PENT,CYRIX
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XCRYPTOFB void [ \336 0f a7 e8] PENT,CYRIX
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MONTMUL void [ \336 0f a6 c0] PENT,CYRIX
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XSHA1 void [ \336 0f a6 c8] PENT,CYRIX
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XSHA256 void [ \336 0f a6 d0] PENT,CYRIX
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XCRYPTECB void [ mustrep 0f a7 c8] PENT,CYRIX
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XCRYPTCBC void [ mustrep 0f a7 d0] PENT,CYRIX
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XCRYPTCTR void [ mustrep 0f a7 d8] PENT,CYRIX
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XCRYPTCFB void [ mustrep 0f a7 e0] PENT,CYRIX
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XCRYPTOFB void [ mustrep 0f a7 e8] PENT,CYRIX
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MONTMUL void [ mustrep 0f a6 c0] PENT,CYRIX
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XSHA1 void [ mustrep 0f a6 c8] PENT,CYRIX
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XSHA256 void [ mustrep 0f a6 d0] PENT,CYRIX
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;# AMD Lightweight Profiling (LWP) instructions
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;
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43
insns.pl
43
insns.pl
@ -527,18 +527,20 @@ sub decodify($$) {
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my $c = $codestr;
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my @codes = ();
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while ($c ne '') {
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if ($c =~ /^\\x([0-9a-f]+)(.*)$/i) {
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push(@codes, hex $1);
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$c = $2;
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next;
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} elsif ($c =~ /^\\([0-7]{1,3})(.*)$/) {
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push(@codes, oct $1);
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$c = $2;
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next;
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} else {
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die "$fname: unknown code format in \"$codestr\"\n";
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}
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unless ($codestr eq 'ignore') {
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while ($c ne '') {
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if ($c =~ /^\\x([0-9a-f]+)(.*)$/i) {
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push(@codes, hex $1);
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$c = $2;
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next;
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} elsif ($c =~ /^\\([0-7]{1,3})(.*)$/) {
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push(@codes, oct $1);
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$c = $2;
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next;
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} else {
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die "$fname: unknown code format in \"$codestr\"\n";
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}
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}
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}
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return @codes;
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@ -700,13 +702,30 @@ sub byte_code_compile($$) {
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'o64nw' => 0323, # Implied 64-bit operand size (no REX.W)
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'a16' => 0310,
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'a32' => 0311,
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'adf' => 0312, # Address size is default
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'a64' => 0313,
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'!osp' => 0364,
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'!asp' => 0365,
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'f2i' => 0332, # F2 prefix, but 66 for operand size is OK
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'f3i' => 0333, # F3 prefix, but 66 for operand size is OK
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'pushseg' => 0344,
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'popseg' => 0345,
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'pushseg2' => 0346,
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'popseg2' => 0347,
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'mustrep' => 0336,
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'mustrepne' => 0337,
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'rex.l' => 0334,
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'norexb' => 0314,
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'norexx' => 0315,
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'norexr' => 0316,
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'norexw' => 0317,
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'repe' => 0335,
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'nohi' => 0325, # Use spl/bpl/sil/dil even without REX
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'wait' => 0341, # Needs a wait prefix
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'resb' => 0340,
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'jcc8' => 0370, # Match only if Jcc possible with single byte
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'jmp8' => 0371, # Match only if JMP possible with single byte
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'jlen' => 0373, # Length of jump
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'nohle' => 0264,
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'hlexr' => 0265,
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'hlenl' => 0266,
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