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https://github.com/netwide-assembler/nasm.git
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Initial NDISASM support for AVX instructions/VEX prefixes
Initial NDISASM support for AVX instructions and VEX prefixes. It doesn't mean it's correct, but it seems to match my current understanding. It can disassemble *some*, but not *all*, of the AVX test cases (which are known to be at least partially incorrect...)
This commit is contained in:
H. Peter Anvin
parent
4d2c38ce75
commit
7334e3ac23
130
disasm.c
130
disasm.c
@ -49,7 +49,11 @@ struct prefix_info {
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uint8_t rep; /* Rep prefix present */
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uint8_t seg; /* Segment override prefix present */
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uint8_t lock; /* Lock prefix present */
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uint8_t rex; /* Rex prefix present */
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uint8_t vex[3]; /* VEX prefix present */
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uint8_t vex_m; /* VEX.M field */
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uint8_t vex_v;
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uint8_t vex_lp; /* VEX.LP fields */
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uint32_t rex; /* REX prefix present */
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};
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#define getu8(x) (*(uint8_t *)(x))
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@ -155,6 +159,8 @@ static enum reg_enum whichreg(int32_t regflags, int regval, int rex)
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return rd_mmxreg[regval & 7]; /* Ignore REX */
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if (!(XMMREG & ~regflags))
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return rd_xmmreg[regval];
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if (!(YMMREG & ~regflags))
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return rd_ymmreg[regval];
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return 0;
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}
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@ -672,6 +678,71 @@ static int matches(const struct itemplate *t, uint8_t *data,
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break;
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}
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case4(0260):
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{
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int vexm = *r++;
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int vexwlp = *r++;
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ins->rex |= REX_V;
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if ((prefix->rex & (REX_V|REX_D|REX_P)) != REX_V)
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return false;
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if ((vexm & 0x1f) != prefix->vex_m)
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return false;
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switch (vexwlp & 030) {
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case 000:
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if (prefix->rex & REX_W)
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return false;
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break;
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case 010:
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if (!(prefix->rex & REX_W))
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return false;
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break;
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default:
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break; /* XXX: Need to do anything special here? */
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}
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if ((vexwlp & 007) != prefix->vex_lp)
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return false;
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opx->segment |= SEG_RMREG;
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opx->basereg = prefix->vex_v;
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break;
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}
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case 0270:
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{
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int vexm = *r++;
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int vexwlp = *r++;
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ins->rex |= REX_V;
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if ((prefix->rex & (REX_V|REX_D|REX_P)) != REX_V)
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return false;
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if ((vexm & 0x1f) != prefix->vex_m)
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return false;
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switch (vexwlp & 030) {
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case 000:
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if (ins->rex & REX_W)
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return false;
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break;
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case 010:
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if (!(ins->rex & REX_W))
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return false;
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break;
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default:
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break; /* Need to do anything special here? */
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}
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if ((vexwlp & 007) != prefix->vex_lp)
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return false;
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if (prefix->vex_v != 0)
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return false;
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break;
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}
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case 0310:
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if (asize != 16)
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return false;
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@ -822,8 +893,8 @@ static int matches(const struct itemplate *t, uint8_t *data,
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}
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}
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/* REX cannot be combined with DREX */
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if ((ins->rex & REX_D) && (prefix->rex))
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/* REX cannot be combined with DREX or VEX */
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if ((ins->rex & (REX_D|REX_V)) && (prefix->rex & REX_P))
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return false;
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/*
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@ -904,7 +975,8 @@ int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize,
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segover = NULL;
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origdata = data;
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for (end_prefix = false; !end_prefix; ) {
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end_prefix = false;
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while (!end_prefix) {
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switch (*data) {
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case 0xF2:
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case 0xF3:
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@ -939,15 +1011,55 @@ int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize,
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prefix.asize = (segsize == 32) ? 16 : 32;
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prefix.asp = *data++;
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break;
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default:
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if (segsize == 64 && (*data & 0xf0) == REX_P) {
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case 0xC4:
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case 0xC5:
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if (segsize == 64 || (data[1] & 0xc0) == 0xc0) {
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prefix.vex[0] = *data++;
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prefix.vex[1] = *data++;
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if (prefix.vex[0] == 0xc4)
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prefix.vex[2] = *data++;
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}
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prefix.rex = REX_V;
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if (prefix.vex[0] == 0xc4) {
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prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
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prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
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prefix.vex_m = prefix.vex[1] & 0x1f;
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prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
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prefix.vex_lp = prefix.vex[2] & 7;
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} else {
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prefix.rex |= (~prefix.vex[1] >> (7-2)) & REX_R;
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prefix.vex_m = 1;
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prefix.vex_v = (~prefix.vex[1] >> 3) & 15;
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prefix.vex_lp = prefix.vex[1] & 7;
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}
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end_prefix = true;
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break;
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case REX_P + 0x0:
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case REX_P + 0x1:
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case REX_P + 0x2:
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case REX_P + 0x3:
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case REX_P + 0x4:
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case REX_P + 0x5:
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case REX_P + 0x6:
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case REX_P + 0x7:
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case REX_P + 0x8:
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case REX_P + 0x9:
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case REX_P + 0xA:
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case REX_P + 0xB:
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case REX_P + 0xC:
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case REX_P + 0xD:
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case REX_P + 0xE:
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case REX_P + 0xF:
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if (segsize == 64) {
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prefix.rex = *data++;
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if (prefix.rex & REX_W)
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prefix.osize = 64;
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end_prefix = true;
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} else {
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end_prefix = true;
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}
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end_prefix = true;
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break;
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default:
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end_prefix = true;
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break;
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}
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}
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5
insns.pl
5
insns.pl
@ -355,6 +355,11 @@ sub startseq($) {
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return addprefix($prefix, $c1..($c1+15));
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} elsif ($c0 == 0 || $c0 == 0340) {
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return $prefix;
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} elsif (($c0 & ~3) == 0260 || $c0 == 270) {
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shift(@codes);
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shift(@codes);
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} elsif ($c0 == 0172) {
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shift(@codes);
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} else {
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# We really need to be able to distinguish "forbidden"
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# and "ignorable" codes here
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@ -1,9 +1,14 @@
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bits 64
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vpermil2ps xmm0,xmm1,[rdi],xmm3,0
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times 16 nop
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vpermil2ps xmm0,xmm1,xmm2,[rdi],1
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times 16 nop
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vpermil2ps ymm0,ymm1,ymm2,ymm3,2
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times 16 nop
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vpermil2ps ymm0,ymm1,ymm2,[rdi],3
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times 16 nop
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vpermil2ps ymm0,ymm1,[rdi],ymm3,2
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times 16 nop
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vpermil2ps ymm0,ymm1,ymm2,[rdi],3
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times 16 nop
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