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Drop SAME_AS flag from instruction matcher
It was there to support the SSE5 DREX encoding, which as far as I know is dead forever. Signed-off-by: Ben Rudiak-Gould <benrudiak@gmail.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
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21
assemble.c
21
assemble.c
@ -1810,10 +1810,8 @@ static enum match_result find_match(const struct itemplate **tempp,
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/*
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* Missing operand size and a candidate for fuzzy matching...
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*/
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for (i = 0; i < temp->operands; i++) {
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if ((temp->opd[i] & SAME_AS) == 0)
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xsizeflags[i] |= temp->opd[i] & SIZE_MASK;
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}
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for (i = 0; i < temp->operands; i++)
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xsizeflags[i] |= temp->opd[i] & SIZE_MASK;
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opsizemissing = true;
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}
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if (m > merr)
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@ -1958,13 +1956,7 @@ static enum match_result matches(const struct itemplate *itemp,
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* guess it either from template (IF_S* flag) or
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* from code bits.
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*
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* 2) If template operand (i) has SAME_AS flag [used for registers only]
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* (ie the same operand as was specified somewhere in template, and
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* this referred operand index is being achieved via ~SAME_AS)
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* we are to be sure that both registers (in template and instruction)
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* do exactly match.
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*
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* 3) If template operand do not match the instruction OR
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* 2) If template operand do not match the instruction OR
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* template has an operand size specified AND this size differ
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* from which instruction has (perhaps we got it from code bits)
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* we are:
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@ -1980,12 +1972,7 @@ static enum match_result matches(const struct itemplate *itemp,
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if (!(type & SIZE_MASK))
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type |= size[i];
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if (itemp->opd[i] & SAME_AS) {
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int j = itemp->opd[i] & ~SAME_AS;
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if (type != instruction->oprs[j].type ||
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instruction->oprs[i].basereg != instruction->oprs[j].basereg)
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return MERR_INVALOP;
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} else if (itemp->opd[i] & ~type & ~SIZE_MASK) {
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if (itemp->opd[i] & ~type & ~SIZE_MASK) {
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return MERR_INVALOP;
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} else if ((itemp->opd[i] & SIZE_MASK) &&
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(itemp->opd[i] & SIZE_MASK) != (type & SIZE_MASK)) {
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10
disasm.c
10
disasm.c
@ -1124,8 +1124,7 @@ int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize,
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* XXX: Need to make sure this is actually correct.
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*/
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for (i = 0; i < (*p)->operands; i++) {
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if (!((*p)->opd[i] & SAME_AS) &&
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(
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if (
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/* If it's a mem-only EA but we have a
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register, die. */
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((tmp_ins.oprs[i].segment & SEG_RMREG) &&
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@ -1141,7 +1140,7 @@ int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize,
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(tmp_ins.oprs[i].segment & SEG_RMREG)) &&
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!whichreg((*p)->opd[i],
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tmp_ins.oprs[i].basereg, tmp_ins.rex))
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)) {
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) {
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works = false;
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break;
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}
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@ -1212,11 +1211,6 @@ int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize,
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const operand *o = &ins.oprs[i];
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int64_t offs;
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if (t & SAME_AS) {
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o = &ins.oprs[t & ~SAME_AS];
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t = (*p)->opd[t & ~SAME_AS];
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}
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output[slen++] = (colon ? ':' : i == 0 ? ' ' : ',');
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offs = o->offset;
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30
insns.pl
30
insns.pl
@ -433,25 +433,21 @@ sub format_insn($$$$$) {
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@ops = ();
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if ($operands ne 'void') {
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foreach $op (split(/,/, $operands)) {
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if ($op =~ /^\=([0-9]+)$/) {
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$op = "same_as|$1";
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} else {
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@opx = ();
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foreach $opp (split(/\|/, $op)) {
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@oppx = ();
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if ($opp =~ s/(?<=\D)(8|16|32|64|80|128|256)$//) {
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push(@oppx, "bits$1");
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}
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$opp =~ s/^mem$/memory/;
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$opp =~ s/^memory_offs$/mem_offs/;
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$opp =~ s/^imm$/immediate/;
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$opp =~ s/^([a-z]+)rm$/rm_$1/;
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$opp =~ s/^rm$/rm_gpr/;
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$opp =~ s/^reg$/reg_gpr/;
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push(@opx, $opp, @oppx);
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@opx = ();
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foreach $opp (split(/\|/, $op)) {
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@oppx = ();
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if ($opp =~ s/(?<=\D)(8|16|32|64|80|128|256)$//) {
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push(@oppx, "bits$1");
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}
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$op = join('|', @opx);
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$opp =~ s/^mem$/memory/;
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$opp =~ s/^memory_offs$/mem_offs/;
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$opp =~ s/^imm$/immediate/;
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$opp =~ s/^([a-z]+)rm$/rm_$1/;
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$opp =~ s/^rm$/rm_gpr/;
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$opp =~ s/^reg$/reg_gpr/;
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push(@opx, $opp, @oppx);
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}
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$op = join('|', @opx);
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push(@ops, $op);
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}
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}
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@ -239,7 +239,4 @@ typedef uint64_t opflags_t;
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#define SDWORD (GEN_SUBCLASS(3) | IMMEDIATE) /* operand is in the range -0x80000000..0x7FFFFFFF */
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#define UDWORD (GEN_SUBCLASS(4) | IMMEDIATE) /* operand is in the range 0..0xFFFFFFFF */
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/* special flags */
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#define SAME_AS GEN_SPECIAL(0)
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#endif /* NASM_OPFLAGS_H */
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