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x86/insns.dat: SHA512-NI VEX support

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Add support for VEX-encoded SHA512-NI instructions.

Signed-off-by: Tomasz Kantecki <tomasz.kantecki@intel.com>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
This commit is contained in:
Tomasz Kantecki 2023-01-13 16:05:47 +00:00 committed by H. Peter Anvin
parent 24275695ff
commit 5f684412c7
4 changed files with 10 additions and 0 deletions
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3
test/sha-64.asm
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@ -28,3 +28,6 @@ BITS 64
sha256msg2 xmm2, [rax]
sha256msg2 xmm3, [rax+0x12]
sha256msg2 xmm4, [rax+rbx*2]
vsha512rnds2 ymm1, ymm2, xmm0
vsha512msg1 ymm1, xmm2
vsha512msg2 ymm1, ymm2

3
test/sha.asm
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@ -29,3 +29,6 @@ BITS 32
sha256msg2 xmm2, [eax]
sha256msg2 xmm3, [eax+0x12]
sha256msg2 xmm4, [eax+ebx*2]
vsha512rnds2 ymm1, ymm2, xmm0
vsha512msg1 ymm1, xmm2
vsha512msg2 ymm1, ymm2

1
x86/iflags.ph
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@ -112,6 +112,7 @@ if_("AVXVNNIINT8", "AVX Vector Neural Network 8-bit integer instructions")
if_("AVXIFMA", "AVX integer multiply and add");
if_("HRESET", "History reset");
if_("SMAP", "Supervisor Mode Access Prevention (SMAP)");
if_("SHA512", "SHA512 instructions");
# Put these last to minimize their relevance
if_("OBSOLETE", "Instruction removed from architecture");

3
x86/insns.dat
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@ -3587,6 +3587,9 @@ SHA256MSG1 xmmreg,xmmrm128 [rm: 0f 38 cc /r ] SHA,FUTUR
SHA256MSG2 xmmreg,xmmrm128 [rm: 0f 38 cd /r ] SHA,FUTURE
SHA256RNDS2 xmmreg,xmmrm128,xmm0 [rm-: 0f 38 cb /r ] SHA,FUTURE
SHA256RNDS2 xmmreg,xmmrm128 [rm: 0f 38 cb /r ] SHA,FUTURE
VSHA512MSG1 ymmreg,xmmreg [rm: vex.256.f2.0f38.w0 cc /r] SHA512,AVX,FUTURE
VSHA512MSG2 ymmreg,ymmreg [rm: vex.256.f2.0f38.w0 cd /r] SHA512,AVX,FUTURE
VSHA512RNDS2 ymmreg,ymmreg,xmmreg [rvm: vex.nds.256.f2.0f38.w0 cb /r] SHA512,AVX,FUTURE
;# AVX no exception conversions
; Must precede AVX-512 versions