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insns.pl: first steps toward a "smart" bytecode compiler
First steps toward a smart(er) bytecode compiler, using a syntax that can be more directly taken from the manuals.
This commit is contained in:
H. Peter Anvin
parent
2c94c44f35
commit
4f0a3e64ee
126
insns.pl
126
insns.pl
@ -40,27 +40,30 @@ $line = 0;
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$insns = 0;
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while (<F>) {
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$line++;
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next if /^\s*;/; # comments
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chomp;
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split;
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next if $#_ == -1; # blank lines
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(warn "line $line does not contain four fields\n"), next if $#_ != 3;
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($formatted, $nd) = &format(@_);
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next if ( /^\s*(\;.*|)$/ ); # comments or blank lines
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unless (/^\s*(\S+)\s+(\S+)\s+(\S+|\[.*\])\s+(\S+)\s*$/) {
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warn "line $line does not contain four fields\n";
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next;
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}
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@fields = ($1, $2, $3, $4);
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($formatted, $nd) = format(@fields);
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if ($formatted) {
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$insns++;
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$aname = "aa_$_[0]";
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$aname = "aa_$fields[0]";
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push @$aname, $formatted;
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}
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if ( $_[0] =~ /cc$/ ) {
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if ( $fields[0] =~ /cc$/ ) {
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# Conditional instruction
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$k_opcodes_cc{$_[0]}++;
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$k_opcodes_cc{$fields[0]}++;
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} else {
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# Unconditional instruction
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$k_opcodes{$_[0]}++;
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$k_opcodes{$fields[0]}++;
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}
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if ($formatted && !$nd) {
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push @big, $formatted;
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my @sseq = startseq($_[2]);
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my @sseq = startseq($fields[2]);
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foreach $i (@sseq) {
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if (!defined($dinstables{$i})) {
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$dinstables{$i} = [];
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@ -281,7 +284,7 @@ if ( !defined($output) || $output eq 'n' ) {
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printf STDERR "Done: %d instructions\n", $insns;
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sub format {
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sub format(@) {
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my ($opcode, $operands, $codes, $flags) = @_;
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my $num, $nd = 0;
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my @bytecode;
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@ -363,6 +366,10 @@ sub decodify($) {
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my $c = $codestr;
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my @codes = ();
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if ($codestr =~ /^\s*\[([^\]]*)\]\s*$/) {
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return byte_code_compile($1);
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}
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while ($c ne '') {
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if ($c =~ /^\\x([0-9a-f]+)(.*)$/i) {
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push(@codes, hex $1);
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@ -465,3 +472,100 @@ sub startseq($) {
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}
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return $prefix;
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}
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#
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# This function takes a series of byte codes in a format which is more
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# typical of the Intel documentation, and encode it.
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#
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# The format looks like:
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#
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# [operands: opcodes]
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#
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# The operands word lists the order of the operands:
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#
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# r = register field in the modr/m
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# m = modr/m
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# v = VEX "v" field or DREX "src" field
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# i = immediate
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# z = register field of is4 or imz2 field
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#
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sub byte_code_compile($) {
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my($str) = @_;
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my $opr;
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my $opc;
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my @codes = ();
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my $litix = undef;
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my %oppos = ();
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my $i;
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my $op, $oq;
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if ($str =~ /^(\S*)\:\s*(.*\S)\s*$/) {
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$opr = "\L$1";
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$opc = "\L$2";
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} else {
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$opr = '';
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$opc = $str;
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}
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for ($i = 0; $i < length($opr); $i++) {
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$oppos{substr($opr,$i,1)} = $i;
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}
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foreach $op (split($opc)) {
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if ($op =~ /^[0-9a-f]{2}$/) {
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if (defined($litix) && $litix+$codes[$litix]+1 == scalar @codes) {
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$codes[$litix]++;
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push(@codes, hex $op);
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} else {
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$litix = scalar(@codes);
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push(@codes, 01, hex $op);
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}
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} elsif ($op eq '/r') {
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if (!defined($oppos{'r'}) || !defined($oppos{'m'})) {
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die "$0: $line: $op requires r and m operands\n";
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}
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push(@codes, 0100 + ($oppos{'m'} << 3) + $oppos{'r'});
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} elsif ($op =~ m:^/([0-7])$:) {
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if (!defined($oppos{'m'})) {
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die "$0: $line: $op requires m operand\n";
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}
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push(@codes, 0200 + ($oppos{'m'} << 3) + $1;
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} elsif ($op =~ /^vex\./) {
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my ($m,$w,$l,$p) = (undef,2,undef,0);
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foreach $oq (split(/\./, $op)) {
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if ($oq eq 'vex') {
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# prefix
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} elsif ($oq eq '128' || $oq eq 'l0') {
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$l = 0;
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} elsif ($oq eq '256' || $oq eq 'l1') {
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$l = 1;
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} elsif ($oq eq 'w0') {
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$w = 0;
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} elsif ($oq eq 'w1') {
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$w = 1;
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} elsif ($oq eq '66') {
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$p = 1;
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} elsif ($oq eq 'f3') {
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$p = 2;
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} elsif ($oq eq 'f2') {
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$p = 3;
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} elsif ($oq eq '0f') {
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$m = 1;
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} elsif ($oq eq '0f38') {
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$m = 2;
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} elsif ($oq eq '0f3a') {
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$m = 3;
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} elsif ($oq =~ /^m([0-9]+)$/) {
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$m = $1+0;
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} elsif ($oq eq 'nds' || $oq eq 'ndd') {
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return undef if (!defined($oppos{'v'}));
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} else {
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die "$0: $line: undefined VEX subcode: $oq\n";
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}
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}
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if (!defined($m) || !defined($w) || !defined($l) || !defined($p)) {
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die "$0: $line: missing fields in VEX specification\n";
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}
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push(@codes, defined($oppos{'v'}) ? 0260+$oppos{'v'} : 0270,
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$m, ($w << 3)+($l << 2)+$p);
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}
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