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BR 1828866: fix handling of LAR/LSL

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Fix handling of LAR/LSL with various sized operands
This commit is contained in:
H. Peter Anvin 2007-11-12 22:05:31 -08:00
parent e8cdcdcc37
commit 4b3390eb47
2 changed files with 134 additions and 0 deletions
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12
insns.dat
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@ -618,10 +618,16 @@ JRCXZ imm \1\xE3\50 X64
LAHF void \1\x9F 8086
LAR reg16,mem \320\2\x0F\x02\110 286,PROT,SW
LAR reg16,reg16 \320\2\x0F\x02\110 286,PROT
LAR reg16,reg32 \320\2\x0F\x02\110 386,PROT
LAR reg16,reg64 \320\323\2\x0F\x02\110 X64,PROT,ND
LAR reg32,mem \321\2\x0F\x02\110 386,PROT,SW
LAR reg32,reg16 \321\2\x0F\x02\110 386,PROT
LAR reg32,reg32 \321\2\x0F\x02\110 386,PROT
LAR reg32,reg64 \321\323\2\x0F\x02\110 X64,PROT,ND
LAR reg64,mem \324\2\x0F\x02\110 X64,PROT,SW
LAR reg64,reg16 \324\2\x0F\x02\110 X64,PROT
LAR reg64,reg32 \324\2\x0F\x02\110 X64,PROT
LAR reg64,reg64 \324\2\x0F\x02\110 X64,PROT
LDS reg16,mem \320\1\xC5\110 8086,NOLONG
LDS reg32,mem \321\1\xC5\110 386,NOLONG
LEA reg16,mem \320\1\x8D\110 8086
@ -671,10 +677,16 @@ LOOPZ imm,reg_ecx \311\1\xE1\50 386
LOOPZ imm,reg_rcx \313\1\xE1\50 X64
LSL reg16,mem \320\2\x0F\x03\110 286,PROT,SW
LSL reg16,reg16 \320\2\x0F\x03\110 286,PROT
LSL reg16,reg32 \320\2\x0F\x03\110 386,PROT
LSL reg16,reg64 \320\323\2\x0F\x03\110 X64,PROT,ND
LSL reg32,mem \321\2\x0F\x03\110 386,PROT,SW
LSL reg32,reg16 \321\2\x0F\x03\110 386,PROT
LSL reg32,reg32 \321\2\x0F\x03\110 386,PROT
LSL reg32,reg64 \321\323\2\x0F\x03\110 X64,PROT,ND
LSL reg64,mem \324\2\x0F\x03\110 X64,PROT,SW
LSL reg64,reg16 \324\2\x0F\x03\110 X64,PROT
LSL reg64,reg32 \324\2\x0F\x03\110 X64,PROT
LSL reg64,reg64 \324\2\x0F\x03\110 X64,PROT
LSS reg16,mem \320\2\x0F\xB2\110 386
LSS reg32,mem \321\2\x0F\xB2\110 386
LTR mem \1\x0F\170\203 286,PROT,PRIV

122
test/lar_lsl.asm Normal file
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@ -0,0 +1,122 @@
; LAR/LSL
;---------
; 1x ; = invalid due to lack of REX
; 3x ; = invalid due to Mw
%macro m 1
bits 16
%1 ax, ax
%1 ax,eax
; %1 ax,rax
%1 eax, ax
%1 eax,eax
; %1 eax,rax
; %1 rax, ax
; %1 rax,eax
; %1 rax,rax
%1 ax, [0]
%1 ax, word [0]
;;; %1 ax,dword [0]
; %1 ax,qword [0]
%1 eax, [0]
%1 eax, word [0]
;;; %1 eax,dword [0]
; %1 eax,qword [0]
; %1 rax, [0]
; %1 rax, word [0]
; %1 rax,dword [0]
; %1 rax,qword [0]
bits 32
%1 ax, ax
%1 ax,eax
; %1 ax,rax
%1 eax, ax
%1 eax,eax
; %1 eax,rax
; %1 rax, ax
; %1 rax,eax
; %1 rax,rax
%1 ax, [0]
%1 ax, word [0]
;;; %1 ax,dword [0]
; %1 ax,qword [0]
%1 eax, [0]
%1 eax, word [0]
;;; %1 eax,dword [0]
; %1 eax,qword [0]
; %1 rax, [0]
; %1 rax, word [0]
; %1 rax,dword [0]
; %1 rax,qword [0]
bits 64
%1 ax, ax
%1 ax,eax
%1 ax,rax ; $TODO: shouldn't emit REX.W $
%1 eax, ax
%1 eax,eax
%1 eax,rax ; $TODO: shouldn't emit REX.W $
%1 rax, ax
%1 rax,eax
%1 rax,rax
%1 ax, [0]
%1 ax, word [0]
;;; %1 ax,dword [0]
;;; %1 ax,qword [0]
%1 eax, [0]
%1 eax, word [0]
;;; %1 eax,dword [0]
;;; %1 eax,qword [0]
%1 rax, [0]
%1 rax, word [0]
;;; %1 rax,dword [0]
;;; %1 rax,qword [0]
%endmacro
m lar
m lsl
bits 16
lar ax,[ si]
lar ax,[esi]
bits 32
lar ax,[ si]
lar ax,[esi]
bits 64
lar ax,[esi]
lar ax,[rsi]
bits 16
lsl ax,[ si]
lsl ax,[esi]
bits 32
lsl ax,[ si]
lsl ax,[esi]
bits 64
lar ax,[esi]
lsl ax,[rsi]
; EOF