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Fix opcode for VADDSUBPS; operands for VBLEND; add SSE for AES ops

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Fix the opcode for VADDSUBPS
Fix the operands for VBLEND
Corrent the instruction flags for the AES ops (they're SSE)
This commit is contained in:
H. Peter Anvin 2009-02-21 16:56:52 -08:00
parent d8e47f6da9
commit 2c784d9024
1 changed files with 14 additions and 14 deletions
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28
insns.dat
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@ -2204,12 +2204,12 @@ MOVBE mem32,reg32 [mr: o32 0f 38 f1 /r] NEHALEM,SM
MOVBE mem64,reg64 [mr: o64 0f 38 f1 /r] NEHALEM,SM
;# Intel AES instructions
AESENC xmmreg,xmmrm [rm: 66 0f 38 dc /r] WESTMERE,SO
AESENCLAST xmmreg,xmmrm [rm: 66 0f 38 dd /r] WESTMERE,SO
AESDEC xmmreg,xmmrm [rm: 66 0f 38 de /r] WESTMERE,SO
AESDECLAST xmmreg,xmmrm [rm: 66 0f 38 df /r] WESTMERE,SO
AESIMC xmmreg,xmmrm [rm: 66 0f 38 db /r] WESTMERE,SO
AESKEYGENASSIST xmmreg,xmmrm,imm [rmi: 66 0f 3a df /r ib] WESTMERE,SO
AESENC xmmreg,xmmrm [rm: 66 0f 38 dc /r] SSE,WESTMERE,SO
AESENCLAST xmmreg,xmmrm [rm: 66 0f 38 dd /r] SSE,WESTMERE,SO
AESDEC xmmreg,xmmrm [rm: 66 0f 38 de /r] SSE,WESTMERE,SO
AESDECLAST xmmreg,xmmrm [rm: 66 0f 38 df /r] SSE,WESTMERE,SO
AESIMC xmmreg,xmmrm [rm: 66 0f 38 db /r] SSE,WESTMERE,SO
AESKEYGENASSIST xmmreg,xmmrm,imm [rmi: 66 0f 3a df /r ib] SSE,WESTMERE,SO
;# Intel AVX AES instructions
VAESENC xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 dc /r] AVX,SANDYBRIDGE,SO
@ -2240,10 +2240,10 @@ VADDSUBPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f d0 /r] AVX,SANDYBRIDGE,S
VADDSUBPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f d0 /r] AVX,SANDYBRIDGE,SO
VADDSUBPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f d0 /r] AVX,SANDYBRIDGE,SY
VADDSUBPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f d0 /r] AVX,SANDYBRIDGE,SY
VADDSUBPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f f0 /r] AVX,SANDYBRIDGE,SO
VADDSUBPS xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f f0 /r] AVX,SANDYBRIDGE,SO
VADDSUBPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.f2.0f f0 /r] AVX,SANDYBRIDGE,SY
VADDSUBPS ymmreg,ymmrm [r+vm: vex.nds.256.f2.0f f0 /r] AVX,SANDYBRIDGE,SY
VADDSUBPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f d0 /r] AVX,SANDYBRIDGE,SO
VADDSUBPS xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f d0 /r] AVX,SANDYBRIDGE,SO
VADDSUBPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.f2.0f d0 /r] AVX,SANDYBRIDGE,SY
VADDSUBPS ymmreg,ymmrm [r+vm: vex.nds.256.f2.0f d0 /r] AVX,SANDYBRIDGE,SY
VANDPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 54 /r] AVX,SANDYBRIDGE,SO
VANDPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 54 /r] AVX,SANDYBRIDGE,SO
VANDPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f 54 /r] AVX,SANDYBRIDGE,SY
@ -2268,13 +2268,13 @@ VBLENDPS xmmreg,xmmreg,xmmrm,imm [rvmi: vex.nds.128.66.0f3a 0c /r ib] AVX,SAND
VBLENDPS xmmreg,xmmrm,imm [r+vmi: vex.nds.128.66.0f3a 0c /r ib] AVX,SANDYBRIDGE,SO
VBLENDPS ymmreg,ymmreg,ymmrm,imm [rvmi: vex.nds.256.66.0f3a 0c /r ib] AVX,SANDYBRIDGE,SY
VBLENDPS ymmreg,ymmrm,imm [r+vmi: vex.nds.256.66.0f3a 0c /r ib] AVX,SANDYBRIDGE,SY
VBLENDVPD xmmreg,xmmreg,xmmrm,xmmrm [rvms: vex.nds.128.66.0f3a 4b /r /is4] AVX,SANDYBRIDGE,SO
VBLENDVPD xmmreg,xmmreg,xmmrm,xmmreg [rvms: vex.nds.128.66.0f3a 4b /r /is4] AVX,SANDYBRIDGE,SO
VBLENDVPD xmmreg,xmmrm,xmm0 [rm-: vex.128.66.0f38 15 /r] AVX,SANDYBRIDGE,SO
VBLENDVPD ymmreg,ymmreg,ymmrm,ymmrm [rvms: vex.nds.256.66.0f3a 4b /r /is4] AVX,SANDYBRIDGE,SY
VBLENDVPD ymmreg,ymmreg,ymmrm,ymmreg [rvms: vex.nds.256.66.0f3a 4b /r /is4] AVX,SANDYBRIDGE,SY
VBLENDVPD ymmreg,ymmrm,ymm0 [rm-: vex.256.66.0f38 15 /r] AVX,SANDYBRIDGE,SY
VBLENDVPS xmmreg,xmmreg,xmmrm,xmmrm [rvms: vex.nds.128.66.0f3a 4a /r /is4] AVX,SANDYBRIDGE,SO
VBLENDVPS xmmreg,xmmreg,xmmrm,xmmreg [rvms: vex.nds.128.66.0f3a 4a /r /is4] AVX,SANDYBRIDGE,SO
VBLENDVPS xmmreg,xmmrm,xmm0 [rm-: vex.128.66.0f38 14 /r] AVX,SANDYBRIDGE,SO
VBLENDVPS ymmreg,ymmreg,ymmrm,ymmrm [rvms: vex.nds.256.66.0f3a 4a /r /is4] AVX,SANDYBRIDGE,SY
VBLENDVPS ymmreg,ymmreg,ymmrm,ymmreg [rvms: vex.nds.256.66.0f3a 4a /r /is4] AVX,SANDYBRIDGE,SY
VBLENDVPD ymmreg,ymmrm,ymm0 [rm-: vex.256.66.0f38 14 /r] AVX,SANDYBRIDGE,SY
VBROADCASTSS xmmreg,mem [rm: vex.128.66.0f38 18 /r] AVX,SANDYBRIDGE,SD
VBROADCASTSS ymmreg,mem [rm: vex.256.66.0f38 18 /r] AVX,SANDYBRIDGE,SD