mirror of
https://github.com/netwide-assembler/nasm.git
synced 2025-03-19 18:00:23 +08:00
assemble: move the instruction-matching loop into a common function
Move the instruction-matching loop into a common function. This gives us a single point to adjust the instruction-selection algorithm. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
This commit is contained in:
H. Peter Anvin
parent
65289e84ed
commit
23595f5946
387
assemble.c
387
assemble.c
@ -195,6 +195,9 @@ static int64_t calcsize(int32_t, int64_t, int, insn *, const uint8_t *);
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static void gencode(int32_t segment, int64_t offset, int bits,
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insn * ins, const struct itemplate *temp,
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int64_t insn_end);
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static enum match_result find_match(const struct itemplate **tempp,
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insn *instruction,
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int32_t segment, int64_t offset, int bits);
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static enum match_result matches(const struct itemplate *, insn *, int bits);
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static int32_t regflag(const operand *);
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static int32_t regval(const operand *);
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@ -328,7 +331,7 @@ int64_t assemble(int32_t segment, int64_t offset, int bits, uint32_t cp,
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{
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const struct itemplate *temp;
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int j;
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enum match_result size_prob;
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enum match_result m;
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int64_t insn_end;
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int32_t itimes;
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int64_t start = offset;
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@ -499,149 +502,140 @@ int64_t assemble(int32_t segment, int64_t offset, int bits, uint32_t cp,
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/* Check to see if we need an address-size prefix */
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add_asp(instruction, bits);
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size_prob = MERR_INVALOP;
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m = find_match(&temp, instruction, segment, offset, bits);
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for (temp = nasm_instructions[instruction->opcode];
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temp->opcode != -1; temp++){
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enum match_result m = matches(temp, instruction, bits);
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if (m == MOK_GOOD ||
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(m == MOK_JUMP && jmp_match(segment, offset, bits,
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instruction, temp->code))) {
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/* Matches! */
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int64_t insn_size = calcsize(segment, offset, bits,
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instruction, temp->code);
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itimes = instruction->times;
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if (insn_size < 0) /* shouldn't be, on pass two */
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error(ERR_PANIC, "errors made it through from pass one");
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else
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while (itimes--) {
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for (j = 0; j < MAXPREFIX; j++) {
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uint8_t c = 0;
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switch (instruction->prefixes[j]) {
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case P_WAIT:
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c = 0x9B;
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break;
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case P_LOCK:
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c = 0xF0;
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break;
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case P_REPNE:
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case P_REPNZ:
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c = 0xF2;
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break;
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case P_REPE:
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case P_REPZ:
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case P_REP:
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c = 0xF3;
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break;
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case R_CS:
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if (bits == 64) {
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error(ERR_WARNING | ERR_PASS2,
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"cs segment base generated, but will be ignored in 64-bit mode");
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}
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c = 0x2E;
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break;
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case R_DS:
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if (bits == 64) {
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error(ERR_WARNING | ERR_PASS2,
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"ds segment base generated, but will be ignored in 64-bit mode");
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}
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c = 0x3E;
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break;
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case R_ES:
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if (bits == 64) {
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error(ERR_WARNING | ERR_PASS2,
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"es segment base generated, but will be ignored in 64-bit mode");
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}
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c = 0x26;
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break;
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case R_FS:
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c = 0x64;
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break;
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case R_GS:
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c = 0x65;
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break;
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case R_SS:
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if (bits == 64) {
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error(ERR_WARNING | ERR_PASS2,
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"ss segment base generated, but will be ignored in 64-bit mode");
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}
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c = 0x36;
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break;
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case R_SEGR6:
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case R_SEGR7:
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error(ERR_NONFATAL,
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"segr6 and segr7 cannot be used as prefixes");
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break;
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case P_A16:
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if (bits == 64) {
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error(ERR_NONFATAL,
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"16-bit addressing is not supported "
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"in 64-bit mode");
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} else if (bits != 16)
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c = 0x67;
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break;
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case P_A32:
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if (bits != 32)
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c = 0x67;
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break;
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case P_A64:
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if (bits != 64) {
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error(ERR_NONFATAL,
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"64-bit addressing is only supported "
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"in 64-bit mode");
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}
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break;
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case P_ASP:
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if (m == MOK_GOOD) {
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/* Matches! */
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int64_t insn_size = calcsize(segment, offset, bits,
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instruction, temp->code);
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itimes = instruction->times;
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if (insn_size < 0) /* shouldn't be, on pass two */
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error(ERR_PANIC, "errors made it through from pass one");
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else
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while (itimes--) {
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for (j = 0; j < MAXPREFIX; j++) {
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uint8_t c = 0;
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switch (instruction->prefixes[j]) {
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case P_WAIT:
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c = 0x9B;
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break;
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case P_LOCK:
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c = 0xF0;
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break;
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case P_REPNE:
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case P_REPNZ:
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c = 0xF2;
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break;
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case P_REPE:
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case P_REPZ:
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case P_REP:
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c = 0xF3;
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break;
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case R_CS:
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if (bits == 64) {
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error(ERR_WARNING | ERR_PASS2,
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"cs segment base generated, but will be ignored in 64-bit mode");
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}
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c = 0x2E;
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break;
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case R_DS:
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if (bits == 64) {
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error(ERR_WARNING | ERR_PASS2,
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"ds segment base generated, but will be ignored in 64-bit mode");
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}
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c = 0x3E;
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break;
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case R_ES:
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if (bits == 64) {
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error(ERR_WARNING | ERR_PASS2,
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"es segment base generated, but will be ignored in 64-bit mode");
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}
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c = 0x26;
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break;
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case R_FS:
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c = 0x64;
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break;
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case R_GS:
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c = 0x65;
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break;
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case R_SS:
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if (bits == 64) {
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error(ERR_WARNING | ERR_PASS2,
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"ss segment base generated, but will be ignored in 64-bit mode");
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}
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c = 0x36;
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break;
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case R_SEGR6:
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case R_SEGR7:
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error(ERR_NONFATAL,
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"segr6 and segr7 cannot be used as prefixes");
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break;
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case P_A16:
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if (bits == 64) {
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error(ERR_NONFATAL,
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"16-bit addressing is not supported "
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"in 64-bit mode");
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} else if (bits != 16)
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c = 0x67;
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break;
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case P_O16:
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if (bits != 16)
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c = 0x66;
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break;
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case P_O32:
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if (bits == 16)
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c = 0x66;
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break;
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case P_O64:
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/* REX.W */
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break;
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case P_OSP:
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break;
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case P_A32:
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if (bits != 32)
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c = 0x67;
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break;
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case P_A64:
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if (bits != 64) {
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error(ERR_NONFATAL,
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"64-bit addressing is only supported "
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"in 64-bit mode");
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}
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break;
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case P_ASP:
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c = 0x67;
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break;
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case P_O16:
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if (bits != 16)
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c = 0x66;
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break;
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case P_none:
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break;
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default:
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error(ERR_PANIC, "invalid instruction prefix");
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}
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if (c != 0) {
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out(offset, segment, &c, OUT_RAWDATA, 1,
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NO_SEG, NO_SEG);
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offset++;
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}
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}
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insn_end = offset + insn_size;
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gencode(segment, offset, bits, instruction,
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temp, insn_end);
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offset += insn_size;
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if (itimes > 0 && itimes == instruction->times - 1) {
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/*
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* Dummy call to list->output to give the offset to the
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* listing module.
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*/
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list->output(offset, NULL, OUT_RAWDATA, 0);
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list->uplevel(LIST_TIMES);
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}
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}
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if (instruction->times > 1)
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list->downlevel(LIST_TIMES);
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return offset - start;
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} else if (m > 0 && m > size_prob) {
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size_prob = m;
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}
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}
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if (temp->opcode == -1) { /* didn't match any instruction */
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switch (size_prob) {
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break;
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case P_O32:
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if (bits == 16)
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c = 0x66;
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break;
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case P_O64:
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/* REX.W */
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break;
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case P_OSP:
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c = 0x66;
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break;
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case P_none:
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break;
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default:
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error(ERR_PANIC, "invalid instruction prefix");
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}
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if (c != 0) {
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out(offset, segment, &c, OUT_RAWDATA, 1,
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NO_SEG, NO_SEG);
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offset++;
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}
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}
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insn_end = offset + insn_size;
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gencode(segment, offset, bits, instruction,
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temp, insn_end);
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offset += insn_size;
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if (itimes > 0 && itimes == instruction->times - 1) {
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/*
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* Dummy call to list->output to give the offset to the
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* listing module.
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*/
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list->output(offset, NULL, OUT_RAWDATA, 0);
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list->uplevel(LIST_TIMES);
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}
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}
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if (instruction->times > 1)
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list->downlevel(LIST_TIMES);
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return offset - start;
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} else {
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/* No match */
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switch (m) {
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case MERR_OPSIZEMISSING:
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error(ERR_NONFATAL, "operation size not specified");
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break;
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@ -668,6 +662,7 @@ int64_t insn_size(int32_t segment, int64_t offset, int bits, uint32_t cp,
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insn * instruction, efunc error)
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{
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const struct itemplate *temp;
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enum match_result m;
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errfunc = error; /* to pass to other functions */
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cpu = cp;
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@ -757,51 +752,47 @@ int64_t insn_size(int32_t segment, int64_t offset, int bits, uint32_t cp,
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/* Check to see if we need an address-size prefix */
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add_asp(instruction, bits);
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for (temp = nasm_instructions[instruction->opcode];
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temp->opcode != -1; temp++) {
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enum match_result m = matches(temp, instruction, bits);
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if (m == MOK_GOOD ||
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(m == MOK_JUMP && jmp_match(segment, offset, bits,
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instruction, temp->code))) {
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/* we've matched an instruction. */
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int64_t isize;
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const uint8_t *codes = temp->code;
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int j;
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isize = calcsize(segment, offset, bits, instruction, codes);
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if (isize < 0)
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return -1;
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for (j = 0; j < MAXPREFIX; j++) {
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switch (instruction->prefixes[j]) {
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case P_A16:
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if (bits != 16)
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isize++;
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break;
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case P_A32:
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if (bits != 32)
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isize++;
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break;
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case P_O16:
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if (bits != 16)
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isize++;
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break;
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case P_O32:
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if (bits == 16)
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isize++;
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break;
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case P_A64:
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case P_O64:
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case P_none:
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break;
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default:
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m = find_match(&temp, instruction, segment, offset, bits);
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if (m == MOK_GOOD) {
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/* we've matched an instruction. */
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int64_t isize;
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const uint8_t *codes = temp->code;
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int j;
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isize = calcsize(segment, offset, bits, instruction, codes);
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if (isize < 0)
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return -1;
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for (j = 0; j < MAXPREFIX; j++) {
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switch (instruction->prefixes[j]) {
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case P_A16:
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if (bits != 16)
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isize++;
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break;
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}
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}
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return isize * instruction->times;
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}
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break;
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case P_A32:
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if (bits != 32)
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isize++;
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break;
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case P_O16:
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if (bits != 16)
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isize++;
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break;
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case P_O32:
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if (bits == 16)
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isize++;
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break;
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case P_A64:
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case P_O64:
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case P_none:
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break;
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default:
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isize++;
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break;
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}
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}
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return isize * instruction->times;
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} else {
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return -1; /* didn't match any instruction */
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}
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return -1; /* didn't match any instruction */
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}
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static bool possible_sbyte(operand *o)
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@ -1986,6 +1977,34 @@ static int rexflags(int val, int32_t flags, int mask)
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return rex & mask;
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}
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static enum match_result find_match(const struct itemplate **tempp,
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insn *instruction,
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int32_t segment, int64_t offset, int bits)
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{
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const struct itemplate *temp;
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enum match_result m, merr;
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merr = MERR_INVALOP;
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for (temp = nasm_instructions[instruction->opcode];
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temp->opcode != I_none; temp++) {
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m = matches(temp, instruction, bits);
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if (m == MOK_JUMP) {
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if (jmp_match(segment, offset, bits, instruction, temp->code))
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m = MOK_GOOD;
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else
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m = MERR_INVALOP;
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}
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if (m > merr)
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merr = m;
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if (merr == MOK_GOOD)
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break;
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}
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*tempp = temp;
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return merr;
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}
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static enum match_result matches(const struct itemplate *itemp,
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insn *instruction, int bits)
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{
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