nasm/test/vaesenc.asm

;; BR 3392454, 3392460

	bits 64
	aesenc xmm0,xmm4
	vaesenc zmm0,zmm0,zmm4
	vpclmullqlqdq zmm1,zmm1,zmm5
	vpclmulqdq zmm0, zmm1, zmm2, 0
	vaesenclast zmm0, zmm1, zmm2

	bits 32
	aesenc xmm0,xmm4
	vaesenc zmm0,zmm0,zmm4
	vpclmullqlqdq zmm1,zmm1,zmm5
	vpclmulqdq zmm0, zmm1, zmm2, 0
	vaesenclast zmm0, zmm1, zmm2

	bits 16
	aesenc xmm0,xmm4
	vaesenc zmm0,zmm0,zmm4
	vpclmullqlqdq zmm1,zmm1,zmm5
	vpclmulqdq zmm0, zmm1, zmm2, 0
	vaesenclast zmm0, zmm1, zmm2
vaesenc.asm: add a few more test cases Signed-off-by: H. Peter Anvin <hpa@linux.intel.com> 2018-02-07 10:48:13 -08:00			`;; BR 3392454, 3392460`
iflag: automatically assign values, saner handling of CPU levels Automatically assign values to the instruction flags; we ended up with a case where pushing flags into the next dword caused comparison failures due to other places in the code explicitly comparing field[3]. This creates necessary defines for this not to happen; it also cleans up a fair bit of the iflag code. This resolves BR 3392454. Reported-by: Thomasz Kantecki <tomasz.kantecki@intel.com> Signed-off-by: H. Peter Anvin <hpa@linux.intel.com> 2018-02-06 14:43:07 -08:00
			`bits 64`
			`aesenc xmm0,xmm4`
			`vaesenc zmm0,zmm0,zmm4`
			`vpclmullqlqdq zmm1,zmm1,zmm5`
vaesenc.asm: add a few more test cases Signed-off-by: H. Peter Anvin <hpa@linux.intel.com> 2018-02-07 10:48:13 -08:00			`vpclmulqdq zmm0, zmm1, zmm2, 0`
			`vaesenclast zmm0, zmm1, zmm2`

			`bits 32`
			`aesenc xmm0,xmm4`
			`vaesenc zmm0,zmm0,zmm4`
			`vpclmullqlqdq zmm1,zmm1,zmm5`
			`vpclmulqdq zmm0, zmm1, zmm2, 0`
			`vaesenclast zmm0, zmm1, zmm2`

			`bits 16`
			`aesenc xmm0,xmm4`
			`vaesenc zmm0,zmm0,zmm4`
			`vpclmullqlqdq zmm1,zmm1,zmm5`
			`vpclmulqdq zmm0, zmm1, zmm2, 0`
			`vaesenclast zmm0, zmm1, zmm2`