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668 lines
18 KiB
C
668 lines
18 KiB
C
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/* disasm.c where all the _work_ gets done in the Netwide Disassembler
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*
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* The Netwide Assembler is copyright (C) 1996 Simon Tatham and
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* Julian Hall. All rights reserved. The software is
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* redistributable under the licence given in the file "Licence"
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* distributed in the NASM archive.
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*
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* initial version 27/iii/95 by Simon Tatham
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*/
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#include <stdio.h>
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#include <string.h>
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#include "nasm.h"
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#include "disasm.h"
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#include "sync.h"
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#include "insns.h"
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#include "names.c"
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extern struct itemplate **itable[];
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/*
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* Flags that go into the `segment' field of `insn' structures
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* during disassembly.
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*/
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#define SEG_RELATIVE 1
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#define SEG_32BIT 2
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#define SEG_RMREG 4
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#define SEG_DISP8 8
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#define SEG_DISP16 16
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#define SEG_DISP32 32
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#define SEG_NODISP 64
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#define SEG_SIGNED 128
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static int whichreg(long regflags, int regval) {
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static int reg32[] = {
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R_EAX, R_ECX, R_EDX, R_EBX, R_ESP, R_EBP, R_ESI, R_EDI };
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static int reg16[] = {
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R_AX, R_CX, R_DX, R_BX, R_SP, R_BP, R_SI, R_DI };
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static int reg8[] = {
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R_AL, R_CL, R_DL, R_BL, R_AH, R_CH, R_DH, R_BH };
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static int sreg[] = {
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R_ES, R_CS, R_SS, R_DS, R_FS, R_GS, 0, 0 };
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static int creg[] = {
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R_CR0, 0, R_CR2, R_CR3, R_CR4, 0, 0, 0 };
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static int dreg[] = {
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R_DR0, R_DR1, R_DR2, R_DR3, 0, 0, R_DR6, R_DR7 };
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static int treg[] = {
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0, 0, 0, R_TR3, R_TR4, R_TR5, R_TR6, R_TR7 };
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static int fpureg[] = {
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R_ST0, R_ST1, R_ST2, R_ST3, R_ST4, R_ST5, R_ST6, R_ST7 };
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static int mmxreg[] = {
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R_MM0, R_MM1, R_MM2, R_MM3, R_MM4, R_MM5, R_MM6, R_MM7 };
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if (!(REG_AL & ~regflags))
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return R_AL;
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if (!(REG_AX & ~regflags))
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return R_AX;
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if (!(REG_EAX & ~regflags))
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return R_EAX;
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if (!(REG_DX & ~regflags))
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return R_DX;
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if (!(REG_CL & ~regflags))
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return R_CL;
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if (!(REG_CX & ~regflags))
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return R_CX;
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if (!(REG_ECX & ~regflags))
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return R_ECX;
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if (!(REG_CR4 & ~regflags))
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return R_CR4;
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if (!(FPU0 & ~regflags))
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return R_ST0;
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if (!((REGMEM|BITS8) & ~regflags))
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return reg8[regval];
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if (!((REGMEM|BITS16) & ~regflags))
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return reg16[regval];
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if (!((REGMEM|BITS32) & ~regflags))
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return reg32[regval];
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if (!(REG_SREG & ~regflags))
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return sreg[regval];
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if (!(REG_CREG & ~regflags))
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return creg[regval];
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if (!(REG_DREG & ~regflags))
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return dreg[regval];
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if (!(REG_TREG & ~regflags))
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return treg[regval];
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if (!(FPUREG & ~regflags))
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return fpureg[regval];
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if (!(MMXREG & ~regflags))
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return mmxreg[regval];
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return 0;
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}
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static char *whichcond(int condval) {
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static int conds[] = {
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C_O, C_NO, C_B, C_AE, C_E, C_NE, C_BE, C_A,
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C_S, C_NS, C_PE, C_PO, C_L, C_GE, C_LE, C_G
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};
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return conditions[conds[condval]];
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}
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/*
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* Process an effective address (ModRM) specification.
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*/
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static unsigned char *do_ea (unsigned char *data, int modrm, int asize,
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int segsize, operand *op) {
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int mod, rm, scale, index, base;
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mod = (modrm >> 6) & 03;
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rm = modrm & 07;
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if (mod == 3) { /* pure register version */
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op->basereg = rm;
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op->segment |= SEG_RMREG;
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return data;
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}
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op->addr_size = 0;
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if (asize == 16) {
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/*
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* <mod> specifies the displacement size (none, byte or
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* word), and <rm> specifies the register combination.
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* Exception: mod=0,rm=6 does not specify [BP] as one might
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* expect, but instead specifies [disp16].
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*/
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op->indexreg = op->basereg = -1;
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op->scale = 1; /* always, in 16 bits */
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switch (rm) {
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case 0: op->basereg = R_BX; op->indexreg = R_SI; break;
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case 1: op->basereg = R_BX; op->indexreg = R_DI; break;
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case 2: op->basereg = R_BP; op->indexreg = R_SI; break;
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case 3: op->basereg = R_BP; op->indexreg = R_DI; break;
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case 4: op->basereg = R_SI; break;
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case 5: op->basereg = R_DI; break;
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case 6: op->basereg = R_BP; break;
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case 7: op->basereg = R_BX; break;
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}
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if (rm == 6 && mod == 0) { /* special case */
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op->basereg = -1;
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if (segsize != 16)
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op->addr_size = 16;
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mod = 2; /* fake disp16 */
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}
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switch (mod) {
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case 0:
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op->segment |= SEG_NODISP;
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break;
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case 1:
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op->segment |= SEG_DISP8;
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op->offset = (signed char) *data++;
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break;
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case 2:
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op->segment |= SEG_DISP16;
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op->offset = *data++;
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op->offset |= (*data++) << 8;
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break;
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}
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return data;
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} else {
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/*
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* Once again, <mod> specifies displacement size (this time
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* none, byte or *dword*), while <rm> specifies the base
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* register. Again, [EBP] is missing, replaced by a pure
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* disp32 (this time that's mod=0,rm=*5*). However, rm=4
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* indicates not a single base register, but instead the
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* presence of a SIB byte...
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*/
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op->indexreg = -1;
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switch (rm) {
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case 0: op->basereg = R_EAX; break;
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case 1: op->basereg = R_ECX; break;
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case 2: op->basereg = R_EDX; break;
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case 3: op->basereg = R_EBX; break;
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case 5: op->basereg = R_EBP; break;
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case 6: op->basereg = R_ESI; break;
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case 7: op->basereg = R_EDI; break;
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}
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if (rm == 5 && mod == 0) {
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op->basereg = -1;
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if (segsize != 32)
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op->addr_size = 32;
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mod = 2; /* fake disp32 */
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}
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if (rm == 4) { /* process SIB */
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scale = (*data >> 6) & 03;
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index = (*data >> 3) & 07;
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base = *data & 07;
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data++;
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op->scale = 1 << scale;
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switch (index) {
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case 0: op->indexreg = R_EAX; break;
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case 1: op->indexreg = R_ECX; break;
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case 2: op->indexreg = R_EDX; break;
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case 3: op->indexreg = R_EBX; break;
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case 4: op->indexreg = -1; break;
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case 5: op->indexreg = R_EBP; break;
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case 6: op->indexreg = R_ESI; break;
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case 7: op->indexreg = R_EDI; break;
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}
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switch (base) {
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case 0: op->basereg = R_EAX; break;
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case 1: op->basereg = R_ECX; break;
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case 2: op->basereg = R_EDX; break;
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case 3: op->basereg = R_EBX; break;
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case 4: op->basereg = R_ESP; break;
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case 6: op->basereg = R_ESI; break;
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case 7: op->basereg = R_EDI; break;
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case 5:
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if (mod == 0) {
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mod = 2;
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op->basereg = -1;
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} else
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op->basereg = R_EBP;
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break;
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}
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}
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switch (mod) {
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case 0:
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op->segment |= SEG_NODISP;
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break;
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case 1:
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op->segment |= SEG_DISP8;
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op->offset = (signed char) *data++;
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break;
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case 2:
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op->segment |= SEG_DISP32;
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op->offset = *data++;
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op->offset |= (*data++) << 8;
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op->offset |= ((long) *data++) << 16;
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op->offset |= ((long) *data++) << 24;
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break;
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}
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return data;
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}
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}
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/*
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* Determine whether the code string in r corresponds to the data
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* stream in data. Return the number of bytes matched if so.
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*/
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static int matches (unsigned char *r, unsigned char *data, int asize,
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int osize, int segsize, insn *ins) {
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unsigned char *origdata = data;
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int a_used = FALSE, o_used = FALSE;
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while (*r) {
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int c = *r++;
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if (c >= 01 && c <= 03) {
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while (c--)
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if (*r++ != *data++)
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return FALSE;
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}
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if (c == 04) {
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switch (*data++) {
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case 0x07: ins->oprs[0].basereg = 0; break;
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case 0x17: ins->oprs[0].basereg = 2; break;
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case 0x1F: ins->oprs[0].basereg = 3; break;
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default: return FALSE;
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}
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}
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if (c == 05) {
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switch (*data++) {
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case 0xA1: ins->oprs[0].basereg = 4; break;
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case 0xA9: ins->oprs[0].basereg = 5; break;
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default: return FALSE;
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}
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}
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if (c == 06) {
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switch (*data++) {
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case 0x06: ins->oprs[0].basereg = 0; break;
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case 0x0E: ins->oprs[0].basereg = 1; break;
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case 0x16: ins->oprs[0].basereg = 2; break;
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case 0x1E: ins->oprs[0].basereg = 3; break;
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default: return FALSE;
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}
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}
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if (c == 07) {
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switch (*data++) {
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case 0xA0: ins->oprs[0].basereg = 4; break;
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case 0xA8: ins->oprs[0].basereg = 5; break;
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default: return FALSE;
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}
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}
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if (c >= 010 && c <= 012) {
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int t = *r++, d = *data++;
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if (d < t || d > t+7)
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return FALSE;
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else {
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ins->oprs[c-010].basereg = d-t;
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ins->oprs[c-010].segment |= SEG_RMREG;
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}
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}
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if (c == 017)
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if (*data++)
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return FALSE;
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if (c >= 014 && c <= 016) {
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ins->oprs[c-014].offset = (signed char) *data++;
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ins->oprs[c-014].segment |= SEG_SIGNED;
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}
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if (c >= 020 && c <= 022)
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ins->oprs[c-020].offset = *data++;
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if (c >= 024 && c <= 026)
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ins->oprs[c-024].offset = *data++;
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if (c >= 030 && c <= 032) {
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ins->oprs[c-030].offset = *data++;
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ins->oprs[c-030].offset |= (*data++ << 8);
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}
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if (c >= 034 && c <= 036) {
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ins->oprs[c-034].offset = *data++;
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ins->oprs[c-034].offset |= (*data++ << 8);
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if (asize == 32) {
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ins->oprs[c-034].offset |= (((long) *data++) << 16);
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ins->oprs[c-034].offset |= (((long) *data++) << 24);
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}
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if (segsize != asize)
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ins->oprs[c-034].addr_size = asize;
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}
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if (c >= 040 && c <= 042) {
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ins->oprs[c-040].offset = *data++;
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ins->oprs[c-040].offset |= (*data++ << 8);
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ins->oprs[c-040].offset |= (((long) *data++) << 16);
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ins->oprs[c-040].offset |= (((long) *data++) << 24);
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}
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if (c >= 050 && c <= 052) {
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ins->oprs[c-050].offset = (signed char) *data++;
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ins->oprs[c-050].segment |= SEG_RELATIVE;
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}
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if (c >= 060 && c <= 062) {
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ins->oprs[c-060].offset = *data++;
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ins->oprs[c-060].offset |= (*data++ << 8);
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ins->oprs[c-060].segment |= SEG_RELATIVE;
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ins->oprs[c-060].segment &= ~SEG_32BIT;
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}
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if (c >= 064 && c <= 066) {
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ins->oprs[c-064].offset = *data++;
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ins->oprs[c-064].offset |= (*data++ << 8);
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if (asize == 32) {
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ins->oprs[c-064].offset |= (((long) *data++) << 16);
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ins->oprs[c-064].offset |= (((long) *data++) << 24);
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ins->oprs[c-064].segment |= SEG_32BIT;
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} else
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ins->oprs[c-064].segment &= ~SEG_32BIT;
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ins->oprs[c-064].segment |= SEG_RELATIVE;
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if (segsize != asize)
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ins->oprs[c-064].addr_size = asize;
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}
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if (c >= 070 && c <= 072) {
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ins->oprs[c-070].offset = *data++;
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ins->oprs[c-070].offset |= (*data++ << 8);
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ins->oprs[c-070].offset |= (((long) *data++) << 16);
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ins->oprs[c-070].offset |= (((long) *data++) << 24);
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ins->oprs[c-070].segment |= SEG_32BIT | SEG_RELATIVE;
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}
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if (c >= 0100 && c <= 0177) {
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int modrm = *data++;
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ins->oprs[c & 07].basereg = (modrm >> 3) & 07;
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ins->oprs[c & 07].segment |= SEG_RMREG;
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data = do_ea (data, modrm, asize, segsize,
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&ins->oprs[(c >> 3) & 07]);
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}
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if (c >= 0200 && c <= 0277) {
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int modrm = *data++;
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if (((modrm >> 3) & 07) != (c & 07))
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return FALSE; /* spare field doesn't match up */
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data = do_ea (data, modrm, asize, segsize,
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&ins->oprs[(c >> 3) & 07]);
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}
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if (c >= 0300 && c <= 0302) {
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if (asize)
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ins->oprs[c-0300].segment |= SEG_32BIT;
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else
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ins->oprs[c-0300].segment &= ~SEG_32BIT;
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a_used = TRUE;
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}
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if (c == 0310) {
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if (asize == 32)
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return FALSE;
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else
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a_used = TRUE;
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}
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if (c == 0311) {
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if (asize == 16)
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return FALSE;
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else
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a_used = TRUE;
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}
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if (c == 0312) {
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if (asize != segsize)
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return FALSE;
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else
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a_used = TRUE;
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}
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if (c == 0320) {
|
||
|
if (osize == 32)
|
||
|
return FALSE;
|
||
|
else
|
||
|
o_used = TRUE;
|
||
|
}
|
||
|
if (c == 0321) {
|
||
|
if (osize == 16)
|
||
|
return FALSE;
|
||
|
else
|
||
|
o_used = TRUE;
|
||
|
}
|
||
|
if (c == 0322) {
|
||
|
if (osize != segsize)
|
||
|
return FALSE;
|
||
|
else
|
||
|
o_used = TRUE;
|
||
|
}
|
||
|
if (c == 0330) {
|
||
|
int t = *r++, d = *data++;
|
||
|
if (d < t || d > t+15)
|
||
|
return FALSE;
|
||
|
else
|
||
|
ins->condition = d - t;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
/*
|
||
|
* Check for unused a/o prefixes.
|
||
|
*/
|
||
|
ins->nprefix = 0;
|
||
|
if (!a_used && asize != segsize)
|
||
|
ins->prefixes[ins->nprefix++] = (asize == 16 ? P_A16 : P_A32);
|
||
|
if (!o_used && osize != segsize)
|
||
|
ins->prefixes[ins->nprefix++] = (osize == 16 ? P_O16 : P_O32);
|
||
|
|
||
|
return data - origdata;
|
||
|
}
|
||
|
|
||
|
long disasm (unsigned char *data, char *output, int segsize, long offset,
|
||
|
int autosync) {
|
||
|
struct itemplate **p;
|
||
|
int length = 0;
|
||
|
char *segover;
|
||
|
int rep, lock, asize, osize, i, slen, colon;
|
||
|
unsigned char *origdata;
|
||
|
int works;
|
||
|
insn ins;
|
||
|
|
||
|
/*
|
||
|
* Scan for prefixes.
|
||
|
*/
|
||
|
asize = osize = segsize;
|
||
|
segover = NULL;
|
||
|
rep = lock = 0;
|
||
|
origdata = data;
|
||
|
for (;;) {
|
||
|
if (*data == 0xF3 || *data == 0xF2)
|
||
|
rep = *data++;
|
||
|
else if (*data == 0xF0)
|
||
|
lock = *data++;
|
||
|
else if (*data == 0x2E || *data == 0x36 || *data == 0x3E ||
|
||
|
*data == 0x26 || *data == 0x64 || *data == 0x65) {
|
||
|
switch (*data++) {
|
||
|
case 0x2E: segover = "cs"; break;
|
||
|
case 0x36: segover = "ss"; break;
|
||
|
case 0x3E: segover = "ds"; break;
|
||
|
case 0x26: segover = "es"; break;
|
||
|
case 0x64: segover = "fs"; break;
|
||
|
case 0x65: segover = "gs"; break;
|
||
|
}
|
||
|
} else if (*data == 0x66)
|
||
|
osize = 48 - segsize, data++;
|
||
|
else if (*data == 0x67)
|
||
|
asize = 48 - segsize, data++;
|
||
|
else
|
||
|
break;
|
||
|
}
|
||
|
|
||
|
ins.oprs[0].segment = ins.oprs[1].segment = ins.oprs[2].segment =
|
||
|
ins.oprs[0].addr_size = ins.oprs[1].addr_size = ins.oprs[2].addr_size =
|
||
|
(segsize == 16 ? 0 : SEG_32BIT);
|
||
|
ins.condition = -1;
|
||
|
works = TRUE;
|
||
|
for (p = itable[*data]; *p; p++)
|
||
|
if ( (length = matches((unsigned char *)((*p)->code), data,
|
||
|
asize, osize, segsize, &ins)) ) {
|
||
|
works = TRUE;
|
||
|
/*
|
||
|
* Final check to make sure the types of r/m match up.
|
||
|
*/
|
||
|
for (i = 0; i < (*p)->operands; i++)
|
||
|
if (((ins.oprs[i].segment & SEG_RMREG) &&
|
||
|
!(MEMORY & ~(*p)->opd[i])) ||
|
||
|
(!(ins.oprs[i].segment & SEG_RMREG) &&
|
||
|
!(REGNORM & ~(*p)->opd[i]) &&
|
||
|
!((*p)->opd[i] & REG_SMASK)))
|
||
|
works = FALSE;
|
||
|
if (works)
|
||
|
break;
|
||
|
}
|
||
|
if (!length || !works)
|
||
|
return 0; /* no instruction was matched */
|
||
|
|
||
|
slen = 0;
|
||
|
|
||
|
if (rep) {
|
||
|
slen += sprintf(output+slen, "rep%s ",
|
||
|
(rep == 0xF2 ? "ne" :
|
||
|
(*p)->opcode == I_CMPSB ||
|
||
|
(*p)->opcode == I_CMPSW ||
|
||
|
(*p)->opcode == I_CMPSD ||
|
||
|
(*p)->opcode == I_SCASB ||
|
||
|
(*p)->opcode == I_SCASW ||
|
||
|
(*p)->opcode == I_SCASD ? "e" : ""));
|
||
|
}
|
||
|
if (lock)
|
||
|
slen += sprintf(output+slen, "lock ");
|
||
|
for (i = 0; i < ins.nprefix; i++)
|
||
|
switch (ins.prefixes[i]) {
|
||
|
case P_A16: slen += sprintf(output+slen, "a16 "); break;
|
||
|
case P_A32: slen += sprintf(output+slen, "a32 "); break;
|
||
|
case P_O16: slen += sprintf(output+slen, "o16 "); break;
|
||
|
case P_O32: slen += sprintf(output+slen, "o32 "); break;
|
||
|
}
|
||
|
|
||
|
for (i = 0; i < elements(ico); i++)
|
||
|
if ((*p)->opcode == ico[i]) {
|
||
|
slen += sprintf(output+slen, "%s%s", icn[i],
|
||
|
whichcond(ins.condition));
|
||
|
break;
|
||
|
}
|
||
|
if (i >= elements(ico))
|
||
|
slen += sprintf(output+slen, "%s", insn_names[(*p)->opcode]);
|
||
|
colon = FALSE;
|
||
|
length += data - origdata; /* fix up for prefixes */
|
||
|
for (i=0; i<(*p)->operands; i++) {
|
||
|
output[slen++] = (colon ? ':' : i==0 ? ' ' : ',');
|
||
|
|
||
|
if (ins.oprs[i].segment & SEG_RELATIVE) {
|
||
|
ins.oprs[i].offset += offset + length;
|
||
|
/*
|
||
|
* sort out wraparound
|
||
|
*/
|
||
|
if (!(ins.oprs[i].segment & SEG_32BIT))
|
||
|
ins.oprs[i].offset &= 0xFFFF;
|
||
|
/*
|
||
|
* add sync marker, if autosync is on
|
||
|
*/
|
||
|
if (autosync)
|
||
|
add_sync (ins.oprs[i].offset, 0L);
|
||
|
}
|
||
|
|
||
|
if ((*p)->opd[i] & COLON)
|
||
|
colon = TRUE;
|
||
|
else
|
||
|
colon = FALSE;
|
||
|
|
||
|
if (((*p)->opd[i] & (REGISTER | FPUREG)) ||
|
||
|
(ins.oprs[i].segment & SEG_RMREG)) {
|
||
|
ins.oprs[i].basereg = whichreg ((*p)->opd[i],
|
||
|
ins.oprs[i].basereg);
|
||
|
slen += sprintf(output+slen, "%s",
|
||
|
reg_names[ins.oprs[i].basereg]);
|
||
|
} else if (!(UNITY & ~(*p)->opd[i])) {
|
||
|
output[slen++] = '1';
|
||
|
} else if ( (*p)->opd[i] & IMMEDIATE ) {
|
||
|
if ( (*p)->opd[i] & BITS8 ) {
|
||
|
slen += sprintf(output+slen, "byte ");
|
||
|
if (ins.oprs[i].segment & SEG_SIGNED) {
|
||
|
if (ins.oprs[i].offset < 0) {
|
||
|
ins.oprs[i].offset *= -1;
|
||
|
output[slen++] = '-';
|
||
|
} else
|
||
|
output[slen++] = '+';
|
||
|
}
|
||
|
} else if ( (*p)->opd[i] & BITS16 ) {
|
||
|
slen += sprintf(output+slen, "word ");
|
||
|
} else if ( (*p)->opd[i] & BITS32 ) {
|
||
|
slen += sprintf(output+slen, "dword ");
|
||
|
} else if ( (*p)->opd[i] & NEAR ) {
|
||
|
slen += sprintf(output+slen, "near ");
|
||
|
} else if ( (*p)->opd[i] & SHORT ) {
|
||
|
slen += sprintf(output+slen, "short ");
|
||
|
}
|
||
|
slen += sprintf(output+slen, "0x%lx", ins.oprs[i].offset);
|
||
|
} else if ( !(MEM_OFFS & ~(*p)->opd[i]) ) {
|
||
|
slen += sprintf(output+slen, "[%s%s%s0x%lx]",
|
||
|
(segover ? segover : ""),
|
||
|
(segover ? ":" : ""),
|
||
|
(ins.oprs[i].addr_size == 32 ? "dword " :
|
||
|
ins.oprs[i].addr_size == 16 ? "word " : ""),
|
||
|
ins.oprs[i].offset);
|
||
|
segover = NULL;
|
||
|
} else if ( !(REGMEM & ~(*p)->opd[i]) ) {
|
||
|
int started = FALSE;
|
||
|
if ( (*p)->opd[i] & BITS8 )
|
||
|
slen += sprintf(output+slen, "byte ");
|
||
|
if ( (*p)->opd[i] & BITS16 )
|
||
|
slen += sprintf(output+slen, "word ");
|
||
|
if ( (*p)->opd[i] & BITS32 )
|
||
|
slen += sprintf(output+slen, "dword ");
|
||
|
if ( (*p)->opd[i] & BITS64 )
|
||
|
slen += sprintf(output+slen, "qword ");
|
||
|
if ( (*p)->opd[i] & BITS80 )
|
||
|
slen += sprintf(output+slen, "tword ");
|
||
|
if ( (*p)->opd[i] & FAR )
|
||
|
slen += sprintf(output+slen, "far ");
|
||
|
if ( (*p)->opd[i] & NEAR )
|
||
|
slen += sprintf(output+slen, "near ");
|
||
|
output[slen++] = '[';
|
||
|
if (ins.oprs[i].addr_size)
|
||
|
slen += sprintf(output+slen, "%s",
|
||
|
(ins.oprs[i].addr_size == 32 ? "dword " :
|
||
|
ins.oprs[i].addr_size == 16 ? "word " : ""));
|
||
|
if (segover) {
|
||
|
slen += sprintf(output+slen, "%s:", segover);
|
||
|
segover = NULL;
|
||
|
}
|
||
|
if (ins.oprs[i].basereg != -1) {
|
||
|
slen += sprintf(output+slen, "%s",
|
||
|
reg_names[ins.oprs[i].basereg]);
|
||
|
started = TRUE;
|
||
|
}
|
||
|
if (ins.oprs[i].indexreg != -1) {
|
||
|
if (started)
|
||
|
output[slen++] = '+';
|
||
|
slen += sprintf(output+slen, "%s",
|
||
|
reg_names[ins.oprs[i].indexreg]);
|
||
|
if (ins.oprs[i].scale > 1)
|
||
|
slen += sprintf(output+slen, "*%d", ins.oprs[i].scale);
|
||
|
started = TRUE;
|
||
|
}
|
||
|
if (ins.oprs[i].segment & SEG_DISP8) {
|
||
|
int sign = '+';
|
||
|
if (ins.oprs[i].offset & 0x80) {
|
||
|
ins.oprs[i].offset = - (signed char) ins.oprs[i].offset;
|
||
|
sign = '-';
|
||
|
}
|
||
|
slen += sprintf(output+slen, "%c0x%lx", sign,
|
||
|
ins.oprs[i].offset);
|
||
|
} else if (ins.oprs[i].segment & SEG_DISP16) {
|
||
|
if (started)
|
||
|
output[slen++] = '+';
|
||
|
slen += sprintf(output+slen, "0x%lx", ins.oprs[i].offset);
|
||
|
} else if (ins.oprs[i].segment & SEG_DISP32) {
|
||
|
if (started)
|
||
|
output[slen++] = '+';
|
||
|
slen += sprintf(output+slen, "0x%lx", ins.oprs[i].offset);
|
||
|
}
|
||
|
output[slen++] = ']';
|
||
|
} else {
|
||
|
slen += sprintf(output+slen, "<operand%d>", i);
|
||
|
}
|
||
|
}
|
||
|
output[slen] = '\0';
|
||
|
if (segover) { /* unused segment override */
|
||
|
char *p = output;
|
||
|
int count = slen+1;
|
||
|
while (count--)
|
||
|
p[count+3] = p[count];
|
||
|
strncpy (output, segover, 2);
|
||
|
output[2] = ' ';
|
||
|
}
|
||
|
return length;
|
||
|
}
|
||
|
|
||
|
long eatbyte (unsigned char *data, char *output) {
|
||
|
sprintf(output, "db 0x%02X", *data);
|
||
|
return 1;
|
||
|
}
|