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nasm/test/mpx-64.asm

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MPX: Add test cases for MPX MPX test asm files are added. These include all three different styles of mib syntax (NASM, ICC and gas). Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-10-16 10:42:41 +08:00
;Testname=mpx-64; Arguments=-felf64 -ompx-64.o -O0; Files=stdout stderr mpx-64.o
BITS 64
bndmk bnd1, [r11]
bndmk bnd1, [rax]
bndmk bnd1, [0x399]
bndmk bnd1, [r9+0x3]
bndmk bnd1, [rax+0x3]
bndmk bnd1, [3,1*r12]
bndmk bnd1, [rax+rcx]
bndmk bnd1, [r11+1*rax+0x3]
bndmk bnd1, [rbx+1*r9+0x3]
; bndmov
bndmov bnd1, [r11]
bndmov bnd1, [rax]
bndmov bnd1, [0x399]
bndmov bnd2, [r9+0x3]
bndmov bnd2, [rax+0x3]
bndmov bnd0, [1*r12+0x3]
bndmov bnd2, [rax+rdx]
bndmov bnd1, [r11+1*rax+0x3]
bndmov bnd1, [rbx+1*r9+0x3]
bndmov bnd0, bnd2
bndmov [r11], bnd1
bndmov [rax], bnd1
bndmov [0x399], bnd1
bndmov [r9+0x3], bnd2
bndmov [rax+0x3], bnd2
bndmov [1*r12+0x3], bnd0
bndmov [rax+rdx], bnd2
bndmov [r11+1*rax+0x3], bnd1
bndmov [rbx+1*r9+0x3], bnd1
bndmov bnd2, bnd0
; bndcl
bndcl bnd1, [r11]
bndcl bnd1, [rax]
bndcl bnd1, r11
bndcl bnd1, rcx
bndcl bnd1, [0x399]
bndcl bnd1, [r9+0x3]
bndcl bnd1, [rax+0x3]
bndcl bnd1, [1*r12+0x3]
bndcl bnd1, [rax+rcx]
bndcl bnd1, [r11+1*rax+0x3]
bndcl bnd1, [rbx+1*r9+0x3]
; bndcu
bndcu bnd1, [r11]
bndcu bnd1, [rax]
bndcu bnd1, r11
bndcu bnd1, rcx
bndcu bnd1, [0x399]
bndcu bnd1, [r9+0x3]
bndcu bnd1, [rax+0x3]
bndcu bnd1, [1*r12+0x3]
bndcu bnd1, [rax+rcx]
bndcu bnd1, [r11+1*rax+0x3]
bndcu bnd1, [rbx+1*r9+0x3]
; bndcn
bndcn bnd1, [r11]
bndcn bnd1, [rax]
bndcn bnd1, r11
bndcn bnd1, rcx
bndcn bnd1, [0x399]
bndcn bnd1, [r9+0x3]
bndcn bnd1, [rax+0x3]
bndcn bnd1, [1*r9+0x3]
bndcn bnd1, [rax+rcx]
bndcn bnd1, [r11+1*rax+0x3]
bndcn bnd1, [rbx+1*r9+0x3]
; bndstx
; next 5 lines should be parsed same
bndstx [rax+0x3,rbx], bnd0 ; NASM - split EA
bndstx [rax+rbx*1+0x3], bnd0 ; GAS
bndstx [rax+rbx+3], bnd0 ; GAS
bndstx [rax+0x3], bnd0, rbx ; ICC-1
bndstx [rax+0x3], rbx, bnd0 ; ICC-2
MPX: Adapt GAS's mib syntax with an index reg only GAS uses *1 multiplier for explicitly marking an index register in mib operand. e.g.) [rdx * 1 + 3] is equivalent to [3, rdx] in NASM's split EA format So only for mib operands, this is encoded same as gas does. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-09 03:41:12 +08:00
; next 5 lines should be parsed same
MPX: Add test cases for MPX MPX test asm files are added. These include all three different styles of mib syntax (NASM, ICC and gas). Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-10-16 10:42:41 +08:00
bndstx [,rcx*1], bnd2 ; NASM
bndstx [0,rcx*1], bnd2 ; NASM
bndstx [0], bnd2, rcx ; ICC-1
bndstx [0], rcx, bnd2 ; ICC-2
MPX: Adapt GAS's mib syntax with an index reg only GAS uses *1 multiplier for explicitly marking an index register in mib operand. e.g.) [rdx * 1 + 3] is equivalent to [3, rdx] in NASM's split EA format So only for mib operands, this is encoded same as gas does. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-09 03:41:12 +08:00
bndstx [rcx*1], bnd2 ; GAS - rcx is encoded as index only when it is mib
MPX: Add test cases for MPX MPX test asm files are added. These include all three different styles of mib syntax (NASM, ICC and gas). Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-10-16 10:42:41 +08:00
MPX: Adapt GAS's mib syntax with an index reg only GAS uses *1 multiplier for explicitly marking an index register in mib operand. e.g.) [rdx * 1 + 3] is equivalent to [3, rdx] in NASM's split EA format So only for mib operands, this is encoded same as gas does. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-09 03:41:12 +08:00
; next 3 lines should be parsed same
MPX: Add test cases for MPX MPX test asm files are added. These include all three different styles of mib syntax (NASM, ICC and gas). Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-10-16 10:42:41 +08:00
bndstx [3,1*r12], bnd2 ; NASM
MPX: Adapt GAS's mib syntax with an index reg only GAS uses *1 multiplier for explicitly marking an index register in mib operand. e.g.) [rdx * 1 + 3] is equivalent to [3, rdx] in NASM's split EA format So only for mib operands, this is encoded same as gas does. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-09 03:41:12 +08:00
bndstx [1*r12+3], bnd2 ; GAS
MPX: Add test cases for MPX MPX test asm files are added. These include all three different styles of mib syntax (NASM, ICC and gas). Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-10-16 10:42:41 +08:00
bndstx [3], r12, bnd2 ; ICC
bndstx [r12+0x399], bnd3
bndstx [r11+0x1234], bnd1
bndstx [rbx+0x1234], bnd2
bndstx [rdx], bnd1
; bndldx
bndldx bnd0, [rax+rbx*1+0x3]
bndldx bnd2, [rbx+rdx+3]
bndldx bnd3, [r12+0x399]
bndldx bnd1, [r11+0x1234]
bndldx bnd2, [rbx+0x1234]
bndldx bnd2, [1*rbx+3]
bndldx bnd2, [1*r12+3]
bndldx bnd1, [rdx]
; bnd
bnd ret
bnd call foo
bnd: Drop bnd prefix for relaxed short jmp instructions Reverted the redundant branch instruction patterns for bnd prefix. And when a relaxed jmp instruction becomes a short (Jb) form, bnd prefix is not needed because it does not initialize bnd registers. So in that case, bnd prefix is silently dropped. BND JMP foo -> drops bnd prefix BND JMP short foo -> shows an explicit error Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-22 11:40:42 +08:00
bnd jmp foo ; when it becomes a Jb form - short jmp (eb),
; bnd prefix is silently dropped
bnd jmp near 0 ; near jmp (opcode e9)
; bnd jmp short 0 ; explicit short jmp (opcode eb) : error
MPX: Add test cases for MPX MPX test asm files are added. These include all three different styles of mib syntax (NASM, ICC and gas). Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-10-16 10:42:41 +08:00
bnd jno foo
foo: bnd ret
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