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nasm/test/avx.asm

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Add automation to avx test.
2008-05-21 19:33:26 +08:00
;Testname=unoptimized; Arguments=-O0 -fbin -oavx.bin; Files=.stdout .stderr avx.bin
;Testname=optimized; Arguments=-Ox -fbin -oavx.bin; Files=.stdout .stderr avx.bin
First cut at AVX machinery. First cut at AVX machinery support. The only instruction implemented is VPERMIL2PS, and it's probably buggy. I'm checking this in with the hope that other people can start helping out with (a) testing this, and (b) adding instructions. NDISASM support is not there yet.
2008-05-05 08:53:31 +08:00
bits 64
Add legacy blendvpd to avx.asm, as a disassembler test.
2008-05-22 06:03:26 +08:00
blendvpd xmm2,xmm1,xmm0
Handle is4 bytes without meaningful information in the bottom bits Support is4 bytes without meaningful information in the bottom bits. This is equivalent to /is4=0 for the assembler, but makes the bottom bits don't care for the disassembler.
2008-05-21 10:29:04 +08:00
vblendvpd xmm2,xmm1,xmm0,xmm0
vblendvpd xmm2,xmm1,xmm0
vblendvpd ymm2,ymm1,ymm0,ymm0
vblendvpd ymm2,ymm1,ymm0
vcvtsi2sd xmm9,xmm10,ecx
vcvtsi2sd xmm9,xmm10,rcx
vcvtsi2sd xmm9,xmm10,dword [rdi]
avx.bin: clean up screwy whitespace
2008-05-27 13:52:57 +08:00
vcvtsi2sd xmm9,xmm10,qword [rdi]
Handle is4 bytes without meaningful information in the bottom bits Support is4 bytes without meaningful information in the bottom bits. This is equivalent to /is4=0 for the assembler, but makes the bottom bits don't care for the disassembler.
2008-05-21 10:29:04 +08:00
First cut at AVX machinery. First cut at AVX machinery support. The only instruction implemented is VPERMIL2PS, and it's probably buggy. I'm checking this in with the hope that other people can start helping out with (a) testing this, and (b) adding instructions. NDISASM support is not there yet.
2008-05-05 08:53:31 +08:00
vpermil2ps xmm0,xmm1,[rdi],xmm3,0
vpermil2ps xmm0,xmm1,xmm2,[rdi],1
vpermil2ps ymm0,ymm1,ymm2,ymm3,2
vpermil2ps ymm0,ymm1,ymm2,[rdi],3
vpermil2ps ymm0,ymm1,[rdi],ymm3,2
vpermil2ps ymm0,ymm1,ymm2,[rdi],3
AVX: instruction table up to PE Complete the instruction table up to and including PE (document 319433-002, start next on page 5-330).
2008-05-22 14:21:57 +08:00
vpextrb [rax],xmm1,0x33
vpextrw [rax],xmm1,0x33
vpextrd [rax],xmm1,0x33
vpextrq [rax],xmm1,0x33
vpextrb rax,xmm1,0x33
vpextrw rax,xmm1,0x33
vpextrd rax,xmm1,0x33
vpextrq rax,xmm1,0x33
vpextrb eax,xmm1,0x33
vpextrw eax,xmm1,0x33
vpextrd eax,xmm1,0x33
; vpextrq eax,xmm1,0x33
VCVTPD2PS, VCVTPD2DQ, VCVTTPD2DQ mem need explicit op size (BR 1974170) BR 1974170: VCVTPD2PS, VCVTPD2DQ, VCVTTPD2DQ with a memory operand are ambiguous without a specific operand size, so force one to be added. Split the instruction pattern due to our current clunky handling of MMX/XMM/YMM registers together with sizes. Fix in the future, please!
2008-05-27 13:48:51 +08:00
vcvtpd2ps xmm0,xmm1
vcvtpd2ps xmm0,oword [rsi]
vcvtpd2ps xmm0,ymm1
vcvtpd2ps xmm0,yword [rsi]
; vcvtpd2ps xmm0,[rsi]
vcvtpd2dq xmm0,xmm1
vcvtpd2dq xmm0,oword [rsi]
vcvtpd2dq xmm0,ymm1
vcvtpd2dq xmm0,yword [rsi]
; vcvtpd2dq xmm0,[rsi]
vcvttpd2dq xmm0,xmm1
vcvttpd2dq xmm0,oword [rsi]
vcvttpd2dq xmm0,ymm1
vcvttpd2dq xmm0,yword [rsi]
; vcvttpd2dq xmm0,[rsi]
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