Commit Graph

106 Commits

Author SHA1 Message Date
Quincey Koziol
427ff7da28 [svn-r9727] Purpose:
Bug Fix/Code Cleanup/Doc Cleanup/Optimization/Branch Sync :-)

Description:
    Generally speaking, this is the "signed->unsigned" change to selections.
However, in the process of merging code back, things got stickier and stickier
until I ended up doing a big "sync the two branches up" operation.  So... I
brought back all the "infrastructure" fixes from the development branch to the
release branch (which I think were actually making some improvement in
performance) as well as fixed several bugs which had been fixed in one branch,
but not the other.

    I've also tagged the repository before making this checkin with the label
"before_signed_unsigned_changes".

Platforms tested:
    FreeBSD 4.10 (sleipnir) w/parallel & fphdf5
    FreeBSD 4.10 (sleipnir) w/threadsafe
    FreeBSD 4.10 (sleipnir) w/backward compatibility
    Solaris 2.7 (arabica) w/"purify options"
    Solaris 2.8 (sol) w/FORTRAN & C++
    AIX 5.x (copper) w/parallel & FORTRAN
    IRIX64 6.5 (modi4) w/FORTRAN
    Linux 2.4 (heping) w/FORTRAN & C++


Misc. update:
2004-12-29 09:26:20 -05:00
John Mainzer
5c415042a3 [svn-r9687] Purpose:
Modify the cache code (H5C) to support automatic cache resizing to
adapt to the work load at run time.


Description:

   Different applications require different sized caches to maintain
an acceptable hit rate.  This set of changes attempts to provide the
ability to adjust to circumstances automatically.


Solution:

   Added highly configurable code to allow the user to either set a
fixed cache size, or allow the cache to grow and shrink according to
conditions.

   If enabled, cache size increases are triggered when the hit rate
drops below a user specified threshold in a user specified interval.

   Cache size reductions (if enabled) are triggered when either the
hit rate exceeds some user specified threshold over a user specified
interval, when the cache contains "enough" entries that haven't been
accessed for a user specified interval, or some mix of the above.

   See the header comments on the H5C_auto_size_ctl_t structure in
H5Cprivate.h for further details.

   At present, the cache resize configuration options are not
accessible via the user API.  Must add this.


Platforms tested:

   h5committested, heping (serial), and copper (parallel)


Misc. update:
2004-12-17 20:30:34 -05:00
John Mainzer
5d05a022f9 [svn-r9023] *** empty log message *** 2004-08-05 13:14:21 -05:00
Quincey Koziol
c97fddc786 [svn-r8892] Purpose:
Code cleanup

Description:
    Clean up a bunch of warnings and bring new code better inline with current
library coding practice.

Platforms tested:
    FreeBSD 4.10 (sleipnir) w/parallel
    Too minor to require h5committest

Misc. update:
2004-07-16 15:48:40 -05:00
Quincey Koziol
153444fed7 [svn-r8800] Purpose:
Code cleanup

Description:
    Fix problems when compiling with C++ compiler.

    Also clean up some warnings with gcc 3.4.x

Platforms tested:
    FreeBSD 4.10 (sleipnir)
    Too minor to require h5committest
2004-07-03 12:00:01 -05:00
John Mainzer
c49dd7fa36 [svn-r8791] Purpose: Rewrote metadata cache (H5AC.c, etc.) to improve performance.
Description:

Replaced the old metadata cache with a cache with a modified LRU
replacement policy.  This should improve the hit rate.

Solution:

Since we want to flush cache entries in increasing address order, I
used the threaded binary B-tree code to store the cache entries.
There is a fair bit of overhead here, so we may want to consider
other options.

While the code is designed to allow the support of other replacement
algorithms, at present, only a modified version of LRU is supported.

The modified LRU algorithm requires that a user selectable portion
of the cache entries be clean.  The clean entries are evicted first
when writes are not permitted.  If the pool of clean entries is used
up, the cache grows beyond its user specified maximum size.  The
cache can also exceed its maximum size if the combined size of the
protected (or locked) entries exceeds the maximum size of the cache.


Platforms tested:

eirene (serial, parallel, fp), h5committested


Misc. update:
2004-07-02 14:35:04 -05:00