glibc/sysdeps/riscv
Khem Raj ff03b5efe6 riscv: Update ulps
Generated with make regen-ulps using gcc14 on a visionfive2 SBC.

Signed-off-by: Khem Raj <raj.khem@gmail.com>
2024-07-25 10:28:44 -03:00
..
bits
multiarch
nofpu riscv: Update nofpu libm test ulps 2024-07-03 21:05:34 +02:00
nptl
rv32
rv64
rvd riscv: Update ulps 2024-07-25 10:28:44 -03:00
rvf
sys
__longjmp.S
bsd-_setjmp.c
bsd-setjmp.c
configure
configure.ac
dl-irel.h
dl-link.sym
dl-machine.h
dl-relocate-ld.h
dl-tls.h
dl-trampoline.S
e_sqrtl.c
fpu_control.h
gccframe.h
Implies
jmpbuf-offsets.h
jmpbuf-unwind.h
ldsodefs.h
libc-tls.c
linkmap.h
machine-gmon.h
Makefile
math-tests-snan-payload.h
math-tests-trap.h
preconfigure
preconfigure.ac
riscv-ifunc.h
setjmp.S
sfp-machine.h
sotruss-lib.c
stackinfo.h
start.S
string-fza.h
string-fzi.h
tininess.h
tst-audit.h
utmp-size.h