mirror of
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59261ad3eb
In bc0cdc498 the configure check for HAVE_ASM_PPC_REL16 was removed
on the grounds that the minimum binutils supports rel16 relocs. This
is true, but not all references to HAVE_ASM_PPC_REL16 in the sources
were removed.
* config.h.in: Remove HAVE_ASM_PPC_REL16.
* sysdeps/powerpc/powerpc32/tls-macros.h: Remove HAVE_ASM_PPC_REL16
and false branch of conditional.
* sysdeps/unix/sysv/linux/powerpc/powerpc32/swapcontext-common.S:
Likewise.
529 lines
12 KiB
ArmAsm
529 lines
12 KiB
ArmAsm
/* Save current context and jump to a new context.
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Copyright (C) 2005-2015 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<http://www.gnu.org/licenses/>. */
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/* This is the common implementation of setcontext for powerpc32.
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It not complete in itself should be included in to a framework that
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defines:
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__CONTEXT_FUNC_NAME
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and if appropriate:
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__CONTEXT_ENABLE_FPRS
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__CONTEXT_ENABLE_VRS
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Any architecture that implements the Vector unit is assumed to also
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implement the floating unit. */
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/* Stack frame offsets. */
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#define _FRAME_BACKCHAIN 0
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#define _FRAME_LR_SAVE 4
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#define _FRAME_PARM_SAVE1 8
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#define _FRAME_PARM_SAVE2 12
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#define _FRAME_PARM_SAVE3 16
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#define _FRAME_PARM_SAVE4 20
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#ifdef __CONTEXT_ENABLE_VRS
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.machine "altivec"
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#endif
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ENTRY(__CONTEXT_FUNC_NAME)
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stwu r1,-16(r1)
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cfi_adjust_cfa_offset (16)
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/* Insure that the _UC_REGS start on a quadword boundary. */
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stw r3,_FRAME_PARM_SAVE1(r1)
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addi r3,r3,_UC_REG_SPACE+12
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stw r4,_FRAME_PARM_SAVE2(r1) /* new context pointer */
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clrrwi r3,r3,4
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/* Save the general purpose registers */
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stw r0,_UC_GREGS+(PT_R0*4)(r3)
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mflr r0
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stw r2,_UC_GREGS+(PT_R2*4)(r3)
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stw r4,_UC_GREGS+(PT_R4*4)(r3)
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/* Set the callers LR_SAVE, and the ucontext LR and NIP to the callers
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return address. */
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stw r0,_UC_GREGS+(PT_LNK*4)(r3)
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stw r0,_UC_GREGS+(PT_NIP*4)(r3)
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stw r0,_FRAME_LR_SAVE+16(r1)
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cfi_offset (lr, _FRAME_LR_SAVE)
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stw r5,_UC_GREGS+(PT_R5*4)(r3)
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stw r6,_UC_GREGS+(PT_R6*4)(r3)
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stw r7,_UC_GREGS+(PT_R7*4)(r3)
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stw r8,_UC_GREGS+(PT_R8*4)(r3)
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stw r9,_UC_GREGS+(PT_R9*4)(r3)
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stw r10,_UC_GREGS+(PT_R10*4)(r3)
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stw r11,_UC_GREGS+(PT_R11*4)(r3)
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stw r12,_UC_GREGS+(PT_R12*4)(r3)
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stw r13,_UC_GREGS+(PT_R13*4)(r3)
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stw r14,_UC_GREGS+(PT_R14*4)(r3)
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stw r15,_UC_GREGS+(PT_R15*4)(r3)
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stw r16,_UC_GREGS+(PT_R16*4)(r3)
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stw r17,_UC_GREGS+(PT_R17*4)(r3)
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stw r18,_UC_GREGS+(PT_R18*4)(r3)
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stw r19,_UC_GREGS+(PT_R19*4)(r3)
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stw r20,_UC_GREGS+(PT_R20*4)(r3)
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stw r21,_UC_GREGS+(PT_R21*4)(r3)
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stw r22,_UC_GREGS+(PT_R22*4)(r3)
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stw r23,_UC_GREGS+(PT_R23*4)(r3)
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stw r24,_UC_GREGS+(PT_R24*4)(r3)
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stw r25,_UC_GREGS+(PT_R25*4)(r3)
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stw r26,_UC_GREGS+(PT_R26*4)(r3)
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stw r27,_UC_GREGS+(PT_R27*4)(r3)
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stw r28,_UC_GREGS+(PT_R28*4)(r3)
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stw r29,_UC_GREGS+(PT_R29*4)(r3)
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stw r30,_UC_GREGS+(PT_R30*4)(r3)
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stw r31,_UC_GREGS+(PT_R31*4)(r3)
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/* Save the value of R1. We had to push the stack before we
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had the address of uc_reg_space. So compute the address of
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the callers stack pointer and save it as R1. */
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addi r8,r1,16
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li r0,0
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/* Save the count, exception and condition registers. */
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mfctr r11
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mfxer r10
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mfcr r9
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stw r8,_UC_GREGS+(PT_R1*4)(r3)
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stw r11,_UC_GREGS+(PT_CTR*4)(r3)
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stw r10,_UC_GREGS+(PT_XER*4)(r3)
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stw r9,_UC_GREGS+(PT_CCR*4)(r3)
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/* Set the return value of getcontext to "success". R3 is the only
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register whose value is not preserved in the saved context. */
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stw r0,_UC_GREGS+(PT_R3*4)(r3)
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/* Zero fill fields that can't be set in user state. */
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stw r0,_UC_GREGS+(PT_MSR*4)(r3)
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stw r0,_UC_GREGS+(PT_MQ*4)(r3)
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#ifdef __CONTEXT_ENABLE_FPRS
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/* Save the floating-point registers */
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stfd fp0,_UC_FREGS+(0*8)(r3)
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stfd fp1,_UC_FREGS+(1*8)(r3)
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stfd fp2,_UC_FREGS+(2*8)(r3)
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stfd fp3,_UC_FREGS+(3*8)(r3)
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stfd fp4,_UC_FREGS+(4*8)(r3)
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stfd fp5,_UC_FREGS+(5*8)(r3)
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stfd fp6,_UC_FREGS+(6*8)(r3)
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stfd fp7,_UC_FREGS+(7*8)(r3)
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stfd fp8,_UC_FREGS+(8*8)(r3)
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stfd fp9,_UC_FREGS+(9*8)(r3)
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stfd fp10,_UC_FREGS+(10*8)(r3)
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stfd fp11,_UC_FREGS+(11*8)(r3)
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stfd fp12,_UC_FREGS+(12*8)(r3)
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stfd fp13,_UC_FREGS+(13*8)(r3)
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stfd fp14,_UC_FREGS+(14*8)(r3)
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stfd fp15,_UC_FREGS+(15*8)(r3)
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stfd fp16,_UC_FREGS+(16*8)(r3)
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stfd fp17,_UC_FREGS+(17*8)(r3)
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stfd fp18,_UC_FREGS+(18*8)(r3)
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stfd fp19,_UC_FREGS+(19*8)(r3)
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stfd fp20,_UC_FREGS+(20*8)(r3)
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stfd fp21,_UC_FREGS+(21*8)(r3)
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stfd fp22,_UC_FREGS+(22*8)(r3)
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stfd fp23,_UC_FREGS+(23*8)(r3)
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stfd fp24,_UC_FREGS+(24*8)(r3)
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stfd fp25,_UC_FREGS+(25*8)(r3)
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stfd fp26,_UC_FREGS+(26*8)(r3)
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stfd fp27,_UC_FREGS+(27*8)(r3)
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stfd fp28,_UC_FREGS+(28*8)(r3)
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stfd fp29,_UC_FREGS+(29*8)(r3)
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mffs fp0
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stfd fp30,_UC_FREGS+(30*8)(r3)
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stfd fp31,_UC_FREGS+(31*8)(r3)
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stfd fp0,_UC_FREGS+(32*8)(r3)
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# ifdef PIC
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mflr r8
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# define got_label GENERATE_GOT_LABEL (__CONTEXT_FUNC_NAME)
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SETUP_GOT_ACCESS(r7,got_label)
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addis r7,r7,_GLOBAL_OFFSET_TABLE_-got_label@ha
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addi r7,r7,_GLOBAL_OFFSET_TABLE_-got_label@l
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# ifdef SHARED
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lwz r7,_rtld_global_ro@got(r7)
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mtlr r8
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lwz r7,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET+LOWORD(r7)
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# else
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lwz r7,_dl_hwcap@got(r7)
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mtlr r8
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lwz r7,LOWORD(r7)
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# endif
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# else
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lis r7,(_dl_hwcap+LOWORD)@ha
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lwz r7,(_dl_hwcap+LOWORD)@l(r7)
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# endif
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# ifdef __CONTEXT_ENABLE_VRS
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andis. r6,r7,(PPC_FEATURE_HAS_ALTIVEC >> 16)
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la r10,(_UC_VREGS)(r3)
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la r9,(_UC_VREGS+16)(r3)
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/* beq L(no_vec)*/
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beq 2f
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/* address of the combined VSCR/VSAVE quadword. */
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la r8,(_UC_VREGS+512)(r3)
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/* Save the vector registers */
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stvx v0,0,r10
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stvx v1,0,r9
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addi r10,r10,32
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addi r9,r9,32
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/* We need to get the Vector Status and Control Register early to avoid
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store order problems later with the VSAVE register that shares the
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same quadword. */
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mfvscr v0
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stvx v2,0,r10
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stvx v3,0,r9
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addi r10,r10,32
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addi r9,r9,32
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stvx v0,0,r8
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stvx v4,0,r10
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stvx v5,0,r9
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addi r10,r10,32
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addi r9,r9,32
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stvx v6,0,r10
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stvx v7,0,r9
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addi r10,r10,32
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addi r9,r9,32
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stvx v8,0,r10
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stvx v9,0,r9
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addi r10,r10,32
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addi r9,r9,32
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stvx v10,0,r10
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stvx v11,0,r9
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addi r10,r10,32
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addi r9,r9,32
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stvx v12,0,r10
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stvx v13,0,r9
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addi r10,r10,32
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addi r9,r9,32
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stvx v14,0,r10
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stvx v15,0,r9
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addi r10,r10,32
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addi r9,r9,32
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stvx v16,0,r10
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stvx v17,0,r9
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addi r10,r10,32
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addi r9,r9,32
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stvx v18,0,r10
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stvx v19,0,r9
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addi r10,r10,32
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addi r9,r9,32
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stvx v20,0,r10
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stvx v21,0,r9
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addi r10,r10,32
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addi r9,r9,32
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stvx v22,0,r10
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stvx v23,0,r9
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addi r10,r10,32
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addi r9,r9,32
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stvx v24,0,r10
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stvx v25,0,r9
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addi r10,r10,32
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addi r9,r9,32
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stvx v26,0,r10
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stvx v27,0,r9
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addi r10,r10,32
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addi r9,r9,32
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stvx v28,0,r10
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stvx v29,0,r9
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addi r10,r10,32
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addi r9,r9,32
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mfvscr v0
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stvx v30,0,r10
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stvx v31,0,r9
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stw r0,0(r8)
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2: /*L(no_vec):*/
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# endif /* __CONTEXT_ENABLE_VRS */
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#endif /* __CONTEXT_ENABLE_FPRS */
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#ifdef __CONTEXT_ENABLE_E500
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getcontext_e500
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#endif
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/* Restore ucontext (parm1) from stack. */
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lwz r12,_FRAME_PARM_SAVE1(r1)
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li r4,0
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stw r3,_UC_REGS_PTR(r12)
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addi r5,r12,_UC_SIGMASK
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li r3,SIG_SETMASK
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bl __sigprocmask@local
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cmpwi r3,0
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bne 3f /* L(error_exit) */
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/*
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* If the new ucontext refers to the point where we were interrupted
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* by a signal, we have to use the rt_sigreturn system call to
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* return to the context so we get both LR and CTR restored.
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*
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* Otherwise, the context we are restoring is either just after
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* a procedure call (getcontext/swapcontext) or at the beginning
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* of a procedure call (makecontext), so we don't need to restore
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* r0, xer, ctr. We don't restore r2 since it will be used as
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* the TLS pointer.
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*/
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lwz r4,_FRAME_PARM_SAVE2(r1)
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lwz r31,_UC_REGS_PTR(r4)
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lwz r0,_UC_GREGS+(PT_MSR*4)(r31)
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cmpwi r0,0
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bne 4f /* L(do_sigret) */
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#ifdef __CONTEXT_ENABLE_FPRS
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# ifdef __CONTEXT_ENABLE_VRS
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# ifdef PIC
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mflr r8
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SETUP_GOT_ACCESS(r7,got_label)
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addis r7,r7,_GLOBAL_OFFSET_TABLE_-got_label@ha
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addi r7,r7,_GLOBAL_OFFSET_TABLE_-got_label@l
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mtlr r8
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# ifdef SHARED
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lwz r7,_rtld_global_ro@got(r7)
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lwz r7,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET+LOWORD(r7)
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# else
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lwz r7,_dl_hwcap@got(r7)
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lwz r7,LOWORD(r7)
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# endif
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# else
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lis r7,(_dl_hwcap+LOWORD)@ha
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lwz r7,(_dl_hwcap+LOWORD)@l(r7)
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# endif
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andis. r7,r7,(PPC_FEATURE_HAS_ALTIVEC >> 16)
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la r10,(_UC_VREGS)(r31)
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beq 6f /* L(has_no_vec) */
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lwz r0,(32*16)(r10)
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li r9,(32*16)
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cmpwi r0,0
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mtspr VRSAVE,r0
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beq 6f /* L(has_no_vec) */
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lvx v19,r9,r10
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la r9,(16)(r10)
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lvx v0,0,r10
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lvx v1,0,r9
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addi r10,r10,32
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addi r9,r9,32
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mtvscr v19
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lvx v2,0,r10
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lvx v3,0,r9
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addi r10,r10,32
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addi r9,r9,32
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lvx v4,0,r10
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lvx v5,0,r9
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addi r10,r10,32
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addi r9,r9,32
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lvx v6,0,r10
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lvx v7,0,r9
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addi r10,r10,32
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addi r9,r9,32
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lvx v8,0,r10
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lvx v9,0,r9
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addi r10,r10,32
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addi r9,r9,32
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lvx v10,0,r10
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lvx v11,0,r9
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addi r10,r10,32
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addi r9,r9,32
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lvx v12,0,r10
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lvx v13,0,r9
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addi r10,r10,32
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addi r9,r9,32
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lvx v14,0,r10
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lvx v15,0,r9
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addi r10,r10,32
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addi r9,r9,32
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lvx v16,0,r10
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lvx v17,0,r9
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addi r10,r10,32
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addi r9,r9,32
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lvx v18,0,r10
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lvx v19,0,r9
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addi r10,r10,32
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addi r9,r9,32
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lvx v20,0,r10
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lvx v21,0,r9
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addi r10,r10,32
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addi r9,r9,32
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lvx v22,0,r10
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lvx v23,0,r9
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addi r10,r10,32
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addi r9,r9,32
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lvx v24,0,r10
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lvx v25,0,r9
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addi r10,r10,32
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addi r9,r9,32
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lvx v26,0,r10
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lvx v27,0,r9
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addi r10,r10,32
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addi r9,r9,32
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lvx v28,0,r10
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lvx v29,0,r9
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addi r10,r10,32
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addi r9,r9,32
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lvx v30,0,r10
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lvx v31,0,r9
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addi r10,r10,32
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addi r9,r9,32
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lvx v10,0,r10
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lvx v11,0,r9
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6: /* L(has_no_vec): */
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# endif /* __CONTEXT_ENABLE_VRS */
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/* Restore the floating-point registers */
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lfd fp31,_UC_FREGS+(32*8)(r31)
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lfd fp0,_UC_FREGS+(0*8)(r31)
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# ifdef _ARCH_PWR6
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/* Use the extended four-operand version of the mtfsf insn. */
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mtfsf 0xff,fp31,1,0
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# else
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.machine push
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.machine "power6"
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/* Availability of DFP indicates a 64-bit FPSCR. */
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andi. r6,r7,PPC_FEATURE_HAS_DFP
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beq 7f
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/* Use the extended four-operand version of the mtfsf insn. */
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mtfsf 0xff,fp31,1,0
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b 8f
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/* Continue to operate on the FPSCR as if it were 32-bits. */
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7: mtfsf 0xff,fp31
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8: .machine pop
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#endif /* _ARCH_PWR6 */
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lfd fp1,_UC_FREGS+(1*8)(r31)
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lfd fp2,_UC_FREGS+(2*8)(r31)
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lfd fp3,_UC_FREGS+(3*8)(r31)
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|
lfd fp4,_UC_FREGS+(4*8)(r31)
|
|
lfd fp5,_UC_FREGS+(5*8)(r31)
|
|
lfd fp6,_UC_FREGS+(6*8)(r31)
|
|
lfd fp7,_UC_FREGS+(7*8)(r31)
|
|
lfd fp8,_UC_FREGS+(8*8)(r31)
|
|
lfd fp9,_UC_FREGS+(9*8)(r31)
|
|
lfd fp10,_UC_FREGS+(10*8)(r31)
|
|
lfd fp11,_UC_FREGS+(11*8)(r31)
|
|
lfd fp12,_UC_FREGS+(12*8)(r31)
|
|
lfd fp13,_UC_FREGS+(13*8)(r31)
|
|
lfd fp14,_UC_FREGS+(14*8)(r31)
|
|
lfd fp15,_UC_FREGS+(15*8)(r31)
|
|
lfd fp16,_UC_FREGS+(16*8)(r31)
|
|
lfd fp17,_UC_FREGS+(17*8)(r31)
|
|
lfd fp18,_UC_FREGS+(18*8)(r31)
|
|
lfd fp19,_UC_FREGS+(19*8)(r31)
|
|
lfd fp20,_UC_FREGS+(20*8)(r31)
|
|
lfd fp21,_UC_FREGS+(21*8)(r31)
|
|
lfd fp22,_UC_FREGS+(22*8)(r31)
|
|
lfd fp23,_UC_FREGS+(23*8)(r31)
|
|
lfd fp24,_UC_FREGS+(24*8)(r31)
|
|
lfd fp25,_UC_FREGS+(25*8)(r31)
|
|
lfd fp26,_UC_FREGS+(26*8)(r31)
|
|
lfd fp27,_UC_FREGS+(27*8)(r31)
|
|
lfd fp28,_UC_FREGS+(28*8)(r31)
|
|
lfd fp29,_UC_FREGS+(29*8)(r31)
|
|
lfd fp30,_UC_FREGS+(30*8)(r31)
|
|
lfd fp31,_UC_FREGS+(31*8)(r31)
|
|
#endif /* __CONTEXT_ENABLE_FPRS */
|
|
|
|
#ifdef __CONTEXT_ENABLE_E500
|
|
setcontext_e500
|
|
#endif
|
|
|
|
/* Restore LR and CCR, and set CTR to the NIP value */
|
|
lwz r3,_UC_GREGS+(PT_LNK*4)(r31)
|
|
lwz r4,_UC_GREGS+(PT_NIP*4)(r31)
|
|
lwz r5,_UC_GREGS+(PT_CCR*4)(r31)
|
|
mtlr r3
|
|
mtctr r4
|
|
mtcr r5
|
|
|
|
/* Restore the general registers */
|
|
lwz r3,_UC_GREGS+(PT_R3*4)(r31)
|
|
lwz r4,_UC_GREGS+(PT_R4*4)(r31)
|
|
lwz r5,_UC_GREGS+(PT_R5*4)(r31)
|
|
lwz r6,_UC_GREGS+(PT_R6*4)(r31)
|
|
lwz r7,_UC_GREGS+(PT_R7*4)(r31)
|
|
lwz r8,_UC_GREGS+(PT_R8*4)(r31)
|
|
lwz r9,_UC_GREGS+(PT_R9*4)(r31)
|
|
lwz r10,_UC_GREGS+(PT_R10*4)(r31)
|
|
lwz r11,_UC_GREGS+(PT_R11*4)(r31)
|
|
lwz r12,_UC_GREGS+(PT_R12*4)(r31)
|
|
lwz r13,_UC_GREGS+(PT_R13*4)(r31)
|
|
lwz r14,_UC_GREGS+(PT_R14*4)(r31)
|
|
lwz r15,_UC_GREGS+(PT_R15*4)(r31)
|
|
lwz r16,_UC_GREGS+(PT_R16*4)(r31)
|
|
lwz r17,_UC_GREGS+(PT_R17*4)(r31)
|
|
lwz r18,_UC_GREGS+(PT_R18*4)(r31)
|
|
lwz r19,_UC_GREGS+(PT_R19*4)(r31)
|
|
lwz r20,_UC_GREGS+(PT_R20*4)(r31)
|
|
lwz r21,_UC_GREGS+(PT_R21*4)(r31)
|
|
lwz r22,_UC_GREGS+(PT_R22*4)(r31)
|
|
lwz r23,_UC_GREGS+(PT_R23*4)(r31)
|
|
lwz r24,_UC_GREGS+(PT_R24*4)(r31)
|
|
lwz r25,_UC_GREGS+(PT_R25*4)(r31)
|
|
lwz r26,_UC_GREGS+(PT_R26*4)(r31)
|
|
lwz r27,_UC_GREGS+(PT_R27*4)(r31)
|
|
lwz r28,_UC_GREGS+(PT_R28*4)(r31)
|
|
lwz r29,_UC_GREGS+(PT_R29*4)(r31)
|
|
lwz r30,_UC_GREGS+(PT_R30*4)(r31)
|
|
lwz r1,_UC_GREGS+(PT_R1*4)(r31)
|
|
lwz r31,_UC_GREGS+(PT_R31*4)(r31)
|
|
|
|
bctr
|
|
|
|
3:/*L(error_exit):*/
|
|
lwz r0,_FRAME_LR_SAVE+16(r1)
|
|
addi r1,r1,16
|
|
mtlr r0
|
|
blr
|
|
|
|
4:/*L(do_sigret):*/
|
|
addi r1,r4,-0xd0
|
|
li r0,SYS_ify(rt_sigreturn)
|
|
sc
|
|
/* NOTREACHED */
|
|
|
|
END(__CONTEXT_FUNC_NAME)
|